| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 532 FMINNUM, FMAXNUM, enumerator
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| D | BasicTTIImpl.h | 774 ISDs.push_back(ISD::FMAXNUM); in getIntrinsicInstrCost()
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| D | SelectionDAG.h | 1187 case ISD::FMAXNUM:
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 309 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; in mightUseCTR()
376 Opcode = ISD::FMAXNUM; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 721 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal); in PPCTargetLowering()
767 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in PPCTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 206 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SITargetLowering()
224 setTargetDAGCombine(ISD::FMAXNUM); in SITargetLowering()
1711 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
2693 case ISD::FMAXNUM: in minMaxOpcToMin3Max3Opc()
2816 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) || in performMinMaxCombine()
2868 case ISD::FMAXNUM: in PerformDAGCombine()
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| D | AMDGPUISelLowering.cpp | 247 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
409 setOperationAction(ISD::FMAXNUM, VT, Expand); in AMDGPUTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 154 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 78 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult()
1018 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break; in ExpandFloatResult()
1891 case ISD::FMAXNUM: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 304 case ISD::FMAXNUM: in LegalizeOp()
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| D | SelectionDAGBuilder.cpp | 2802 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; in visitSelect()
2805 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) in visitSelect()
2806 Opc = ISD::FMAXNUM; in visitSelect()
2810 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ? in visitSelect()
2811 ISD::FMAXNUM : ISD::FMAXNAN; in visitSelect()
5222 : ISD::FMAXNUM; in visitIntrinsicCall()
6255 if (visitBinaryFloatCall(I, ISD::FMAXNUM)) in visitCall()
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| D | LegalizeVectorTypes.cpp | 111 case ISD::FMAXNUM: in ScalarizeVectorResult()
676 case ISD::FMAXNUM: in SplitVectorResult()
2092 case ISD::FMAXNUM: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 3807 case ISD::FMAXNUM: in ConvertNodeToLibcall()
4185 case ISD::FMAXNUM: in PromoteNode()
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| D | DAGCombiner.cpp | 1423 case ISD::FMAXNUM: return visitFMAXNUM(N); in visit()
5049 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM; in combineMinNumMaxNum()
5060 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM; in combineMinNumMaxNum()
9385 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), VT, N1, N0); in visitFMAXNUM()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 293 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in AArch64TargetLowering()
385 setOperationAction(ISD::FMAXNUM, Ty, Legal); in AArch64TargetLowering()
705 ISD::FMINNUM, ISD::FMAXNUM}) in addTypeForNEON()
8561 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
8952 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) { in tryMatchAcrossLaneShuffleForReduction()
9029 case ISD::FMAXNUM: in tryMatchAcrossLaneShuffleForReduction()
9098 Op != ISD::UMIN && Op != ISD::FMAXNUM && Op != ISD::FMINNUM) in performAcrossLaneMinMaxReductionCombine()
9109 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) { in performAcrossLaneMinMaxReductionCombine()
9133 (Op == ISD::FMAXNUM && CC != ISD::SETOGT && CC != ISD::SETOGE && in performAcrossLaneMinMaxReductionCombine()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 869 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 435 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 995 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in ARMTargetLowering()
997 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal); in ARMTargetLowering()
999 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1009 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in ARMTargetLowering()
2969 ? ISD::FMINNUM : ISD::FMAXNUM; in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1949 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 632 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand); in X86TargetLowering()
1648 setTargetDAGCombine(ISD::FMAXNUM); in X86TargetLowering()
29886 auto MinMaxOp = N->getOpcode() == ISD::FMAXNUM ? X86ISD::FMAX : X86ISD::FMIN; in combineFMinNumFMaxNum()
30981 case ISD::FMAXNUM: return combineFMinNumFMaxNum(N, DAG, Subtarget); in PerformDAGCombine()
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