| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 426 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
430 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
434 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
438 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
443 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
447 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
451 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
455 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 147 case ISD::SDIV: in Select()
155 if (N->getOpcode() == ISD::SDIV) { in Select()
165 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; in Select()
|
| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 98 if (ISD == ISD::SDIV && in getArithmeticInstrCost()
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
224 { ISD::SDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
225 { ISD::SDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost()
226 { ISD::SDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost()
227 { ISD::SDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
273 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence in getArithmeticInstrCost()
275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence in getArithmeticInstrCost()
282 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) in getArithmeticInstrCost()
[all …]
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 339 case ISD::SDIV: in Select()
350 if (N->getOpcode() == ISD::SDIV) { in Select()
362 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; in Select()
|
| D | LeonFeatures.td | 39 "AT697E erratum fix: Do not emit SDIV, emit SDIVCC instead">;
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiTargetTransformInfo.h | 71 case ISD::SDIV:
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelDAGToDAG.cpp | 133 case ISD::SDIV: { in Select()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 99 setOperationAction(ISD::SDIV , MVT::i64, Custom); in AlphaTargetLowering()
691 case ISD::SDIV: in LowerOperation()
695 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL) in LowerOperation()
702 case ISD::SDIV: opstr = "__divq"; break; in LowerOperation()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 79 setOperationAction(ISD::SDIV, MVT::i16, Expand); in BlackfinTargetLowering()
80 setOperationAction(ISD::SDIV, MVT::i32, Expand); in BlackfinTargetLowering()
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-rm-a32.json | 43 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
|
| D | cond-rd-rn-rm-t32.json | 42 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1674 case ISD::SDIV: in selectDivRem()
1676 DivOpc = Mips::SDIV; in selectDivRem()
1791 if (!selectBinaryOp(I, ISD::SDIV)) in fastSelectInstruction()
1792 return selectDivRem(I, ISD::SDIV); in fastSelectInstruction()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 142 case ISD::SDIV: in LegalizeOp()
|
| D | FastISel.cpp | 373 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) && in SelectBinaryOp()
898 return SelectBinaryOp(I, ISD::SDIV); in SelectOperator()
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 98 setOperationAction(ISD::SDIV, MVT::i32, Expand); in SystemZTargetLowering()
100 setOperationAction(ISD::SDIV, MVT::i64, Expand); in SystemZTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 182 setOperationAction(ISD::SDIV, MVT::i8, Expand); in SPUTargetLowering()
188 setOperationAction(ISD::SDIV, MVT::i16, Expand); in SPUTargetLowering()
194 setOperationAction(ISD::SDIV, MVT::i32, Expand); in SPUTargetLowering()
200 setOperationAction(ISD::SDIV, MVT::i64, Expand); in SPUTargetLowering()
206 setOperationAction(ISD::SDIV, MVT::i128, Expand); in SPUTargetLowering()
422 setOperationAction(ISD::SDIV, VT, Expand); in SPUTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 156 setOperationAction(ISD::SDIV, MVT::i8, Expand); in MSP430TargetLowering()
162 setOperationAction(ISD::SDIV, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 383 if (ISD == ISD::SDIV && in getArithmeticInstrCost()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 180 case ISD::SDIV: return "sdiv"; in getOperationName()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 109 #define SDIV 0x9ac00c00 macro
1267 …FAIL_IF(push_inst(compiler, ((op == SLJIT_DIVMOD_UW ? UDIV : SDIV) ^ inv_bits) | RD(SLJIT_R0) | RN… in sljit_emit_op0()
1272 …return push_inst(compiler, ((op == SLJIT_DIV_UW ? UDIV : SDIV) ^ inv_bits) | RD(SLJIT_R0) | RN(SLJ… in sljit_emit_op0()
|
| D | sljitNativeSPARC_common.c | 175 #define SDIV (OPC1(0x2) | OPC3(0x0f)) macro
798 …FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? UDIV : SDIV) | D(SLJIT_R0) | S1(SLJIT_R0… in sljit_emit_op0()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 149 setOperationAction(ISD::SDIV, MVT::i8, Expand); in MSP430TargetLowering()
155 setOperationAction(ISD::SDIV, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 968 case ISD::SDIV: in canOpTrap()
1679 case SDiv: return ISD::SDIV; in InstructionOpcodeToISD()
|