| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | invalid-SXTB-arm.txt | 9 # A8.6.223 SXTB
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| D | thumb1.txt | 494 # SXTB/SXTH
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| D | thumb2.txt | 2006 # SXTB
2060 # SXTB
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 45 SXTB, enumerator
64 case AArch64_AM::SXTB: return "sxtb"; in getShiftExtendName()
131 case 4: return AArch64_AM::SXTB; in getExtendType()
158 case AArch64_AM::SXTB: return 4; break; in getExtendEncoding()
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| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-rn-t32.json | 54 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> ; T1
55 // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-ror-amount-t32.json | 32 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-ror-amount-a32.json | 32 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| D | cond-rd-operand-rn-a32.json | 46 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
|
| D | invalid-armv7.txt | 330 # A8.6.223 SXTB
|
| D | thumb2.txt | 2157 # SXTB
2211 # SXTB
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 364 SXTB, enumerator
|
| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 312 VIXL_CHECK(!Operand(w12, SXTB).IsPlainRegister()); in TEST()
|
| D | test-assembler-aarch64.cc | 382 __ Add(sp, sp, Operand(x17, SXTB)); in TEST()
429 __ Mvn(x11, Operand(x2, SXTB, 1)); in TEST()
604 __ Mov(x24, Operand(x13, SXTB, 1)); in TEST()
658 __ Mov(w20, Operand(w11, SXTB, 1)); in TEST()
742 __ Orr(w10, w0, Operand(w1, SXTB)); in TEST()
836 __ Orn(w10, w0, Operand(w1, SXTB)); in TEST()
903 __ And(w10, w0, Operand(w1, SXTB)); in TEST()
1041 __ Bic(w10, w0, Operand(w1, SXTB)); in TEST()
1165 __ Eor(w10, w0, Operand(w1, SXTB)); in TEST()
1232 __ Eon(w10, w0, Operand(w1, SXTB)); in TEST()
[all …]
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| D | test-disasm-aarch64.cc | 435 COMPARE(adds(w15, w16, Operand(w17, SXTB, 4)), "adds w15, w16, w17, sxtb #4"); in TEST()
436 COMPARE(add(x18, x19, Operand(x20, SXTB, 3)), "add x18, x19, w20, sxtb #3"); in TEST()
461 COMPARE(subs(w15, w16, Operand(w17, SXTB, 4)), "subs w15, w16, w17, sxtb #4"); in TEST()
462 COMPARE(sub(x18, x19, Operand(x20, SXTB, 3)), "sub x18, x19, w20, sxtb #3"); in TEST()
466 COMPARE(cmp(w0, Operand(w1, SXTB, 1)), "cmp w0, w1, sxtb #1"); in TEST()
2409 COMPARE_MACRO(Csel(x12, Operand(x13, LSL, 13), Operand(x14, SXTB), eq), in TEST()
2415 Operand(x14, SXTB), in TEST()
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 587 @ SXTB/SXTH
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 343 SXTB = 4, enumerator
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 159 #define SXTB 0xb240 macro
701 return push_inst16(compiler, SXTB | RD3(dst) | RN3(arg2)); in emit_op_imm()
|
| D | sljitNativeARM_32.c | 121 #define SXTB 0xe6af0070 macro
1014 return push_inst(compiler, (op == SLJIT_MOV_U8 ? UXTB : SXTB) | RD(dst) | RM(src2)); in emit_single_op()
|
| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 119 return Operand(InputRegister32(index), SXTB); in InputOperand2_32()
149 return Operand(InputRegister64(index), SXTB); in InputOperand2_64()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2641 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2886 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
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| D | ARMScheduleSwift.td | 157 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 290 SXTB = 4, enumerator
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 988 return (ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB || in isExtend()
2393 .Case("sxtb", AArch64_AM::SXTB) in tryParseOptionalShiftExtend()
|