| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrSystem.td | 17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
30 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
47 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
48 def SYSRETL : I<0x07, RawFrm, (outs), (ins), "sysretl", []>, TB;
49 def SYSRETQ :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
52 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
54 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
[all …]
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| D | X86InstrVMX.td | 29 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
31 "vmclear\t$vmcs", []>, OpSize, TB;
33 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
35 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
37 "vmptrld\t$vmcs", []>, TB;
39 "vmptrst\t$vmcs", []>, TB;
41 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
43 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
45 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
47 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
[all …]
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| D | X86InstrExtension.td | 42 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
44 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
47 [(set GR32:$dst, (sext GR8:$src))]>, TB;
50 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
53 [(set GR32:$dst, (sext GR16:$src))]>, TB;
56 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
59 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
61 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
64 [(set GR32:$dst, (zext GR8:$src))]>, TB;
67 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
[all …]
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| D | X86InstrCMovSetCC.td | 24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,TB,OpSize;
29 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>, TB;
34 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
42 CondNode, EFLAGS))]>, TB, OpSize;
47 CondNode, EFLAGS))]>, TB;
52 CondNode, EFLAGS))]>, TB;
81 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))]>, TB;
84 [(store (X86setcc OpNode, EFLAGS), addr:$dst)]>, TB;
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| D | X86InstrInfo.td | 648 "nop{w}\t$zero", []>, TB, OpSize;
650 "nop{l}\t$zero", []>, TB;
760 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
764 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
771 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
774 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
778 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
781 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
784 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
787 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
[all …]
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| D | X86InstrFormats.td | 94 class TB { bits<5> Prefix = 1; }
304 // PSI - SSE1 instructions with TB prefix.
305 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
307 // VPSI - SSE1 instructions with TB prefix in AVX form.
315 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
319 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
327 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>, TB,
335 // PDI - SSE2 instructions with TB and OpSize prefixes.
336 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
338 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrSystem.td | 19 TB;
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
27 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
51 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
52 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
53 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
57 IIC_SYS_ENTER_EXIT>, TB;
60 IIC_SYS_ENTER_EXIT>, TB;
[all …]
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| D | X86InstrSVM.td | 19 def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
22 def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
25 def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
29 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
34 "vmrun\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
37 "vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
42 "vmload\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
45 "vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
50 "vmsave\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
53 "vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
[all …]
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| D | X86InstrExtension.td | 45 TB, OpSize16, Sched<[WriteALU]>;
49 TB, OpSize16, Sched<[WriteALULd]>;
53 [(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB,
57 [(set GR32:$dst, (sextloadi32i8 addr:$src))], IIC_MOVSX>, TB,
61 [(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB,
66 OpSize32, TB, Sched<[WriteALULd]>;
71 TB, OpSize16, Sched<[WriteALU]>;
75 TB, OpSize16, Sched<[WriteALULd]>;
79 [(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB,
83 [(set GR32:$dst, (zextloadi32i8 addr:$src))], IIC_MOVZX>, TB,
[all …]
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| D | X86InstrVMX.td | 33 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
37 def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
39 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
41 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
45 "vmptrst\t$vmcs", []>, TB;
63 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
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| D | X86InstrCMovSetCC.td | 25 IIC_CMOV16_RR>, TB, OpSize16;
31 IIC_CMOV32_RR>, TB, OpSize32;
37 IIC_CMOV32_RR>, TB;
47 TB, OpSize16;
53 TB, OpSize32;
58 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
88 IIC_SET_R>, TB, Sched<[WriteALU]>;
92 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
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| /external/cblas/src/ |
| D | cblas_sgemm.c | 18 char TA, TB; in cblas_sgemm() local
23 #define F77_TB &TB in cblas_sgemm()
56 if(TransB == CblasTrans) TB='T'; in cblas_sgemm()
57 else if ( TransB == CblasConjTrans ) TB='C'; in cblas_sgemm()
58 else if ( TransB == CblasNoTrans ) TB='N'; in cblas_sgemm()
70 F77_TB = C2F_CHAR(&TB); in cblas_sgemm()
77 if(TransA == CblasTrans) TB='T'; in cblas_sgemm()
78 else if ( TransA == CblasConjTrans ) TB='C'; in cblas_sgemm()
79 else if ( TransA == CblasNoTrans ) TB='N'; in cblas_sgemm()
101 F77_TB = C2F_CHAR(&TB); in cblas_sgemm()
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| D | cblas_cgemm.c | 18 char TA, TB; in cblas_cgemm() local
23 #define F77_TB &TB in cblas_cgemm()
56 if(TransB == CblasTrans) TB='T'; in cblas_cgemm()
57 else if ( TransB == CblasConjTrans ) TB='C'; in cblas_cgemm()
58 else if ( TransB == CblasNoTrans ) TB='N'; in cblas_cgemm()
69 F77_TB = C2F_CHAR(&TB); in cblas_cgemm()
77 if(TransA == CblasTrans) TB='T'; in cblas_cgemm()
78 else if ( TransA == CblasConjTrans ) TB='C'; in cblas_cgemm()
79 else if ( TransA == CblasNoTrans ) TB='N'; in cblas_cgemm()
99 F77_TB = C2F_CHAR(&TB); in cblas_cgemm()
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| D | cblas_zgemm.c | 18 char TA, TB; in cblas_zgemm() local
23 #define F77_TB &TB in cblas_zgemm()
56 if(TransB == CblasTrans) TB='T'; in cblas_zgemm()
57 else if ( TransB == CblasConjTrans ) TB='C'; in cblas_zgemm()
58 else if ( TransB == CblasNoTrans ) TB='N'; in cblas_zgemm()
69 F77_TB = C2F_CHAR(&TB); in cblas_zgemm()
77 if(TransA == CblasTrans) TB='T'; in cblas_zgemm()
78 else if ( TransA == CblasConjTrans ) TB='C'; in cblas_zgemm()
79 else if ( TransA == CblasNoTrans ) TB='N'; in cblas_zgemm()
99 F77_TB = C2F_CHAR(&TB); in cblas_zgemm()
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| D | cblas_dgemm.c | 18 char TA, TB; in cblas_dgemm() local
23 #define F77_TB &TB in cblas_dgemm()
56 if(TransB == CblasTrans) TB='T'; in cblas_dgemm()
57 else if ( TransB == CblasConjTrans ) TB='C'; in cblas_dgemm()
58 else if ( TransB == CblasNoTrans ) TB='N'; in cblas_dgemm()
69 F77_TB = C2F_CHAR(&TB); in cblas_dgemm()
77 if(TransA == CblasTrans) TB='T'; in cblas_dgemm()
78 else if ( TransA == CblasConjTrans ) TB='C'; in cblas_dgemm()
79 else if ( TransA == CblasNoTrans ) TB='N'; in cblas_dgemm()
99 F77_TB = C2F_CHAR(&TB); in cblas_dgemm()
|
| /external/tensorflow/tensorflow/core/kernels/ |
| D | matmul_op_test.cc | 36 #define BM_MatmulDev(M, K, N, TA, TB, T, TFTYPE, DEVICE) \ argument
37 static void BM_Matmul##_##M##_##K##_##N##_##TA##_##TB##_##TFTYPE##_##DEVICE( \
41 test::Benchmark(#DEVICE, Matmul<T>(M, K, N, TA, TB, TFTYPE)).Run(iters); \
43 BENCHMARK(BM_Matmul##_##M##_##K##_##N##_##TA##_##TB##_##TFTYPE##_##DEVICE);
45 #define BM_Matmul(M, K, N, TA, TB) \ argument
46 BM_MatmulDev(M, K, N, TA, TB, float, DT_FLOAT, cpu); \
47 BM_MatmulDev(M, K, N, TA, TB, std::complex<float>, DT_COMPLEX64, cpu); \
48 BM_MatmulDev(M, K, N, TA, TB, float, DT_FLOAT, gpu); \
49 BM_MatmulDev(M, K, N, TA, TB, std::complex<float>, DT_COMPLEX64, gpu); \
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| D | sparse_tensor_dense_matmul_op_test.cc | 71 #define BM_SparseTensorDenseMatmulDev(NNZ, M, K, N, TA, TB, DEVICE) \ argument
73 BM_SparseTensorDenseMatmul##_##NNZ##_##M##_##K##_##N##_##TA##_##TB##_##DEVICE( \
75 int64 items_per_iter = (static_cast<int64>(NNZ) * (TB ? K : N)); \
79 test::Benchmark(#DEVICE, SparseTensorDenseMatmul(NNZ, M, K, N, TA, TB)) \
83 BM_SparseTensorDenseMatmul##_##NNZ##_##M##_##K##_##N##_##TA##_##TB##_##DEVICE);
85 #define BM_SparseTensorDenseMatmul(NNZ, M, K, N, TA, TB) \ argument
86 BM_SparseTensorDenseMatmulDev(NNZ, M, K, N, TA, TB, cpu); \
87 BM_SparseTensorDenseMatmulDev(NNZ, M, K, N, TA, TB, gpu);
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| D | batch_matmul_op_test.cc | 36 #define BM_BatchMatmulDev(B, M, K, N, TA, TB, T, TFTYPE, DEVICE) \ argument
38 BM_BatchMatmul##_##B##_##M##_##K##_##N##_##TA##_##TB##_##TFTYPE##_##DEVICE( \
42 test::Benchmark(#DEVICE, BatchMatmul<T>(B, M, K, N, TA, TB, TFTYPE)) \
46 BM_BatchMatmul##_##B##_##M##_##K##_##N##_##TA##_##TB##_##TFTYPE##_##DEVICE);
48 #define BM_BatchMatmul(B, M, K, N, TA, TB) \ argument
49 BM_BatchMatmulDev(B, M, K, N, TA, TB, float, DT_FLOAT, cpu);
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| D | sparse_matmul_op_test.cc | 65 template <typename TA, typename TB>
78 Tensor right(DataTypeToEnum<TB>::value, right_shape); in SparseMatMulHelper()
79 right.flat<TB>().setRandom(); in SparseMatMulHelper()
80 Sparsify<TB>(&right, sparsity_b); in SparseMatMulHelper()
88 template <typename TA, typename TB>
93 return SparseMatMulHelper<TA, TB>(g, m, n, d, sparsity_a, sparsity_b, in SparseMatMul()
107 #define BM_SPARSE(M, K, N, S1, S2, TRA, TRB, TA, TB) \ argument
109 BM_Sparse##_##M##_##K##_##N##_##S1##_##S2##_##TRA##_##TRB##_##TA##_##TB( \
117 auto g = SparseMatMul<TA, TB>(M, N, K, S1 / 100.0, S2 / 100.0, TRA, TRB); \
122 BM_Sparse##_##M##_##K##_##N##_##S1##_##S2##_##TRA##_##TRB##_##TA##_##TB);
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| /external/icu/icu4c/source/data/unit/ |
| D | mt.txt | 126 dnam{"TB"}
127 few{"{0} TB"}
128 many{"{0} TB"}
129 one{"{0} TB"}
130 other{"{0} TB"}
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| /external/clang/test/CXX/special/class.dtor/ |
| D | p3-0x.cpp | 66 struct TB { struct
67 ~TB() throw(int);
72 TB<T> b;
114 TB<T> b;
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| /external/autotest/client/site_tests/firmware_TouchMTB/ |
| D | test_conf.py | 420 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
427 GV.TB: ('vertical', 'from top to bottom',),
475 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
483 GV.TB: ('vertical', 'from top to bottom',),
508 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
517 GV.TB: ('from top to bottom',
557 variations=(GV.TB, GV.BT),
560 GV.TB: ('from top to bottom',),
721 variations=(GV.LR, GV.RL, GV.TB, GV.BT),
727 GV.TB: ('center', 'from top to bottom', 'on the right to'),
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 438 MachineBasicBlock *TB = nullptr, *FB = nullptr; in findInductionRegister() local
439 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); in findInductionRegister()
585 MachineBasicBlock *TB = nullptr, *FB = nullptr; in getLoopTripCount() local
586 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); in getLoopTripCount()
594 assert (TB && "Exit block without a branch?"); in getLoopTripCount()
595 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { in getLoopTripCount()
601 if (TB == Latch) in getLoopTripCount()
602 TB = (LTB == Header) ? LTB : LFB; in getLoopTripCount()
606 assert ((!FB || TB == Header || FB == Header) && "Branches not to header?"); in getLoopTripCount()
607 if (!TB || (FB && TB != Header && FB != Header)) in getLoopTripCount()
[all …]
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| D | HexagonEarlyIfConv.cpp | 107 FlowPattern(MachineBasicBlock *B, unsigned PR, MachineBasicBlock *TB, in FlowPattern()
109 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {} in FlowPattern()
220 MachineBasicBlock *TB = 0, *FB = 0; in matchFlowPattern() local
251 TB = T1B, FB = T2B; in matchFlowPattern()
253 TB = T2B, FB = T1B; in matchFlowPattern()
255 if (!MDT->properlyDominates(B, TB) || !MDT->properlyDominates(B, FB)) in matchFlowPattern()
262 unsigned TNP = TB->pred_size(), FNP = FB->pred_size(); in matchFlowPattern()
263 unsigned TNS = TB->succ_size(), FNS = FB->succ_size(); in matchFlowPattern()
276 MachineBasicBlock *TSB = (TNS > 0) ? *TB->succ_begin() : 0; in matchFlowPattern()
294 if (FSB == TB) { in matchFlowPattern()
[all …]
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| /external/v8/tools/clang/blink_gc_plugin/tests/legacy_naming/ |
| D | virtual_and_trace_after_dispatch.h | 17 enum Type { TB }; enumerator
25 B() : A(TB) { } in B()
|