| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 42 UXTW, enumerator
62 case AArch64_AM::UXTW: return "uxtw"; in getShiftExtendName()
129 case 2: return AArch64_AM::UXTW; in getExtendType()
156 case AArch64_AM::UXTW: return 2; break; in getExtendEncoding()
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.cc | 368 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); in ToExtendedRegister()
407 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
468 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
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| D | disasm-aarch64.cc | 4811 (((instr->GetExtendMode() == UXTW) && (instr->GetSixtyFourBits() == 0)) || in SubstituteExtendField()
4841 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| D | constants-aarch64.h | 288 UXTW = 2, enumerator
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| D | simulator-aarch64.cc | 394 case UXTW: in ExtendValue()
1287 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 433 COMPARE(adds(x9, x10, Operand(x11, UXTW, 3)), "adds x9, x10, w11, uxtw #3"); in TEST()
445 COMPARE(add(wsp, wsp, Operand(w4, UXTW, 2)), "add wsp, wsp, w4, lsl #2"); in TEST()
459 COMPARE(subs(x9, x10, Operand(x11, UXTW, 3)), "subs x9, x10, w11, uxtw #3"); in TEST()
471 COMPARE(sub(wsp, wsp, Operand(w4, UXTW, 2)), "sub wsp, wsp, w4, lsl #2"); in TEST()
1057 COMPARE(ldr(w0, MemOperand(x1, w2, UXTW)), "ldr w0, [x1, w2, uxtw]"); in TEST()
1058 COMPARE(ldr(w3, MemOperand(x4, w5, UXTW, 2)), "ldr w3, [x4, w5, uxtw #2]"); in TEST()
1067 COMPARE(ldr(x0, MemOperand(x1, w2, UXTW)), "ldr x0, [x1, w2, uxtw]"); in TEST()
1068 COMPARE(ldr(x3, MemOperand(x4, w5, UXTW, 3)), "ldr x3, [x4, w5, uxtw #3]"); in TEST()
1078 COMPARE(str(w0, MemOperand(x1, w2, UXTW)), "str w0, [x1, w2, uxtw]"); in TEST()
1079 COMPARE(str(w3, MemOperand(x4, w5, UXTW, 2)), "str w3, [x4, w5, uxtw #2]"); in TEST()
[all …]
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| D | test-simulator-aarch64.cc | 229 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); in Test1Op_Helper()
351 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in Test2Op_Helper()
355 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in Test2Op_Helper()
486 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in Test3Op_Helper()
490 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in Test3Op_Helper()
494 __ Ldr(fa, MemOperand(inputs_base, index_a, UXTW, index_shift)); in Test3Op_Helper()
633 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in TestCmp_Helper()
637 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in TestCmp_Helper()
770 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in TestCmpZero_Helper()
897 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); in TestFPToFixed_Helper()
[all …]
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| D | test-api-aarch64.cc | 317 VIXL_CHECK(!Operand(w15, UXTW).IsPlainRegister()); in TEST()
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| D | test-assembler-aarch64.cc | 432 __ Mvn(x14, Operand(w2, UXTW, 4)); in TEST()
607 __ Mov(x27, Operand(w13, UXTW, 4)); in TEST()
668 __ Mov(x29, Operand(x12, UXTW, 1)); in TEST()
740 __ Orr(w8, w0, Operand(w1, UXTW, 2)); in TEST()
834 __ Orn(w8, w0, Operand(w1, UXTW, 2)); in TEST()
901 __ And(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1039 __ Bic(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1163 __ Eor(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1230 __ Eon(w8, w0, Operand(w1, UXTW, 2)); in TEST()
3088 __ Ldr(h3, MemOperand(x17, x18, UXTW, 1)); in TEST()
[all …]
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 438 __ Ldr(result, MemOperand(buffer, offset, UXTW)); \
450 __ asm_instr(result, MemOperand(buffer, offset, UXTW)); \
462 __ asm_instr(result, MemOperand(buffer, offset, UXTW)); \
474 __ Str(value, MemOperand(buffer, offset, UXTW)); \
486 __ asm_instr(value, MemOperand(buffer, offset, UXTW)); \
498 __ asm_instr(value, MemOperand(buffer, offset, UXTW)); \
1800 __ Add(temp, temp, Operand(input, UXTW, 2)); in AssembleArchTableSwitch()
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| /external/v8/src/regexp/arm64/ |
| D | regexp-macro-assembler-arm64.cc | 191 __ Add(x10, code_pointer(), Operand(w10, UXTW)); in Backtrack()
581 __ Ldrb(w11, MemOperand(x11, w10, UXTW)); in CheckBitInTable()
662 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); in CheckSpecialCharacterClass()
675 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); in CheckSpecialCharacterClass()
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| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 383 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
466 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
519 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
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| D | disasm-arm64.cc | 1647 (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) || in SubstituteExtendField()
1671 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| D | constants-arm64.h | 341 UXTW = 2, enumerator
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| D | simulator-arm64.cc | 983 case UXTW: in ExtendValue()
1615 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | code-stubs-arm64.cc | 1537 __ Add(x2, start, Operand(w10, UXTW)); in Generate()
1542 __ Add(x3, x2, Operand(w10, UXTW)); in Generate()
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| D | assembler-arm64.cc | 2502 case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
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| D | macro-assembler-arm64.cc | 1070 PushPreamble(Operand(count, UXTW, WhichPowerOf2(src.SizeInBytes()))); in PushMultipleTimes()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 361 UXTW, enumerator
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 670 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
694 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
754 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
791 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
813 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
991 Addr.getExtendType() == AArch64_AM::UXTW ) in simplifyAddress()
1002 if (Addr.getExtendType() == AArch64_AM::UXTW) in simplifyAddress()
1770 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitLoad()
2037 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitStore()
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| D | AArch64ISelDAGToDAG.cpp | 393 return AArch64_AM::UXTW; in getExtendTypeForNode()
411 return AArch64_AM::UXTW; in getExtendTypeForNode()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1104 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1110 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 990 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
1025 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
1561 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
2391 .Case("uxtw", AArch64_AM::UXTW) in tryParseOptionalShiftExtend()
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| /external/v8/src/crankshaft/arm64/ |
| D | lithium-codegen-arm64.cc | 1337 __ Ldr(result, MemOperand(arguments, result, UXTW, kPointerSizeLog2)); in DoAccessArgumentsAt()
1339 __ Ldr(result, MemOperand(arguments, length, UXTW, kPointerSizeLog2)); in DoAccessArgumentsAt()
1346 __ Ldr(result, MemOperand(arguments, result, UXTW, kPointerSizeLog2)); in DoAccessArgumentsAt()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1392 ### UXTW ### subsection
|