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Searched refs:nblk_y (Results 1 – 18 of 18) sorted by relevance

/external/libdrm/radeon/
Dradeon_surface.c180 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in surf_minify()
184 if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) { in surf_minify()
190 surflevel->nblk_y = ALIGN(surflevel->nblk_y, yalign); in surf_minify()
195 surflevel->slice_size = (uint64_t)surflevel->pitch_bytes * surflevel->nblk_y; in surf_minify()
589 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in eg_surf_minify()
593 if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) { in eg_surf_minify()
599 surflevel->nblk_y = ALIGN(surflevel->nblk_y, mtileh); in eg_surf_minify()
605 mtile_ps = (mtile_pr * surflevel->nblk_y) / mtileh; in eg_surf_minify()
1440 surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h; in si_surf_minify()
1444 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in si_surf_minify()
[all …]
Dradeon_surface.h76 uint32_t nblk_y; member
/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_surface.c76 level_drm->nblk_y = level_ws->nblk_y; in surf_level_winsys_to_drm()
88 level_ws->nblk_y = level_drm->nblk_y; in surf_level_drm_to_winsys()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_dma.c171 rtiled->surface.level[tiled_lvl].nblk_y) / (8*8) - 1; in si_dma_copy_tile()
177 height = rtiled->surface.level[tiled_lvl].nblk_y; in si_dma_copy_tile()
283 rsrc->surface.level[src_level].nblk_y != in si_dma_copy()
284 rdst->surface.level[dst_level].nblk_y) { in si_dma_copy()
Dsi_state.c2313 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); in si_init_depth_surface()
2324 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1); in si_init_depth_surface()
2326 levelinfo->nblk_y) / 64 - 1); in si_init_depth_surface()
2548 level_info->nblk_y / 64 - 1; in si_emit_framebuffer_state()
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vce_40_2_2.c99 RVCE_CS(align(enc->luma->level[0].nblk_y, 16) / 8); // encRefYHeightInQw in create()
326 RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch in encode()
Dradeon_vce.c228 unsigned vpitch = align(enc->luma->level[0].nblk_y, 16); in rvce_frame_offset()
460 cpb_size = cpb_size * align(tmp_surf->level[0].nblk_y, 32); in rvce_create_encoder()
Dradeon_vce_50.c133 RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch in encode()
Dradeon_winsys.h293 uint16_t nblk_y; member
Dradeon_vce_52.c182 RVCE_CS(align(enc->luma->level[0].nblk_y, 16) / 8); // encRefYHeightInQw in create()
246 RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch in encode()
Dr600_texture.c271 surface->level[0].slice_size = pitch_in_bytes_override * surface->level[0].nblk_y; in r600_init_surface()
636 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64; in r600_texture_get_fmask_info()
959 rtex->surface.level[i].nblk_y, in r600_print_texture_info()
977 rtex->surface.stencil_level[i].nblk_y, in r600_print_texture_info()
/external/mesa3d/src/amd/vulkan/
Dradv_radeon_winsys.h163 uint32_t nblk_y; member
Dradv_image.c494 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64; in radv_image_get_fmask_info()
745 image->surface.level[0].slice_size = create_info->stride * image->surface.level[0].nblk_y; in radv_image_create()
Dradv_device.c1616 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1; in radv_initialise_color_surface()
1837 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1); in radv_initialise_ds_surface()
1838 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1); in radv_initialise_ds_surface()
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.c210 surf_level->nblk_y = AddrSurfInfoOut->height; in radv_compute_level()
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c195 surf_level->nblk_y = AddrSurfInfoOut->height; in compute_level()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_state.c832 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; in r600_init_color_surface()
1027 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; in r600_init_depth_surface()
1050 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1; in r600_init_depth_surface()
2838 …slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) /… in r600_dma_copy_tile()
2857 …slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) /… in r600_dma_copy_tile()
Devergreen_state.c1007 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; in evergreen_init_color_surface()
1214 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); in evergreen_init_depth_surface()
1220 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1); in evergreen_init_depth_surface()
1222 levelinfo->nblk_y / 64 - 1); in evergreen_init_depth_surface()
3377 …slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) /… in evergreen_dma_copy_tile()
3402 …slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) /… in evergreen_dma_copy_tile()