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Searched refs:rrx (Results 1 – 25 of 45) sorted by relevance

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/external/llvm/test/MC/ARM/
Darm-shift-encoding.s10 ldr r0, [r0, r0, rrx]
20 @ CHECK: ldr r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x90,0xe7]
30 pld [r0, r0, rrx]
40 @ CHECK: [r0, r0, rrx] @ encoding: [0x60,0xf0,0xd0,0xf7]
50 str r0, [r0, r0, rrx]
60 @ CHECK: str r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x80,0xe7]
68 ldr r0, [r1], r2, rrx
73 @ CHECK: ldr r0, [r1], r2, rrx @ encoding: [0x62,0x00,0x91,0xe6]
88 adc r7, r2, r12, rrx
98 @ CHECK: adc r7, r2, r12, rrx @ encoding: [0x6c,0x70,0xa2,0xe0]
[all …]
Dthumb-shift-encoding.s14 sbc.w r7, r2, r12, rrx
24 @ CHECK: sbc.w r7, r2, r12, rrx @ encoding: [0x62,0xeb,0x3c,0x07]
34 and.w r7, r2, r12, rrx
44 @ CHECK: and.w r7, r2, r12, rrx @ encoding: [0x02,0xea,0x3c,0x07]
Dbasic-arm-instructions.s86 adc r4, r5, r6, rrx
100 adc r4, r5, rrx
105 adc r4, r5, rrx
124 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
137 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
142 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
205 add r4, r5, r6, rrx
229 add r4, r5, rrx
261 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
284 @ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0]
[all …]
/external/capstone/suite/MC/ARM/
Darm-shift-encoding.s.cs9 0x60,0x00,0x90,0xe7 = ldr r0, [r0, r0, rrx]
18 0x60,0xf0,0xd0,0xf7 = pld [r0, r0, rrx]
27 0x60,0x00,0x80,0xe7 = str r0, [r0, r0, rrx]
29 0x62,0x00,0x91,0xe6 = ldr r0, [r1], r2, rrx
40 0x6c,0x70,0xa2,0xe0 = adc r7, r2, r12, rrx
49 0x62,0x00,0x57,0xe1 = cmp r7, r2, rrx
Dbasic-arm-instructions.s.cs29 0x66,0x40,0xa5,0xe0 = adc r4, r5, r6, rrx
41 0x65,0x40,0xa4,0xe0 = adc r4, r4, r5, rrx
46 0x65,0x40,0xa4,0xe0 = adc r4, r4, r5, rrx
59 0x66,0x40,0x85,0xe0 = add r4, r5, r6, rrx
71 0x65,0x40,0x84,0xe0 = add r4, r4, r5, rrx
87 0x66,0xa0,0x01,0xe0 = and r10, r1, r6, rrx
100 0x61,0xa0,0x0a,0xe0 = and r10, r10, r1, rrx
122 0x66,0xa0,0xc1,0xe1 = bic r10, r1, r6, rrx
134 0x61,0xa0,0xca,0xe1 = bic r10, r10, r1, rrx
166 0x66,0x00,0x71,0xe1 = cmn r1, r6, rrx
[all …]
Dthumb-shift-encoding.s.cs9 0x62,0xeb,0x3c,0x07 = sbc.w r7, r2, r12, rrx
18 0x02,0xea,0x3c,0x07 = and.w r7, r2, r12, rrx
Dbasic-thumb2-instructions.s.cs475 0x4f,0xea,0x34,0x04 = rrx r4, r4
527 0x6f,0xea,0x36,0x05 = mvn.w r5, r6, rrx
636 0x4f,0xea,0x32,0x01 = rrx r1, r2
984 0xa2,0xeb,0x3c,0x05 = sub.w r5, r2, r12, rrx
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dthumb2-lsr3.ll6 ; CHECK: rrx r0, r0
15 ; CHECK: rrx r0, r0
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-lsr3.ll6 ; CHECK: rrx r0, r0
15 ; CHECK: rrx r0, r0
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s66 adc r4, r5, r6, rrx
80 adc r4, r5, rrx
85 adc r4, r5, rrx
104 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
117 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
122 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
159 add r4, r5, r6, rrx
173 add r4, r5, rrx
186 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
200 @ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0]
[all …]
/external/llvm/test/CodeGen/ARM/
Dlong_shift.ll7 ; CHECK-LE-NEXT: rrx r2, r2
11 ; CHECK-BE-NEXT: rrx r3, r3
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt60 # CHECK: adc r4, r5, r6, rrx
73 # CHECK: adc r4, r4, r5, rrx
78 # CHECK: adc r4, r4, r5, rrx
133 # CHECK: add r4, r5, r6, rrx
146 # CHECK: add r4, r4, r5, rrx
217 # CHECK: and r10, r1, r6, rrx
230 # CHECK: and r10, r10, r1, rrx
300 # CHECK: bic r10, r1, r6, rrx
313 # CHECK: bic r10, r10, r1, rrx
435 # CHECK: cmn r1, r6, rrx
[all …]
Darm-tests.txt108 # CHECK-NOT: orr r7, r8, r7, rrx #0
109 # CHECK: orr r7, r8, r7, rrx
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt54 # CHECK: adc r4, r5, r6, rrx
67 # CHECK: adc r4, r4, r5, rrx
72 # CHECK: adc r4, r4, r5, rrx
125 # CHECK: add r4, r5, r6, rrx
138 # CHECK: add r4, r4, r5, rrx
190 # CHECK: and r10, r1, r6, rrx
203 # CHECK: and r10, r10, r1, rrx
269 # CHECK: bic r10, r1, r6, rrx
282 # CHECK: bic r10, r10, r1, rrx
400 # CHECK: cmn r1, r6, rrx
[all …]
Darm-tests.txt84 # CHECK-NOT: orr r7, r8, r7, rrx #0
85 # CHECK: orr r7, r8, r7, rrx
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h32 rrx enumerator
51 case ARM_AM::rrx: return "rrx"; in getShiftOpcStr()
DARMMCCodeEmitter.cpp186 case ARM_AM::rrx: return 3; in getShiftOp()
1165 case ARM_AM::rrx: in getSORegImmOpValue()
1280 case ARM_AM::rrx: // FALLTHROUGH in getT2SORegOpValue()
1285 if (SOpc == ARM_AM::rrx) in getT2SORegOpValue()
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dlong_shift.ll6 ; CHECK-NEXT: rrx r2, r2
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h33 rrx enumerator
52 case ARM_AM::rrx: return "rrx"; in getShiftOpcStr()
DARMMCCodeEmitter.cpp212 case ARM_AM::rrx: return 3; in getShiftOp()
1394 case ARM_AM::rrx: in getSORegImmOpValue()
1496 case ARM_AM::rrx: // FALLTHROUGH in getT2SORegOpValue()
1501 if (SOpc == ARM_AM::rrx) in getT2SORegOpValue()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
251 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
268 if (ShOpc == ARM_AM::rrx) in printSORegImmOperand()
832 if (ShOpc != ARM_AM::rrx) in printT2SOOperand()
/external/swiftshader/third_party/subzero/src/
DIceInstARM32.def100 X(RRX, "rrx")
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp407 case ARM_AM::rrx: return 3; in getShiftOp()
945 case ARM_AM::rrx: SBits = 0x6; break; in getMachineSoRegOpValue()
962 if (SOpc == ARM_AM::rrx) in getMachineSoRegOpValue()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp53 if (ShOpc != ARM_AM::rrx) { in printRegImmShift()
116 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
354 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-t32.cc57 M(rrx) \

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