1/* 2 * This file was generated automatically by gen-mterp.py for 'arm'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: arm/header.S */ 8/* 9 * Copyright (C) 2016 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 Art assembly interpreter notes: 26 27 First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't 28 handle invoke, allows higher-level code to create frame & shadow frame. 29 30 Once that's working, support direct entry code & eliminate shadow frame (and 31 excess locals allocation. 32 33 Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the 34 base of the vreg array within the shadow frame. Access the other fields, 35 dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue 36 the shadow frame mechanism of double-storing object references - via rFP & 37 number_of_vregs_. 38 39 */ 40 41/* 42ARM EABI general notes: 43 44r0-r3 hold first 4 args to a method; they are not preserved across method calls 45r4-r8 are available for general use 46r9 is given special treatment in some situations, but not for us 47r10 (sl) seems to be generally available 48r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 49r12 (ip) is scratch -- not preserved across method calls 50r13 (sp) should be managed carefully in case a signal arrives 51r14 (lr) must be preserved 52r15 (pc) can be tinkered with directly 53 54r0 holds returns of <= 4 bytes 55r0-r1 hold returns of 8 bytes, low word in r0 56 57Callee must save/restore r4+ (except r12) if it modifies them. If VFP 58is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 59s0-s15 (d0-d7, q0-a3) do not need to be. 60 61Stack is "full descending". Only the arguments that don't fit in the first 4 62registers are placed on the stack. "sp" points at the first stacked argument 63(i.e. the 5th arg). 64 65VFP: single-precision results in s0, double-precision results in d0. 66 67In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 6864-bit quantities (long long, double) must be 64-bit aligned. 69*/ 70 71/* 72Mterp and ARM notes: 73 74The following registers have fixed assignments: 75 76 reg nick purpose 77 r4 rPC interpreted program counter, used for fetching instructions 78 r5 rFP interpreted frame pointer, used for accessing locals and args 79 r6 rSELF self (Thread) pointer 80 r7 rINST first 16-bit code unit of current instruction 81 r8 rIBASE interpreted instruction base pointer, used for computed goto 82 r10 rPROFILE branch profiling countdown 83 r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). 84 85Macros are provided for common operations. Each macro MUST emit only 86one instruction to make instruction-counting easier. They MUST NOT alter 87unspecified registers or condition codes. 88*/ 89 90/* 91 * This is a #include, not a %include, because we want the C pre-processor 92 * to expand the macros into assembler assignment statements. 93 */ 94#include "asm_support.h" 95#include "interpreter/cfi_asm_support.h" 96 97#define MTERP_PROFILE_BRANCHES 1 98#define MTERP_LOGGING 0 99 100/* During bringup, we'll use the shadow frame model instead of rFP */ 101/* single-purpose registers, given names for clarity */ 102#define rPC r4 103#define CFI_DEX 4 // DWARF register number of the register holding dex-pc (xPC). 104#define CFI_TMP 0 // DWARF register number of the first argument register (r0). 105#define rFP r5 106#define rSELF r6 107#define rINST r7 108#define rIBASE r8 109#define rPROFILE r10 110#define rREFS r11 111 112/* 113 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, 114 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 115 */ 116#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 117#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 118#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 119#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 120#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 121#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 122#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 123#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) 124#define OFF_FP_SHADOWFRAME OFF_FP(0) 125 126/* 127 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 128 * be done *before* something throws. 129 * 130 * It's okay to do this more than once. 131 * 132 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 133 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 134 * offset into the code_items_[] array. For effiency, we will "export" the 135 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 136 * to convert to a dex pc when needed. 137 */ 138.macro EXPORT_PC 139 str rPC, [rFP, #OFF_FP_DEX_PC_PTR] 140.endm 141 142.macro EXPORT_DEX_PC tmp 143 ldr \tmp, [rFP, #OFF_FP_DEX_INSTRUCTIONS] 144 str rPC, [rFP, #OFF_FP_DEX_PC_PTR] 145 sub \tmp, rPC, \tmp 146 asr \tmp, #1 147 str \tmp, [rFP, #OFF_FP_DEX_PC] 148.endm 149 150/* 151 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 152 */ 153.macro FETCH_INST 154 ldrh rINST, [rPC] 155.endm 156 157/* 158 * Fetch the next instruction from the specified offset. Advances rPC 159 * to point to the next instruction. "_count" is in 16-bit code units. 160 * 161 * Because of the limited size of immediate constants on ARM, this is only 162 * suitable for small forward movements (i.e. don't try to implement "goto" 163 * with this). 164 * 165 * This must come AFTER anything that can throw an exception, or the 166 * exception catch may miss. (This also implies that it must come after 167 * EXPORT_PC.) 168 */ 169.macro FETCH_ADVANCE_INST count 170 ldrh rINST, [rPC, #((\count)*2)]! 171.endm 172 173/* 174 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 175 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 176 */ 177.macro PREFETCH_ADVANCE_INST dreg, sreg, count 178 ldrh \dreg, [\sreg, #((\count)*2)]! 179.endm 180 181/* 182 * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load 183 * rINST ahead of possible exception point. Be sure to manually advance rPC 184 * later. 185 */ 186.macro PREFETCH_INST count 187 ldrh rINST, [rPC, #((\count)*2)] 188.endm 189 190/* Advance rPC by some number of code units. */ 191.macro ADVANCE count 192 add rPC, #((\count)*2) 193.endm 194 195/* 196 * Fetch the next instruction from an offset specified by _reg. Updates 197 * rPC to point to the next instruction. "_reg" must specify the distance 198 * in bytes, *not* 16-bit code units, and may be a signed value. 199 * 200 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 201 * bits that hold the shift distance are used for the half/byte/sign flags. 202 * In some cases we can pre-double _reg for free, so we require a byte offset 203 * here. 204 */ 205.macro FETCH_ADVANCE_INST_RB reg 206 ldrh rINST, [rPC, \reg]! 207.endm 208 209/* 210 * Fetch a half-word code unit from an offset past the current PC. The 211 * "_count" value is in 16-bit code units. Does not advance rPC. 212 * 213 * The "_S" variant works the same but treats the value as signed. 214 */ 215.macro FETCH reg, count 216 ldrh \reg, [rPC, #((\count)*2)] 217.endm 218 219.macro FETCH_S reg, count 220 ldrsh \reg, [rPC, #((\count)*2)] 221.endm 222 223/* 224 * Fetch one byte from an offset past the current PC. Pass in the same 225 * "_count" as you would for FETCH, and an additional 0/1 indicating which 226 * byte of the halfword you want (lo/hi). 227 */ 228.macro FETCH_B reg, count, byte 229 ldrb \reg, [rPC, #((\count)*2+(\byte))] 230.endm 231 232/* 233 * Put the instruction's opcode field into the specified register. 234 */ 235.macro GET_INST_OPCODE reg 236 and \reg, rINST, #255 237.endm 238 239/* 240 * Put the prefetched instruction's opcode field into the specified register. 241 */ 242.macro GET_PREFETCHED_OPCODE oreg, ireg 243 and \oreg, \ireg, #255 244.endm 245 246/* 247 * Begin executing the opcode in _reg. Because this only jumps within the 248 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 249 */ 250.macro GOTO_OPCODE reg 251 add pc, rIBASE, \reg, lsl #7 252.endm 253.macro GOTO_OPCODE_BASE base,reg 254 add pc, \base, \reg, lsl #7 255.endm 256 257/* 258 * Get/set the 32-bit value from a Dalvik register. 259 */ 260.macro GET_VREG reg, vreg 261 ldr \reg, [rFP, \vreg, lsl #2] 262.endm 263.macro SET_VREG reg, vreg 264 str \reg, [rFP, \vreg, lsl #2] 265 mov \reg, #0 266 str \reg, [rREFS, \vreg, lsl #2] 267.endm 268.macro SET_VREG_OBJECT reg, vreg, tmpreg 269 str \reg, [rFP, \vreg, lsl #2] 270 str \reg, [rREFS, \vreg, lsl #2] 271.endm 272.macro SET_VREG_SHADOW reg, vreg 273 str \reg, [rREFS, \vreg, lsl #2] 274.endm 275 276/* 277 * Clear the corresponding shadow regs for a vreg pair 278 */ 279.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 280 mov \tmp1, #0 281 add \tmp2, \vreg, #1 282 SET_VREG_SHADOW \tmp1, \vreg 283 SET_VREG_SHADOW \tmp1, \tmp2 284.endm 285 286/* 287 * Convert a virtual register index into an address. 288 */ 289.macro VREG_INDEX_TO_ADDR reg, vreg 290 add \reg, rFP, \vreg, lsl #2 /* WARNING/FIXME: handle shadow frame vreg zero if store */ 291.endm 292 293/* 294 * Refresh handler table. 295 */ 296.macro REFRESH_IBASE 297 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] 298.endm 299 300/* 301 * cfi support macros. 302 */ 303.macro ENTRY name 304 .arm 305 .type \name, #function 306 .hidden \name // Hide this as a global symbol, so we do not incur plt calls. 307 .global \name 308 /* Cache alignment for function entry */ 309 .balign 16 310\name: 311 .cfi_startproc 312 .fnstart 313.endm 314 315.macro END name 316 .fnend 317 .cfi_endproc 318 .size \name, .-\name 319.endm 320 321/* File: arm/entry.S */ 322/* 323 * Copyright (C) 2016 The Android Open Source Project 324 * 325 * Licensed under the Apache License, Version 2.0 (the "License"); 326 * you may not use this file except in compliance with the License. 327 * You may obtain a copy of the License at 328 * 329 * http://www.apache.org/licenses/LICENSE-2.0 330 * 331 * Unless required by applicable law or agreed to in writing, software 332 * distributed under the License is distributed on an "AS IS" BASIS, 333 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 334 * See the License for the specific language governing permissions and 335 * limitations under the License. 336 */ 337/* 338 * Interpreter entry point. 339 */ 340 341 .text 342 .align 2 343 344/* 345 * On entry: 346 * r0 Thread* self/ 347 * r1 insns_ 348 * r2 ShadowFrame 349 * r3 JValue* result_register 350 * 351 */ 352 353ENTRY ExecuteMterpImpl 354 stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64) 355 .cfi_adjust_cfa_offset 40 356 .cfi_rel_offset r3, 0 357 .cfi_rel_offset r4, 4 358 .cfi_rel_offset r5, 8 359 .cfi_rel_offset r6, 12 360 .cfi_rel_offset r7, 16 361 .cfi_rel_offset r8, 20 362 .cfi_rel_offset r9, 24 363 .cfi_rel_offset r10, 28 364 .cfi_rel_offset fp, 32 365 .cfi_rel_offset lr, 36 366 367 /* Remember the return register */ 368 str r3, [r2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] 369 370 /* Remember the dex instruction pointer */ 371 str r1, [r2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] 372 373 /* set up "named" registers */ 374 mov rSELF, r0 375 ldr r0, [r2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] 376 add rFP, r2, #SHADOWFRAME_VREGS_OFFSET @ point to vregs. 377 VREG_INDEX_TO_ADDR rREFS, r0 @ point to reference array in shadow frame 378 ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc. 379 add rPC, r1, r0, lsl #1 @ Create direct pointer to 1st dex opcode 380 CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) 381 EXPORT_PC 382 383 /* Starting ibase */ 384 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] 385 386 /* Set up for backwards branches & osr profiling */ 387 ldr r0, [rFP, #OFF_FP_METHOD] 388 add r1, rFP, #OFF_FP_SHADOWFRAME 389 mov r2, rSELF 390 bl MterpSetUpHotnessCountdown 391 mov rPROFILE, r0 @ Starting hotness countdown to rPROFILE 392 393 /* start executing the instruction at rPC */ 394 FETCH_INST @ load rINST from rPC 395 GET_INST_OPCODE ip @ extract opcode from rINST 396 GOTO_OPCODE ip @ jump to next instruction 397 /* NOTE: no fallthrough */ 398 399 400 .global artMterpAsmInstructionStart 401artMterpAsmInstructionStart = .L_op_nop 402 .text 403 404/* ------------------------------ */ 405 .balign 128 406.L_op_nop: /* 0x00 */ 407/* File: arm/op_nop.S */ 408 FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST 409 GET_INST_OPCODE ip @ ip<- opcode from rINST 410 GOTO_OPCODE ip @ execute it 411 412/* ------------------------------ */ 413 .balign 128 414.L_op_move: /* 0x01 */ 415/* File: arm/op_move.S */ 416 /* for move, move-object, long-to-int */ 417 /* op vA, vB */ 418 mov r1, rINST, lsr #12 @ r1<- B from 15:12 419 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 420 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 421 GET_VREG r2, r1 @ r2<- fp[B] 422 GET_INST_OPCODE ip @ ip<- opcode from rINST 423 .if 0 424 SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 425 .else 426 SET_VREG r2, r0 @ fp[A]<- r2 427 .endif 428 GOTO_OPCODE ip @ execute next instruction 429 430/* ------------------------------ */ 431 .balign 128 432.L_op_move_from16: /* 0x02 */ 433/* File: arm/op_move_from16.S */ 434 /* for: move/from16, move-object/from16 */ 435 /* op vAA, vBBBB */ 436 FETCH r1, 1 @ r1<- BBBB 437 mov r0, rINST, lsr #8 @ r0<- AA 438 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 439 GET_VREG r2, r1 @ r2<- fp[BBBB] 440 GET_INST_OPCODE ip @ extract opcode from rINST 441 .if 0 442 SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 443 .else 444 SET_VREG r2, r0 @ fp[AA]<- r2 445 .endif 446 GOTO_OPCODE ip @ jump to next instruction 447 448/* ------------------------------ */ 449 .balign 128 450.L_op_move_16: /* 0x03 */ 451/* File: arm/op_move_16.S */ 452 /* for: move/16, move-object/16 */ 453 /* op vAAAA, vBBBB */ 454 FETCH r1, 2 @ r1<- BBBB 455 FETCH r0, 1 @ r0<- AAAA 456 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 457 GET_VREG r2, r1 @ r2<- fp[BBBB] 458 GET_INST_OPCODE ip @ extract opcode from rINST 459 .if 0 460 SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 461 .else 462 SET_VREG r2, r0 @ fp[AAAA]<- r2 463 .endif 464 GOTO_OPCODE ip @ jump to next instruction 465 466/* ------------------------------ */ 467 .balign 128 468.L_op_move_wide: /* 0x04 */ 469/* File: arm/op_move_wide.S */ 470 /* move-wide vA, vB */ 471 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 472 mov r3, rINST, lsr #12 @ r3<- B 473 ubfx rINST, rINST, #8, #4 @ rINST<- A 474 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 475 VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[A] 476 ldmia r3, {r0-r1} @ r0/r1<- fp[B] 477 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs 478 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 479 GET_INST_OPCODE ip @ extract opcode from rINST 480 stmia r2, {r0-r1} @ fp[A]<- r0/r1 481 GOTO_OPCODE ip @ jump to next instruction 482 483/* ------------------------------ */ 484 .balign 128 485.L_op_move_wide_from16: /* 0x05 */ 486/* File: arm/op_move_wide_from16.S */ 487 /* move-wide/from16 vAA, vBBBB */ 488 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 489 FETCH r3, 1 @ r3<- BBBB 490 mov rINST, rINST, lsr #8 @ rINST<- AA 491 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] 492 VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] 493 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 494 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs 495 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 496 GET_INST_OPCODE ip @ extract opcode from rINST 497 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 498 GOTO_OPCODE ip @ jump to next instruction 499 500/* ------------------------------ */ 501 .balign 128 502.L_op_move_wide_16: /* 0x06 */ 503/* File: arm/op_move_wide_16.S */ 504 /* move-wide/16 vAAAA, vBBBB */ 505 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 506 FETCH r3, 2 @ r3<- BBBB 507 FETCH r2, 1 @ r2<- AAAA 508 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] 509 VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA] 510 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 511 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 512 CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs 513 stmia lr, {r0-r1} @ fp[AAAA]<- r0/r1 514 GET_INST_OPCODE ip @ extract opcode from rINST 515 GOTO_OPCODE ip @ jump to next instruction 516 517/* ------------------------------ */ 518 .balign 128 519.L_op_move_object: /* 0x07 */ 520/* File: arm/op_move_object.S */ 521/* File: arm/op_move.S */ 522 /* for move, move-object, long-to-int */ 523 /* op vA, vB */ 524 mov r1, rINST, lsr #12 @ r1<- B from 15:12 525 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 526 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 527 GET_VREG r2, r1 @ r2<- fp[B] 528 GET_INST_OPCODE ip @ ip<- opcode from rINST 529 .if 1 530 SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 531 .else 532 SET_VREG r2, r0 @ fp[A]<- r2 533 .endif 534 GOTO_OPCODE ip @ execute next instruction 535 536 537/* ------------------------------ */ 538 .balign 128 539.L_op_move_object_from16: /* 0x08 */ 540/* File: arm/op_move_object_from16.S */ 541/* File: arm/op_move_from16.S */ 542 /* for: move/from16, move-object/from16 */ 543 /* op vAA, vBBBB */ 544 FETCH r1, 1 @ r1<- BBBB 545 mov r0, rINST, lsr #8 @ r0<- AA 546 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 547 GET_VREG r2, r1 @ r2<- fp[BBBB] 548 GET_INST_OPCODE ip @ extract opcode from rINST 549 .if 1 550 SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 551 .else 552 SET_VREG r2, r0 @ fp[AA]<- r2 553 .endif 554 GOTO_OPCODE ip @ jump to next instruction 555 556 557/* ------------------------------ */ 558 .balign 128 559.L_op_move_object_16: /* 0x09 */ 560/* File: arm/op_move_object_16.S */ 561/* File: arm/op_move_16.S */ 562 /* for: move/16, move-object/16 */ 563 /* op vAAAA, vBBBB */ 564 FETCH r1, 2 @ r1<- BBBB 565 FETCH r0, 1 @ r0<- AAAA 566 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 567 GET_VREG r2, r1 @ r2<- fp[BBBB] 568 GET_INST_OPCODE ip @ extract opcode from rINST 569 .if 1 570 SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 571 .else 572 SET_VREG r2, r0 @ fp[AAAA]<- r2 573 .endif 574 GOTO_OPCODE ip @ jump to next instruction 575 576 577/* ------------------------------ */ 578 .balign 128 579.L_op_move_result: /* 0x0a */ 580/* File: arm/op_move_result.S */ 581 /* for: move-result, move-result-object */ 582 /* op vAA */ 583 mov r2, rINST, lsr #8 @ r2<- AA 584 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 585 ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. 586 ldr r0, [r0] @ r0 <- result.i. 587 GET_INST_OPCODE ip @ extract opcode from rINST 588 .if 0 589 SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 590 .else 591 SET_VREG r0, r2 @ fp[AA]<- r0 592 .endif 593 GOTO_OPCODE ip @ jump to next instruction 594 595/* ------------------------------ */ 596 .balign 128 597.L_op_move_result_wide: /* 0x0b */ 598/* File: arm/op_move_result_wide.S */ 599 /* move-result-wide vAA */ 600 mov rINST, rINST, lsr #8 @ rINST<- AA 601 ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] 602 VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] 603 ldmia r3, {r0-r1} @ r0/r1<- retval.j 604 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs 605 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 606 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 607 GET_INST_OPCODE ip @ extract opcode from rINST 608 GOTO_OPCODE ip @ jump to next instruction 609 610/* ------------------------------ */ 611 .balign 128 612.L_op_move_result_object: /* 0x0c */ 613/* File: arm/op_move_result_object.S */ 614/* File: arm/op_move_result.S */ 615 /* for: move-result, move-result-object */ 616 /* op vAA */ 617 mov r2, rINST, lsr #8 @ r2<- AA 618 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 619 ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. 620 ldr r0, [r0] @ r0 <- result.i. 621 GET_INST_OPCODE ip @ extract opcode from rINST 622 .if 1 623 SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 624 .else 625 SET_VREG r0, r2 @ fp[AA]<- r0 626 .endif 627 GOTO_OPCODE ip @ jump to next instruction 628 629 630/* ------------------------------ */ 631 .balign 128 632.L_op_move_exception: /* 0x0d */ 633/* File: arm/op_move_exception.S */ 634 /* move-exception vAA */ 635 mov r2, rINST, lsr #8 @ r2<- AA 636 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 637 mov r1, #0 @ r1<- 0 638 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 639 SET_VREG_OBJECT r3, r2 @ fp[AA]<- exception obj 640 GET_INST_OPCODE ip @ extract opcode from rINST 641 str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ clear exception 642 GOTO_OPCODE ip @ jump to next instruction 643 644/* ------------------------------ */ 645 .balign 128 646.L_op_return_void: /* 0x0e */ 647/* File: arm/op_return_void.S */ 648 .extern MterpThreadFenceForConstructor 649 bl MterpThreadFenceForConstructor 650 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 651 mov r0, rSELF 652 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 653 blne MterpSuspendCheck @ (self) 654 mov r0, #0 655 mov r1, #0 656 b MterpReturn 657 658/* ------------------------------ */ 659 .balign 128 660.L_op_return: /* 0x0f */ 661/* File: arm/op_return.S */ 662 /* 663 * Return a 32-bit value. 664 * 665 * for: return, return-object 666 */ 667 /* op vAA */ 668 .extern MterpThreadFenceForConstructor 669 bl MterpThreadFenceForConstructor 670 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 671 mov r0, rSELF 672 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 673 blne MterpSuspendCheck @ (self) 674 mov r2, rINST, lsr #8 @ r2<- AA 675 GET_VREG r0, r2 @ r0<- vAA 676 mov r1, #0 677 b MterpReturn 678 679/* ------------------------------ */ 680 .balign 128 681.L_op_return_wide: /* 0x10 */ 682/* File: arm/op_return_wide.S */ 683 /* 684 * Return a 64-bit value. 685 */ 686 /* return-wide vAA */ 687 .extern MterpThreadFenceForConstructor 688 bl MterpThreadFenceForConstructor 689 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 690 mov r0, rSELF 691 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 692 blne MterpSuspendCheck @ (self) 693 mov r2, rINST, lsr #8 @ r2<- AA 694 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[AA] 695 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 696 b MterpReturn 697 698/* ------------------------------ */ 699 .balign 128 700.L_op_return_object: /* 0x11 */ 701/* File: arm/op_return_object.S */ 702/* File: arm/op_return.S */ 703 /* 704 * Return a 32-bit value. 705 * 706 * for: return, return-object 707 */ 708 /* op vAA */ 709 .extern MterpThreadFenceForConstructor 710 bl MterpThreadFenceForConstructor 711 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 712 mov r0, rSELF 713 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 714 blne MterpSuspendCheck @ (self) 715 mov r2, rINST, lsr #8 @ r2<- AA 716 GET_VREG r0, r2 @ r0<- vAA 717 mov r1, #0 718 b MterpReturn 719 720 721/* ------------------------------ */ 722 .balign 128 723.L_op_const_4: /* 0x12 */ 724/* File: arm/op_const_4.S */ 725 /* const/4 vA, #+B */ 726 sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended) 727 ubfx r0, rINST, #8, #4 @ r0<- A 728 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 729 GET_INST_OPCODE ip @ ip<- opcode from rINST 730 SET_VREG r1, r0 @ fp[A]<- r1 731 GOTO_OPCODE ip @ execute next instruction 732 733/* ------------------------------ */ 734 .balign 128 735.L_op_const_16: /* 0x13 */ 736/* File: arm/op_const_16.S */ 737 /* const/16 vAA, #+BBBB */ 738 FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) 739 mov r3, rINST, lsr #8 @ r3<- AA 740 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 741 SET_VREG r0, r3 @ vAA<- r0 742 GET_INST_OPCODE ip @ extract opcode from rINST 743 GOTO_OPCODE ip @ jump to next instruction 744 745/* ------------------------------ */ 746 .balign 128 747.L_op_const: /* 0x14 */ 748/* File: arm/op_const.S */ 749 /* const vAA, #+BBBBbbbb */ 750 mov r3, rINST, lsr #8 @ r3<- AA 751 FETCH r0, 1 @ r0<- bbbb (low) 752 FETCH r1, 2 @ r1<- BBBB (high) 753 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 754 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 755 GET_INST_OPCODE ip @ extract opcode from rINST 756 SET_VREG r0, r3 @ vAA<- r0 757 GOTO_OPCODE ip @ jump to next instruction 758 759/* ------------------------------ */ 760 .balign 128 761.L_op_const_high16: /* 0x15 */ 762/* File: arm/op_const_high16.S */ 763 /* const/high16 vAA, #+BBBB0000 */ 764 FETCH r0, 1 @ r0<- 0000BBBB (zero-extended) 765 mov r3, rINST, lsr #8 @ r3<- AA 766 mov r0, r0, lsl #16 @ r0<- BBBB0000 767 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 768 SET_VREG r0, r3 @ vAA<- r0 769 GET_INST_OPCODE ip @ extract opcode from rINST 770 GOTO_OPCODE ip @ jump to next instruction 771 772/* ------------------------------ */ 773 .balign 128 774.L_op_const_wide_16: /* 0x16 */ 775/* File: arm/op_const_wide_16.S */ 776 /* const-wide/16 vAA, #+BBBB */ 777 FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) 778 mov r3, rINST, lsr #8 @ r3<- AA 779 mov r1, r0, asr #31 @ r1<- ssssssss 780 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 781 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs 782 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] 783 GET_INST_OPCODE ip @ extract opcode from rINST 784 stmia r3, {r0-r1} @ vAA<- r0/r1 785 GOTO_OPCODE ip @ jump to next instruction 786 787/* ------------------------------ */ 788 .balign 128 789.L_op_const_wide_32: /* 0x17 */ 790/* File: arm/op_const_wide_32.S */ 791 /* const-wide/32 vAA, #+BBBBbbbb */ 792 FETCH r0, 1 @ r0<- 0000bbbb (low) 793 mov r3, rINST, lsr #8 @ r3<- AA 794 FETCH_S r2, 2 @ r2<- ssssBBBB (high) 795 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 796 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 797 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs 798 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] 799 mov r1, r0, asr #31 @ r1<- ssssssss 800 GET_INST_OPCODE ip @ extract opcode from rINST 801 stmia r3, {r0-r1} @ vAA<- r0/r1 802 GOTO_OPCODE ip @ jump to next instruction 803 804/* ------------------------------ */ 805 .balign 128 806.L_op_const_wide: /* 0x18 */ 807/* File: arm/op_const_wide.S */ 808 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 809 FETCH r0, 1 @ r0<- bbbb (low) 810 FETCH r1, 2 @ r1<- BBBB (low middle) 811 FETCH r2, 3 @ r2<- hhhh (high middle) 812 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 813 FETCH r3, 4 @ r3<- HHHH (high) 814 mov r9, rINST, lsr #8 @ r9<- AA 815 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 816 CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs 817 FETCH_ADVANCE_INST 5 @ advance rPC, load rINST 818 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 819 GET_INST_OPCODE ip @ extract opcode from rINST 820 stmia r9, {r0-r1} @ vAA<- r0/r1 821 GOTO_OPCODE ip @ jump to next instruction 822 823/* ------------------------------ */ 824 .balign 128 825.L_op_const_wide_high16: /* 0x19 */ 826/* File: arm/op_const_wide_high16.S */ 827 /* const-wide/high16 vAA, #+BBBB000000000000 */ 828 FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) 829 mov r3, rINST, lsr #8 @ r3<- AA 830 mov r0, #0 @ r0<- 00000000 831 mov r1, r1, lsl #16 @ r1<- BBBB0000 832 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 833 CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs 834 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] 835 GET_INST_OPCODE ip @ extract opcode from rINST 836 stmia r3, {r0-r1} @ vAA<- r0/r1 837 GOTO_OPCODE ip @ jump to next instruction 838 839/* ------------------------------ */ 840 .balign 128 841.L_op_const_string: /* 0x1a */ 842/* File: arm/op_const_string.S */ 843/* File: arm/const.S */ 844 /* const/class vAA, type@BBBB */ 845 /* const/method-handle vAA, method_handle@BBBB */ 846 /* const/method-type vAA, proto@BBBB */ 847 /* const/string vAA, string@@BBBB */ 848 .extern MterpConstString 849 EXPORT_PC 850 FETCH r0, 1 @ r0<- BBBB 851 mov r1, rINST, lsr #8 @ r1<- AA 852 add r2, rFP, #OFF_FP_SHADOWFRAME 853 mov r3, rSELF 854 bl MterpConstString @ (index, tgt_reg, shadow_frame, self) 855 PREFETCH_INST 2 @ load rINST 856 cmp r0, #0 @ fail? 857 bne MterpPossibleException @ let reference interpreter deal with it. 858 ADVANCE 2 @ advance rPC 859 GET_INST_OPCODE ip @ extract opcode from rINST 860 GOTO_OPCODE ip @ jump to next instruction 861 862 863/* ------------------------------ */ 864 .balign 128 865.L_op_const_string_jumbo: /* 0x1b */ 866/* File: arm/op_const_string_jumbo.S */ 867 /* const/string vAA, String@BBBBBBBB */ 868 EXPORT_PC 869 FETCH r0, 1 @ r0<- bbbb (low) 870 FETCH r2, 2 @ r2<- BBBB (high) 871 mov r1, rINST, lsr #8 @ r1<- AA 872 orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb 873 add r2, rFP, #OFF_FP_SHADOWFRAME 874 mov r3, rSELF 875 bl MterpConstString @ (index, tgt_reg, shadow_frame, self) 876 PREFETCH_INST 3 @ advance rPC 877 cmp r0, #0 @ fail? 878 bne MterpPossibleException @ let reference interpreter deal with it. 879 ADVANCE 3 @ advance rPC 880 GET_INST_OPCODE ip @ extract opcode from rINST 881 GOTO_OPCODE ip @ jump to next instruction 882 883/* ------------------------------ */ 884 .balign 128 885.L_op_const_class: /* 0x1c */ 886/* File: arm/op_const_class.S */ 887/* File: arm/const.S */ 888 /* const/class vAA, type@BBBB */ 889 /* const/method-handle vAA, method_handle@BBBB */ 890 /* const/method-type vAA, proto@BBBB */ 891 /* const/string vAA, string@@BBBB */ 892 .extern MterpConstClass 893 EXPORT_PC 894 FETCH r0, 1 @ r0<- BBBB 895 mov r1, rINST, lsr #8 @ r1<- AA 896 add r2, rFP, #OFF_FP_SHADOWFRAME 897 mov r3, rSELF 898 bl MterpConstClass @ (index, tgt_reg, shadow_frame, self) 899 PREFETCH_INST 2 @ load rINST 900 cmp r0, #0 @ fail? 901 bne MterpPossibleException @ let reference interpreter deal with it. 902 ADVANCE 2 @ advance rPC 903 GET_INST_OPCODE ip @ extract opcode from rINST 904 GOTO_OPCODE ip @ jump to next instruction 905 906 907/* ------------------------------ */ 908 .balign 128 909.L_op_monitor_enter: /* 0x1d */ 910/* File: arm/op_monitor_enter.S */ 911 /* 912 * Synchronize on an object. 913 */ 914 /* monitor-enter vAA */ 915 EXPORT_PC 916 mov r2, rINST, lsr #8 @ r2<- AA 917 GET_VREG r0, r2 @ r0<- vAA (object) 918 mov r1, rSELF @ r1<- self 919 bl artLockObjectFromCode 920 cmp r0, #0 921 bne MterpException 922 FETCH_ADVANCE_INST 1 923 GET_INST_OPCODE ip @ extract opcode from rINST 924 GOTO_OPCODE ip @ jump to next instruction 925 926/* ------------------------------ */ 927 .balign 128 928.L_op_monitor_exit: /* 0x1e */ 929/* File: arm/op_monitor_exit.S */ 930 /* 931 * Unlock an object. 932 * 933 * Exceptions that occur when unlocking a monitor need to appear as 934 * if they happened at the following instruction. See the Dalvik 935 * instruction spec. 936 */ 937 /* monitor-exit vAA */ 938 EXPORT_PC 939 mov r2, rINST, lsr #8 @ r2<- AA 940 GET_VREG r0, r2 @ r0<- vAA (object) 941 mov r1, rSELF @ r0<- self 942 bl artUnlockObjectFromCode @ r0<- success for unlock(self, obj) 943 cmp r0, #0 @ failed? 944 bne MterpException 945 FETCH_ADVANCE_INST 1 @ before throw: advance rPC, load rINST 946 GET_INST_OPCODE ip @ extract opcode from rINST 947 GOTO_OPCODE ip @ jump to next instruction 948 949/* ------------------------------ */ 950 .balign 128 951.L_op_check_cast: /* 0x1f */ 952/* File: arm/op_check_cast.S */ 953 /* 954 * Check to see if a cast from one class to another is allowed. 955 */ 956 /* check-cast vAA, class@BBBB */ 957 EXPORT_PC 958 FETCH r0, 1 @ r0<- BBBB 959 mov r1, rINST, lsr #8 @ r1<- AA 960 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object 961 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method 962 mov r3, rSELF @ r3<- self 963 bl MterpCheckCast @ (index, &obj, method, self) 964 PREFETCH_INST 2 965 cmp r0, #0 966 bne MterpPossibleException 967 ADVANCE 2 968 GET_INST_OPCODE ip @ extract opcode from rINST 969 GOTO_OPCODE ip @ jump to next instruction 970 971/* ------------------------------ */ 972 .balign 128 973.L_op_instance_of: /* 0x20 */ 974/* File: arm/op_instance_of.S */ 975 /* 976 * Check to see if an object reference is an instance of a class. 977 * 978 * Most common situation is a non-null object, being compared against 979 * an already-resolved class. 980 */ 981 /* instance-of vA, vB, class@CCCC */ 982 EXPORT_PC 983 FETCH r0, 1 @ r0<- CCCC 984 mov r1, rINST, lsr #12 @ r1<- B 985 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object 986 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method 987 mov r3, rSELF @ r3<- self 988 bl MterpInstanceOf @ (index, &obj, method, self) 989 ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] 990 ubfx r9, rINST, #8, #4 @ r9<- A 991 PREFETCH_INST 2 992 cmp r1, #0 @ exception pending? 993 bne MterpException 994 ADVANCE 2 @ advance rPC 995 SET_VREG r0, r9 @ vA<- r0 996 GET_INST_OPCODE ip @ extract opcode from rINST 997 GOTO_OPCODE ip @ jump to next instruction 998 999/* ------------------------------ */ 1000 .balign 128 1001.L_op_array_length: /* 0x21 */ 1002/* File: arm/op_array_length.S */ 1003 /* 1004 * Return the length of an array. 1005 */ 1006 mov r1, rINST, lsr #12 @ r1<- B 1007 ubfx r2, rINST, #8, #4 @ r2<- A 1008 GET_VREG r0, r1 @ r0<- vB (object ref) 1009 cmp r0, #0 @ is object null? 1010 beq common_errNullObject @ yup, fail 1011 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 1012 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- array length 1013 GET_INST_OPCODE ip @ extract opcode from rINST 1014 SET_VREG r3, r2 @ vB<- length 1015 GOTO_OPCODE ip @ jump to next instruction 1016 1017/* ------------------------------ */ 1018 .balign 128 1019.L_op_new_instance: /* 0x22 */ 1020/* File: arm/op_new_instance.S */ 1021 /* 1022 * Create a new instance of a class. 1023 */ 1024 /* new-instance vAA, class@BBBB */ 1025 EXPORT_PC 1026 add r0, rFP, #OFF_FP_SHADOWFRAME 1027 mov r1, rSELF 1028 mov r2, rINST 1029 bl MterpNewInstance @ (shadow_frame, self, inst_data) 1030 cmp r0, #0 1031 beq MterpPossibleException 1032 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1033 GET_INST_OPCODE ip @ extract opcode from rINST 1034 GOTO_OPCODE ip @ jump to next instruction 1035 1036/* ------------------------------ */ 1037 .balign 128 1038.L_op_new_array: /* 0x23 */ 1039/* File: arm/op_new_array.S */ 1040 /* 1041 * Allocate an array of objects, specified with the array class 1042 * and a count. 1043 * 1044 * The verifier guarantees that this is an array class, so we don't 1045 * check for it here. 1046 */ 1047 /* new-array vA, vB, class@CCCC */ 1048 EXPORT_PC 1049 add r0, rFP, #OFF_FP_SHADOWFRAME 1050 mov r1, rPC 1051 mov r2, rINST 1052 mov r3, rSELF 1053 bl MterpNewArray 1054 cmp r0, #0 1055 beq MterpPossibleException 1056 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1057 GET_INST_OPCODE ip @ extract opcode from rINST 1058 GOTO_OPCODE ip @ jump to next instruction 1059 1060/* ------------------------------ */ 1061 .balign 128 1062.L_op_filled_new_array: /* 0x24 */ 1063/* File: arm/op_filled_new_array.S */ 1064 /* 1065 * Create a new array with elements filled from registers. 1066 * 1067 * for: filled-new-array, filled-new-array/range 1068 */ 1069 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1070 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1071 .extern MterpFilledNewArray 1072 EXPORT_PC 1073 add r0, rFP, #OFF_FP_SHADOWFRAME 1074 mov r1, rPC 1075 mov r2, rSELF 1076 bl MterpFilledNewArray 1077 cmp r0, #0 1078 beq MterpPossibleException 1079 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 1080 GET_INST_OPCODE ip @ extract opcode from rINST 1081 GOTO_OPCODE ip @ jump to next instruction 1082 1083/* ------------------------------ */ 1084 .balign 128 1085.L_op_filled_new_array_range: /* 0x25 */ 1086/* File: arm/op_filled_new_array_range.S */ 1087/* File: arm/op_filled_new_array.S */ 1088 /* 1089 * Create a new array with elements filled from registers. 1090 * 1091 * for: filled-new-array, filled-new-array/range 1092 */ 1093 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1094 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1095 .extern MterpFilledNewArrayRange 1096 EXPORT_PC 1097 add r0, rFP, #OFF_FP_SHADOWFRAME 1098 mov r1, rPC 1099 mov r2, rSELF 1100 bl MterpFilledNewArrayRange 1101 cmp r0, #0 1102 beq MterpPossibleException 1103 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 1104 GET_INST_OPCODE ip @ extract opcode from rINST 1105 GOTO_OPCODE ip @ jump to next instruction 1106 1107 1108/* ------------------------------ */ 1109 .balign 128 1110.L_op_fill_array_data: /* 0x26 */ 1111/* File: arm/op_fill_array_data.S */ 1112 /* fill-array-data vAA, +BBBBBBBB */ 1113 EXPORT_PC 1114 FETCH r0, 1 @ r0<- bbbb (lo) 1115 FETCH r1, 2 @ r1<- BBBB (hi) 1116 mov r3, rINST, lsr #8 @ r3<- AA 1117 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1118 GET_VREG r0, r3 @ r0<- vAA (array object) 1119 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1120 bl MterpFillArrayData @ (obj, payload) 1121 cmp r0, #0 @ 0 means an exception is thrown 1122 beq MterpPossibleException @ exception? 1123 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 1124 GET_INST_OPCODE ip @ extract opcode from rINST 1125 GOTO_OPCODE ip @ jump to next instruction 1126 1127/* ------------------------------ */ 1128 .balign 128 1129.L_op_throw: /* 0x27 */ 1130/* File: arm/op_throw.S */ 1131 /* 1132 * Throw an exception object in the current thread. 1133 */ 1134 /* throw vAA */ 1135 EXPORT_PC 1136 mov r2, rINST, lsr #8 @ r2<- AA 1137 GET_VREG r1, r2 @ r1<- vAA (exception object) 1138 cmp r1, #0 @ null object? 1139 beq common_errNullObject @ yes, throw an NPE instead 1140 str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ thread->exception<- obj 1141 b MterpException 1142 1143/* ------------------------------ */ 1144 .balign 128 1145.L_op_goto: /* 0x28 */ 1146/* File: arm/op_goto.S */ 1147 /* 1148 * Unconditional branch, 8-bit offset. 1149 * 1150 * The branch distance is a signed code-unit offset, which we need to 1151 * double to get a byte offset. 1152 */ 1153 /* goto +AA */ 1154 sbfx rINST, rINST, #8, #8 @ rINST<- ssssssAA (sign-extended) 1155 b MterpCommonTakenBranchNoFlags 1156 1157/* ------------------------------ */ 1158 .balign 128 1159.L_op_goto_16: /* 0x29 */ 1160/* File: arm/op_goto_16.S */ 1161 /* 1162 * Unconditional branch, 16-bit offset. 1163 * 1164 * The branch distance is a signed code-unit offset, which we need to 1165 * double to get a byte offset. 1166 */ 1167 /* goto/16 +AAAA */ 1168 FETCH_S rINST, 1 @ rINST<- ssssAAAA (sign-extended) 1169 b MterpCommonTakenBranchNoFlags 1170 1171/* ------------------------------ */ 1172 .balign 128 1173.L_op_goto_32: /* 0x2a */ 1174/* File: arm/op_goto_32.S */ 1175 /* 1176 * Unconditional branch, 32-bit offset. 1177 * 1178 * The branch distance is a signed code-unit offset, which we need to 1179 * double to get a byte offset. 1180 * 1181 * Unlike most opcodes, this one is allowed to branch to itself, so 1182 * our "backward branch" test must be "<=0" instead of "<0". Because 1183 * we need the V bit set, we'll use an adds to convert from Dalvik 1184 * offset to byte offset. 1185 */ 1186 /* goto/32 +AAAAAAAA */ 1187 FETCH r0, 1 @ r0<- aaaa (lo) 1188 FETCH r3, 2 @ r1<- AAAA (hi) 1189 orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa 1190 b MterpCommonTakenBranch 1191 1192/* ------------------------------ */ 1193 .balign 128 1194.L_op_packed_switch: /* 0x2b */ 1195/* File: arm/op_packed_switch.S */ 1196 /* 1197 * Handle a packed-switch or sparse-switch instruction. In both cases 1198 * we decode it and hand it off to a helper function. 1199 * 1200 * We don't really expect backward branches in a switch statement, but 1201 * they're perfectly legal, so we check for them here. 1202 * 1203 * for: packed-switch, sparse-switch 1204 */ 1205 /* op vAA, +BBBB */ 1206 FETCH r0, 1 @ r0<- bbbb (lo) 1207 FETCH r1, 2 @ r1<- BBBB (hi) 1208 mov r3, rINST, lsr #8 @ r3<- AA 1209 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1210 GET_VREG r1, r3 @ r1<- vAA 1211 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1212 bl MterpDoPackedSwitch @ r0<- code-unit branch offset 1213 movs rINST, r0 1214 b MterpCommonTakenBranch 1215 1216/* ------------------------------ */ 1217 .balign 128 1218.L_op_sparse_switch: /* 0x2c */ 1219/* File: arm/op_sparse_switch.S */ 1220/* File: arm/op_packed_switch.S */ 1221 /* 1222 * Handle a packed-switch or sparse-switch instruction. In both cases 1223 * we decode it and hand it off to a helper function. 1224 * 1225 * We don't really expect backward branches in a switch statement, but 1226 * they're perfectly legal, so we check for them here. 1227 * 1228 * for: packed-switch, sparse-switch 1229 */ 1230 /* op vAA, +BBBB */ 1231 FETCH r0, 1 @ r0<- bbbb (lo) 1232 FETCH r1, 2 @ r1<- BBBB (hi) 1233 mov r3, rINST, lsr #8 @ r3<- AA 1234 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1235 GET_VREG r1, r3 @ r1<- vAA 1236 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1237 bl MterpDoSparseSwitch @ r0<- code-unit branch offset 1238 movs rINST, r0 1239 b MterpCommonTakenBranch 1240 1241 1242/* ------------------------------ */ 1243 .balign 128 1244.L_op_cmpl_float: /* 0x2d */ 1245/* File: arm/op_cmpl_float.S */ 1246 /* 1247 * Compare two floating-point values. Puts 0, 1, or -1 into the 1248 * destination register based on the results of the comparison. 1249 * 1250 * int compare(x, y) { 1251 * if (x == y) { 1252 * return 0; 1253 * } else if (x > y) { 1254 * return 1; 1255 * } else if (x < y) { 1256 * return -1; 1257 * } else { 1258 * return -1; 1259 * } 1260 * } 1261 */ 1262 /* op vAA, vBB, vCC */ 1263 FETCH r0, 1 @ r0<- CCBB 1264 mov r9, rINST, lsr #8 @ r9<- AA 1265 and r2, r0, #255 @ r2<- BB 1266 mov r3, r0, lsr #8 @ r3<- CC 1267 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 1268 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 1269 flds s0, [r2] @ s0<- vBB 1270 flds s1, [r3] @ s1<- vCC 1271 vcmpe.f32 s0, s1 @ compare (vBB, vCC) 1272 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1273 mvn r0, #0 @ r0<- -1 (default) 1274 GET_INST_OPCODE ip @ extract opcode from rINST 1275 fmstat @ export status flags 1276 movgt r0, #1 @ (greater than) r1<- 1 1277 moveq r0, #0 @ (equal) r1<- 0 1278 SET_VREG r0, r9 @ vAA<- r0 1279 GOTO_OPCODE ip @ jump to next instruction 1280 1281/* ------------------------------ */ 1282 .balign 128 1283.L_op_cmpg_float: /* 0x2e */ 1284/* File: arm/op_cmpg_float.S */ 1285 /* 1286 * Compare two floating-point values. Puts 0, 1, or -1 into the 1287 * destination register based on the results of the comparison. 1288 * 1289 * int compare(x, y) { 1290 * if (x == y) { 1291 * return 0; 1292 * } else if (x < y) { 1293 * return -1; 1294 * } else if (x > y) { 1295 * return 1; 1296 * } else { 1297 * return 1; 1298 * } 1299 * } 1300 */ 1301 /* op vAA, vBB, vCC */ 1302 FETCH r0, 1 @ r0<- CCBB 1303 mov r9, rINST, lsr #8 @ r9<- AA 1304 and r2, r0, #255 @ r2<- BB 1305 mov r3, r0, lsr #8 @ r3<- CC 1306 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 1307 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 1308 flds s0, [r2] @ s0<- vBB 1309 flds s1, [r3] @ s1<- vCC 1310 vcmpe.f32 s0, s1 @ compare (vBB, vCC) 1311 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1312 mov r0, #1 @ r0<- 1 (default) 1313 GET_INST_OPCODE ip @ extract opcode from rINST 1314 fmstat @ export status flags 1315 mvnmi r0, #0 @ (less than) r1<- -1 1316 moveq r0, #0 @ (equal) r1<- 0 1317 SET_VREG r0, r9 @ vAA<- r0 1318 GOTO_OPCODE ip @ jump to next instruction 1319 1320/* ------------------------------ */ 1321 .balign 128 1322.L_op_cmpl_double: /* 0x2f */ 1323/* File: arm/op_cmpl_double.S */ 1324 /* 1325 * Compare two floating-point values. Puts 0, 1, or -1 into the 1326 * destination register based on the results of the comparison. 1327 * 1328 * int compare(x, y) { 1329 * if (x == y) { 1330 * return 0; 1331 * } else if (x > y) { 1332 * return 1; 1333 * } else if (x < y) { 1334 * return -1; 1335 * } else { 1336 * return -1; 1337 * } 1338 * } 1339 */ 1340 /* op vAA, vBB, vCC */ 1341 FETCH r0, 1 @ r0<- CCBB 1342 mov r9, rINST, lsr #8 @ r9<- AA 1343 and r2, r0, #255 @ r2<- BB 1344 mov r3, r0, lsr #8 @ r3<- CC 1345 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 1346 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 1347 fldd d0, [r2] @ d0<- vBB 1348 fldd d1, [r3] @ d1<- vCC 1349 vcmpe.f64 d0, d1 @ compare (vBB, vCC) 1350 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1351 mvn r0, #0 @ r0<- -1 (default) 1352 GET_INST_OPCODE ip @ extract opcode from rINST 1353 fmstat @ export status flags 1354 movgt r0, #1 @ (greater than) r1<- 1 1355 moveq r0, #0 @ (equal) r1<- 0 1356 SET_VREG r0, r9 @ vAA<- r0 1357 GOTO_OPCODE ip @ jump to next instruction 1358 1359/* ------------------------------ */ 1360 .balign 128 1361.L_op_cmpg_double: /* 0x30 */ 1362/* File: arm/op_cmpg_double.S */ 1363 /* 1364 * Compare two floating-point values. Puts 0, 1, or -1 into the 1365 * destination register based on the results of the comparison. 1366 * 1367 * int compare(x, y) { 1368 * if (x == y) { 1369 * return 0; 1370 * } else if (x < y) { 1371 * return -1; 1372 * } else if (x > y) { 1373 * return 1; 1374 * } else { 1375 * return 1; 1376 * } 1377 * } 1378 */ 1379 /* op vAA, vBB, vCC */ 1380 FETCH r0, 1 @ r0<- CCBB 1381 mov r9, rINST, lsr #8 @ r9<- AA 1382 and r2, r0, #255 @ r2<- BB 1383 mov r3, r0, lsr #8 @ r3<- CC 1384 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 1385 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 1386 fldd d0, [r2] @ d0<- vBB 1387 fldd d1, [r3] @ d1<- vCC 1388 vcmpe.f64 d0, d1 @ compare (vBB, vCC) 1389 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1390 mov r0, #1 @ r0<- 1 (default) 1391 GET_INST_OPCODE ip @ extract opcode from rINST 1392 fmstat @ export status flags 1393 mvnmi r0, #0 @ (less than) r1<- -1 1394 moveq r0, #0 @ (equal) r1<- 0 1395 SET_VREG r0, r9 @ vAA<- r0 1396 GOTO_OPCODE ip @ jump to next instruction 1397 1398/* ------------------------------ */ 1399 .balign 128 1400.L_op_cmp_long: /* 0x31 */ 1401/* File: arm/op_cmp_long.S */ 1402 /* 1403 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1404 * register based on the results of the comparison. 1405 */ 1406 /* cmp-long vAA, vBB, vCC */ 1407 FETCH r0, 1 @ r0<- CCBB 1408 mov r9, rINST, lsr #8 @ r9<- AA 1409 and r2, r0, #255 @ r2<- BB 1410 mov r3, r0, lsr #8 @ r3<- CC 1411 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 1412 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 1413 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1414 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1415 cmp r0, r2 1416 sbcs ip, r1, r3 @ Sets correct CCs for checking LT (but not EQ/NE) 1417 mov ip, #0 1418 mvnlt ip, #0 @ -1 1419 cmpeq r0, r2 @ For correct EQ/NE, we may need to repeat the first CMP 1420 orrne ip, #1 1421 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1422 SET_VREG ip, r9 @ vAA<- ip 1423 GET_INST_OPCODE ip @ extract opcode from rINST 1424 GOTO_OPCODE ip @ jump to next instruction 1425 1426/* ------------------------------ */ 1427 .balign 128 1428.L_op_if_eq: /* 0x32 */ 1429/* File: arm/op_if_eq.S */ 1430/* File: arm/bincmp.S */ 1431 /* 1432 * Generic two-operand compare-and-branch operation. Provide a "condition" 1433 * fragment that specifies the comparison to perform. 1434 * 1435 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1436 */ 1437 /* if-cmp vA, vB, +CCCC */ 1438 mov r1, rINST, lsr #12 @ r1<- B 1439 ubfx r0, rINST, #8, #4 @ r0<- A 1440 GET_VREG r3, r1 @ r3<- vB 1441 GET_VREG r0, r0 @ r0<- vA 1442 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1443 cmp r0, r3 @ compare (vA, vB) 1444 beq MterpCommonTakenBranchNoFlags 1445 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1446 beq .L_check_not_taken_osr 1447 FETCH_ADVANCE_INST 2 1448 GET_INST_OPCODE ip @ extract opcode from rINST 1449 GOTO_OPCODE ip @ jump to next instruction 1450 1451 1452/* ------------------------------ */ 1453 .balign 128 1454.L_op_if_ne: /* 0x33 */ 1455/* File: arm/op_if_ne.S */ 1456/* File: arm/bincmp.S */ 1457 /* 1458 * Generic two-operand compare-and-branch operation. Provide a "condition" 1459 * fragment that specifies the comparison to perform. 1460 * 1461 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1462 */ 1463 /* if-cmp vA, vB, +CCCC */ 1464 mov r1, rINST, lsr #12 @ r1<- B 1465 ubfx r0, rINST, #8, #4 @ r0<- A 1466 GET_VREG r3, r1 @ r3<- vB 1467 GET_VREG r0, r0 @ r0<- vA 1468 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1469 cmp r0, r3 @ compare (vA, vB) 1470 bne MterpCommonTakenBranchNoFlags 1471 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1472 beq .L_check_not_taken_osr 1473 FETCH_ADVANCE_INST 2 1474 GET_INST_OPCODE ip @ extract opcode from rINST 1475 GOTO_OPCODE ip @ jump to next instruction 1476 1477 1478/* ------------------------------ */ 1479 .balign 128 1480.L_op_if_lt: /* 0x34 */ 1481/* File: arm/op_if_lt.S */ 1482/* File: arm/bincmp.S */ 1483 /* 1484 * Generic two-operand compare-and-branch operation. Provide a "condition" 1485 * fragment that specifies the comparison to perform. 1486 * 1487 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1488 */ 1489 /* if-cmp vA, vB, +CCCC */ 1490 mov r1, rINST, lsr #12 @ r1<- B 1491 ubfx r0, rINST, #8, #4 @ r0<- A 1492 GET_VREG r3, r1 @ r3<- vB 1493 GET_VREG r0, r0 @ r0<- vA 1494 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1495 cmp r0, r3 @ compare (vA, vB) 1496 blt MterpCommonTakenBranchNoFlags 1497 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1498 beq .L_check_not_taken_osr 1499 FETCH_ADVANCE_INST 2 1500 GET_INST_OPCODE ip @ extract opcode from rINST 1501 GOTO_OPCODE ip @ jump to next instruction 1502 1503 1504/* ------------------------------ */ 1505 .balign 128 1506.L_op_if_ge: /* 0x35 */ 1507/* File: arm/op_if_ge.S */ 1508/* File: arm/bincmp.S */ 1509 /* 1510 * Generic two-operand compare-and-branch operation. Provide a "condition" 1511 * fragment that specifies the comparison to perform. 1512 * 1513 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1514 */ 1515 /* if-cmp vA, vB, +CCCC */ 1516 mov r1, rINST, lsr #12 @ r1<- B 1517 ubfx r0, rINST, #8, #4 @ r0<- A 1518 GET_VREG r3, r1 @ r3<- vB 1519 GET_VREG r0, r0 @ r0<- vA 1520 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1521 cmp r0, r3 @ compare (vA, vB) 1522 bge MterpCommonTakenBranchNoFlags 1523 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1524 beq .L_check_not_taken_osr 1525 FETCH_ADVANCE_INST 2 1526 GET_INST_OPCODE ip @ extract opcode from rINST 1527 GOTO_OPCODE ip @ jump to next instruction 1528 1529 1530/* ------------------------------ */ 1531 .balign 128 1532.L_op_if_gt: /* 0x36 */ 1533/* File: arm/op_if_gt.S */ 1534/* File: arm/bincmp.S */ 1535 /* 1536 * Generic two-operand compare-and-branch operation. Provide a "condition" 1537 * fragment that specifies the comparison to perform. 1538 * 1539 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1540 */ 1541 /* if-cmp vA, vB, +CCCC */ 1542 mov r1, rINST, lsr #12 @ r1<- B 1543 ubfx r0, rINST, #8, #4 @ r0<- A 1544 GET_VREG r3, r1 @ r3<- vB 1545 GET_VREG r0, r0 @ r0<- vA 1546 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1547 cmp r0, r3 @ compare (vA, vB) 1548 bgt MterpCommonTakenBranchNoFlags 1549 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1550 beq .L_check_not_taken_osr 1551 FETCH_ADVANCE_INST 2 1552 GET_INST_OPCODE ip @ extract opcode from rINST 1553 GOTO_OPCODE ip @ jump to next instruction 1554 1555 1556/* ------------------------------ */ 1557 .balign 128 1558.L_op_if_le: /* 0x37 */ 1559/* File: arm/op_if_le.S */ 1560/* File: arm/bincmp.S */ 1561 /* 1562 * Generic two-operand compare-and-branch operation. Provide a "condition" 1563 * fragment that specifies the comparison to perform. 1564 * 1565 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1566 */ 1567 /* if-cmp vA, vB, +CCCC */ 1568 mov r1, rINST, lsr #12 @ r1<- B 1569 ubfx r0, rINST, #8, #4 @ r0<- A 1570 GET_VREG r3, r1 @ r3<- vB 1571 GET_VREG r0, r0 @ r0<- vA 1572 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1573 cmp r0, r3 @ compare (vA, vB) 1574 ble MterpCommonTakenBranchNoFlags 1575 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1576 beq .L_check_not_taken_osr 1577 FETCH_ADVANCE_INST 2 1578 GET_INST_OPCODE ip @ extract opcode from rINST 1579 GOTO_OPCODE ip @ jump to next instruction 1580 1581 1582/* ------------------------------ */ 1583 .balign 128 1584.L_op_if_eqz: /* 0x38 */ 1585/* File: arm/op_if_eqz.S */ 1586/* File: arm/zcmp.S */ 1587 /* 1588 * Generic one-operand compare-and-branch operation. Provide a "condition" 1589 * fragment that specifies the comparison to perform. 1590 * 1591 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1592 */ 1593 /* if-cmp vAA, +BBBB */ 1594 mov r0, rINST, lsr #8 @ r0<- AA 1595 GET_VREG r0, r0 @ r0<- vAA 1596 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1597 cmp r0, #0 @ compare (vA, 0) 1598 beq MterpCommonTakenBranchNoFlags 1599 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1600 beq .L_check_not_taken_osr 1601 FETCH_ADVANCE_INST 2 1602 GET_INST_OPCODE ip @ extract opcode from rINST 1603 GOTO_OPCODE ip @ jump to next instruction 1604 1605 1606/* ------------------------------ */ 1607 .balign 128 1608.L_op_if_nez: /* 0x39 */ 1609/* File: arm/op_if_nez.S */ 1610/* File: arm/zcmp.S */ 1611 /* 1612 * Generic one-operand compare-and-branch operation. Provide a "condition" 1613 * fragment that specifies the comparison to perform. 1614 * 1615 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1616 */ 1617 /* if-cmp vAA, +BBBB */ 1618 mov r0, rINST, lsr #8 @ r0<- AA 1619 GET_VREG r0, r0 @ r0<- vAA 1620 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1621 cmp r0, #0 @ compare (vA, 0) 1622 bne MterpCommonTakenBranchNoFlags 1623 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1624 beq .L_check_not_taken_osr 1625 FETCH_ADVANCE_INST 2 1626 GET_INST_OPCODE ip @ extract opcode from rINST 1627 GOTO_OPCODE ip @ jump to next instruction 1628 1629 1630/* ------------------------------ */ 1631 .balign 128 1632.L_op_if_ltz: /* 0x3a */ 1633/* File: arm/op_if_ltz.S */ 1634/* File: arm/zcmp.S */ 1635 /* 1636 * Generic one-operand compare-and-branch operation. Provide a "condition" 1637 * fragment that specifies the comparison to perform. 1638 * 1639 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1640 */ 1641 /* if-cmp vAA, +BBBB */ 1642 mov r0, rINST, lsr #8 @ r0<- AA 1643 GET_VREG r0, r0 @ r0<- vAA 1644 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1645 cmp r0, #0 @ compare (vA, 0) 1646 blt MterpCommonTakenBranchNoFlags 1647 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1648 beq .L_check_not_taken_osr 1649 FETCH_ADVANCE_INST 2 1650 GET_INST_OPCODE ip @ extract opcode from rINST 1651 GOTO_OPCODE ip @ jump to next instruction 1652 1653 1654/* ------------------------------ */ 1655 .balign 128 1656.L_op_if_gez: /* 0x3b */ 1657/* File: arm/op_if_gez.S */ 1658/* File: arm/zcmp.S */ 1659 /* 1660 * Generic one-operand compare-and-branch operation. Provide a "condition" 1661 * fragment that specifies the comparison to perform. 1662 * 1663 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1664 */ 1665 /* if-cmp vAA, +BBBB */ 1666 mov r0, rINST, lsr #8 @ r0<- AA 1667 GET_VREG r0, r0 @ r0<- vAA 1668 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1669 cmp r0, #0 @ compare (vA, 0) 1670 bge MterpCommonTakenBranchNoFlags 1671 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1672 beq .L_check_not_taken_osr 1673 FETCH_ADVANCE_INST 2 1674 GET_INST_OPCODE ip @ extract opcode from rINST 1675 GOTO_OPCODE ip @ jump to next instruction 1676 1677 1678/* ------------------------------ */ 1679 .balign 128 1680.L_op_if_gtz: /* 0x3c */ 1681/* File: arm/op_if_gtz.S */ 1682/* File: arm/zcmp.S */ 1683 /* 1684 * Generic one-operand compare-and-branch operation. Provide a "condition" 1685 * fragment that specifies the comparison to perform. 1686 * 1687 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1688 */ 1689 /* if-cmp vAA, +BBBB */ 1690 mov r0, rINST, lsr #8 @ r0<- AA 1691 GET_VREG r0, r0 @ r0<- vAA 1692 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1693 cmp r0, #0 @ compare (vA, 0) 1694 bgt MterpCommonTakenBranchNoFlags 1695 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1696 beq .L_check_not_taken_osr 1697 FETCH_ADVANCE_INST 2 1698 GET_INST_OPCODE ip @ extract opcode from rINST 1699 GOTO_OPCODE ip @ jump to next instruction 1700 1701 1702/* ------------------------------ */ 1703 .balign 128 1704.L_op_if_lez: /* 0x3d */ 1705/* File: arm/op_if_lez.S */ 1706/* File: arm/zcmp.S */ 1707 /* 1708 * Generic one-operand compare-and-branch operation. Provide a "condition" 1709 * fragment that specifies the comparison to perform. 1710 * 1711 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1712 */ 1713 /* if-cmp vAA, +BBBB */ 1714 mov r0, rINST, lsr #8 @ r0<- AA 1715 GET_VREG r0, r0 @ r0<- vAA 1716 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1717 cmp r0, #0 @ compare (vA, 0) 1718 ble MterpCommonTakenBranchNoFlags 1719 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1720 beq .L_check_not_taken_osr 1721 FETCH_ADVANCE_INST 2 1722 GET_INST_OPCODE ip @ extract opcode from rINST 1723 GOTO_OPCODE ip @ jump to next instruction 1724 1725 1726/* ------------------------------ */ 1727 .balign 128 1728.L_op_unused_3e: /* 0x3e */ 1729/* File: arm/op_unused_3e.S */ 1730/* File: arm/unused.S */ 1731/* 1732 * Bail to reference interpreter to throw. 1733 */ 1734 b MterpFallback 1735 1736 1737/* ------------------------------ */ 1738 .balign 128 1739.L_op_unused_3f: /* 0x3f */ 1740/* File: arm/op_unused_3f.S */ 1741/* File: arm/unused.S */ 1742/* 1743 * Bail to reference interpreter to throw. 1744 */ 1745 b MterpFallback 1746 1747 1748/* ------------------------------ */ 1749 .balign 128 1750.L_op_unused_40: /* 0x40 */ 1751/* File: arm/op_unused_40.S */ 1752/* File: arm/unused.S */ 1753/* 1754 * Bail to reference interpreter to throw. 1755 */ 1756 b MterpFallback 1757 1758 1759/* ------------------------------ */ 1760 .balign 128 1761.L_op_unused_41: /* 0x41 */ 1762/* File: arm/op_unused_41.S */ 1763/* File: arm/unused.S */ 1764/* 1765 * Bail to reference interpreter to throw. 1766 */ 1767 b MterpFallback 1768 1769 1770/* ------------------------------ */ 1771 .balign 128 1772.L_op_unused_42: /* 0x42 */ 1773/* File: arm/op_unused_42.S */ 1774/* File: arm/unused.S */ 1775/* 1776 * Bail to reference interpreter to throw. 1777 */ 1778 b MterpFallback 1779 1780 1781/* ------------------------------ */ 1782 .balign 128 1783.L_op_unused_43: /* 0x43 */ 1784/* File: arm/op_unused_43.S */ 1785/* File: arm/unused.S */ 1786/* 1787 * Bail to reference interpreter to throw. 1788 */ 1789 b MterpFallback 1790 1791 1792/* ------------------------------ */ 1793 .balign 128 1794.L_op_aget: /* 0x44 */ 1795/* File: arm/op_aget.S */ 1796 /* 1797 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1798 * 1799 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1800 * instructions. We use a pair of FETCH_Bs instead. 1801 * 1802 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1803 * 1804 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1805 * If this changes, specialize. 1806 */ 1807 /* op vAA, vBB, vCC */ 1808 FETCH_B r2, 1, 0 @ r2<- BB 1809 mov r9, rINST, lsr #8 @ r9<- AA 1810 FETCH_B r3, 1, 1 @ r3<- CC 1811 GET_VREG r0, r2 @ r0<- vBB (array object) 1812 GET_VREG r1, r3 @ r1<- vCC (requested index) 1813 cmp r0, #0 @ null array object? 1814 beq common_errNullObject @ yes, bail 1815 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1816 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1817 cmp r1, r3 @ compare unsigned index, length 1818 bcs common_errArrayIndex @ index >= length, bail 1819 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1820 ldr r2, [r0, #MIRROR_INT_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] 1821 GET_INST_OPCODE ip @ extract opcode from rINST 1822 SET_VREG r2, r9 @ vAA<- r2 1823 GOTO_OPCODE ip @ jump to next instruction 1824 1825/* ------------------------------ */ 1826 .balign 128 1827.L_op_aget_wide: /* 0x45 */ 1828/* File: arm/op_aget_wide.S */ 1829 /* 1830 * Array get, 64 bits. vAA <- vBB[vCC]. 1831 * 1832 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 1833 */ 1834 /* aget-wide vAA, vBB, vCC */ 1835 FETCH r0, 1 @ r0<- CCBB 1836 mov r9, rINST, lsr #8 @ r9<- AA 1837 and r2, r0, #255 @ r2<- BB 1838 mov r3, r0, lsr #8 @ r3<- CC 1839 GET_VREG r0, r2 @ r0<- vBB (array object) 1840 GET_VREG r1, r3 @ r1<- vCC (requested index) 1841 cmp r0, #0 @ null array object? 1842 beq common_errNullObject @ yes, bail 1843 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1844 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 1845 cmp r1, r3 @ compare unsigned index, length 1846 bcs common_errArrayIndex @ index >= length, bail 1847 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1848 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 1849 ldrd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] 1850 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 1851 GET_INST_OPCODE ip @ extract opcode from rINST 1852 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 1853 GOTO_OPCODE ip @ jump to next instruction 1854 1855/* ------------------------------ */ 1856 .balign 128 1857.L_op_aget_object: /* 0x46 */ 1858/* File: arm/op_aget_object.S */ 1859 /* 1860 * Array object get. vAA <- vBB[vCC]. 1861 * 1862 * for: aget-object 1863 */ 1864 /* op vAA, vBB, vCC */ 1865 FETCH_B r2, 1, 0 @ r2<- BB 1866 mov r9, rINST, lsr #8 @ r9<- AA 1867 FETCH_B r3, 1, 1 @ r3<- CC 1868 EXPORT_PC 1869 GET_VREG r0, r2 @ r0<- vBB (array object) 1870 GET_VREG r1, r3 @ r1<- vCC (requested index) 1871 bl artAGetObjectFromMterp @ (array, index) 1872 ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] 1873 PREFETCH_INST 2 1874 cmp r1, #0 1875 bne MterpException 1876 SET_VREG_OBJECT r0, r9 1877 ADVANCE 2 1878 GET_INST_OPCODE ip 1879 GOTO_OPCODE ip @ jump to next instruction 1880 1881/* ------------------------------ */ 1882 .balign 128 1883.L_op_aget_boolean: /* 0x47 */ 1884/* File: arm/op_aget_boolean.S */ 1885/* File: arm/op_aget.S */ 1886 /* 1887 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1888 * 1889 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1890 * instructions. We use a pair of FETCH_Bs instead. 1891 * 1892 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1893 * 1894 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1895 * If this changes, specialize. 1896 */ 1897 /* op vAA, vBB, vCC */ 1898 FETCH_B r2, 1, 0 @ r2<- BB 1899 mov r9, rINST, lsr #8 @ r9<- AA 1900 FETCH_B r3, 1, 1 @ r3<- CC 1901 GET_VREG r0, r2 @ r0<- vBB (array object) 1902 GET_VREG r1, r3 @ r1<- vCC (requested index) 1903 cmp r0, #0 @ null array object? 1904 beq common_errNullObject @ yes, bail 1905 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1906 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 1907 cmp r1, r3 @ compare unsigned index, length 1908 bcs common_errArrayIndex @ index >= length, bail 1909 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1910 ldrb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] 1911 GET_INST_OPCODE ip @ extract opcode from rINST 1912 SET_VREG r2, r9 @ vAA<- r2 1913 GOTO_OPCODE ip @ jump to next instruction 1914 1915 1916/* ------------------------------ */ 1917 .balign 128 1918.L_op_aget_byte: /* 0x48 */ 1919/* File: arm/op_aget_byte.S */ 1920/* File: arm/op_aget.S */ 1921 /* 1922 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1923 * 1924 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1925 * instructions. We use a pair of FETCH_Bs instead. 1926 * 1927 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1928 * 1929 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1930 * If this changes, specialize. 1931 */ 1932 /* op vAA, vBB, vCC */ 1933 FETCH_B r2, 1, 0 @ r2<- BB 1934 mov r9, rINST, lsr #8 @ r9<- AA 1935 FETCH_B r3, 1, 1 @ r3<- CC 1936 GET_VREG r0, r2 @ r0<- vBB (array object) 1937 GET_VREG r1, r3 @ r1<- vCC (requested index) 1938 cmp r0, #0 @ null array object? 1939 beq common_errNullObject @ yes, bail 1940 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1941 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 1942 cmp r1, r3 @ compare unsigned index, length 1943 bcs common_errArrayIndex @ index >= length, bail 1944 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1945 ldrsb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] 1946 GET_INST_OPCODE ip @ extract opcode from rINST 1947 SET_VREG r2, r9 @ vAA<- r2 1948 GOTO_OPCODE ip @ jump to next instruction 1949 1950 1951/* ------------------------------ */ 1952 .balign 128 1953.L_op_aget_char: /* 0x49 */ 1954/* File: arm/op_aget_char.S */ 1955/* File: arm/op_aget.S */ 1956 /* 1957 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1958 * 1959 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1960 * instructions. We use a pair of FETCH_Bs instead. 1961 * 1962 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1963 * 1964 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1965 * If this changes, specialize. 1966 */ 1967 /* op vAA, vBB, vCC */ 1968 FETCH_B r2, 1, 0 @ r2<- BB 1969 mov r9, rINST, lsr #8 @ r9<- AA 1970 FETCH_B r3, 1, 1 @ r3<- CC 1971 GET_VREG r0, r2 @ r0<- vBB (array object) 1972 GET_VREG r1, r3 @ r1<- vCC (requested index) 1973 cmp r0, #0 @ null array object? 1974 beq common_errNullObject @ yes, bail 1975 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1976 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 1977 cmp r1, r3 @ compare unsigned index, length 1978 bcs common_errArrayIndex @ index >= length, bail 1979 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1980 ldrh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] 1981 GET_INST_OPCODE ip @ extract opcode from rINST 1982 SET_VREG r2, r9 @ vAA<- r2 1983 GOTO_OPCODE ip @ jump to next instruction 1984 1985 1986/* ------------------------------ */ 1987 .balign 128 1988.L_op_aget_short: /* 0x4a */ 1989/* File: arm/op_aget_short.S */ 1990/* File: arm/op_aget.S */ 1991 /* 1992 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1993 * 1994 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1995 * instructions. We use a pair of FETCH_Bs instead. 1996 * 1997 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1998 * 1999 * NOTE: assumes data offset for arrays is the same for all non-wide types. 2000 * If this changes, specialize. 2001 */ 2002 /* op vAA, vBB, vCC */ 2003 FETCH_B r2, 1, 0 @ r2<- BB 2004 mov r9, rINST, lsr #8 @ r9<- AA 2005 FETCH_B r3, 1, 1 @ r3<- CC 2006 GET_VREG r0, r2 @ r0<- vBB (array object) 2007 GET_VREG r1, r3 @ r1<- vCC (requested index) 2008 cmp r0, #0 @ null array object? 2009 beq common_errNullObject @ yes, bail 2010 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2011 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2012 cmp r1, r3 @ compare unsigned index, length 2013 bcs common_errArrayIndex @ index >= length, bail 2014 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2015 ldrsh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] 2016 GET_INST_OPCODE ip @ extract opcode from rINST 2017 SET_VREG r2, r9 @ vAA<- r2 2018 GOTO_OPCODE ip @ jump to next instruction 2019 2020 2021/* ------------------------------ */ 2022 .balign 128 2023.L_op_aput: /* 0x4b */ 2024/* File: arm/op_aput.S */ 2025 /* 2026 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2027 * 2028 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2029 * instructions. We use a pair of FETCH_Bs instead. 2030 * 2031 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2032 * 2033 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2034 * If this changes, specialize. 2035 */ 2036 /* op vAA, vBB, vCC */ 2037 FETCH_B r2, 1, 0 @ r2<- BB 2038 mov r9, rINST, lsr #8 @ r9<- AA 2039 FETCH_B r3, 1, 1 @ r3<- CC 2040 GET_VREG r0, r2 @ r0<- vBB (array object) 2041 GET_VREG r1, r3 @ r1<- vCC (requested index) 2042 cmp r0, #0 @ null array object? 2043 beq common_errNullObject @ yes, bail 2044 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2045 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2046 cmp r1, r3 @ compare unsigned index, length 2047 bcs common_errArrayIndex @ index >= length, bail 2048 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2049 GET_VREG r2, r9 @ r2<- vAA 2050 GET_INST_OPCODE ip @ extract opcode from rINST 2051 str r2, [r0, #MIRROR_INT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 2052 GOTO_OPCODE ip @ jump to next instruction 2053 2054/* ------------------------------ */ 2055 .balign 128 2056.L_op_aput_wide: /* 0x4c */ 2057/* File: arm/op_aput_wide.S */ 2058 /* 2059 * Array put, 64 bits. vBB[vCC] <- vAA. 2060 * 2061 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2062 */ 2063 /* aput-wide vAA, vBB, vCC */ 2064 FETCH r0, 1 @ r0<- CCBB 2065 mov r9, rINST, lsr #8 @ r9<- AA 2066 and r2, r0, #255 @ r2<- BB 2067 mov r3, r0, lsr #8 @ r3<- CC 2068 GET_VREG r0, r2 @ r0<- vBB (array object) 2069 GET_VREG r1, r3 @ r1<- vCC (requested index) 2070 cmp r0, #0 @ null array object? 2071 beq common_errNullObject @ yes, bail 2072 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2073 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2074 cmp r1, r3 @ compare unsigned index, length 2075 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 2076 bcs common_errArrayIndex @ index >= length, bail 2077 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2078 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 2079 GET_INST_OPCODE ip @ extract opcode from rINST 2080 strd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] 2081 GOTO_OPCODE ip @ jump to next instruction 2082 2083/* ------------------------------ */ 2084 .balign 128 2085.L_op_aput_object: /* 0x4d */ 2086/* File: arm/op_aput_object.S */ 2087 /* 2088 * Store an object into an array. vBB[vCC] <- vAA. 2089 */ 2090 /* op vAA, vBB, vCC */ 2091 EXPORT_PC 2092 add r0, rFP, #OFF_FP_SHADOWFRAME 2093 mov r1, rPC 2094 mov r2, rINST 2095 bl MterpAputObject 2096 cmp r0, #0 2097 beq MterpPossibleException 2098 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2099 GET_INST_OPCODE ip @ extract opcode from rINST 2100 GOTO_OPCODE ip @ jump to next instruction 2101 2102/* ------------------------------ */ 2103 .balign 128 2104.L_op_aput_boolean: /* 0x4e */ 2105/* File: arm/op_aput_boolean.S */ 2106/* File: arm/op_aput.S */ 2107 /* 2108 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2109 * 2110 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2111 * instructions. We use a pair of FETCH_Bs instead. 2112 * 2113 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2114 * 2115 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2116 * If this changes, specialize. 2117 */ 2118 /* op vAA, vBB, vCC */ 2119 FETCH_B r2, 1, 0 @ r2<- BB 2120 mov r9, rINST, lsr #8 @ r9<- AA 2121 FETCH_B r3, 1, 1 @ r3<- CC 2122 GET_VREG r0, r2 @ r0<- vBB (array object) 2123 GET_VREG r1, r3 @ r1<- vCC (requested index) 2124 cmp r0, #0 @ null array object? 2125 beq common_errNullObject @ yes, bail 2126 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2127 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2128 cmp r1, r3 @ compare unsigned index, length 2129 bcs common_errArrayIndex @ index >= length, bail 2130 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2131 GET_VREG r2, r9 @ r2<- vAA 2132 GET_INST_OPCODE ip @ extract opcode from rINST 2133 strb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 2134 GOTO_OPCODE ip @ jump to next instruction 2135 2136 2137/* ------------------------------ */ 2138 .balign 128 2139.L_op_aput_byte: /* 0x4f */ 2140/* File: arm/op_aput_byte.S */ 2141/* File: arm/op_aput.S */ 2142 /* 2143 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2144 * 2145 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2146 * instructions. We use a pair of FETCH_Bs instead. 2147 * 2148 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2149 * 2150 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2151 * If this changes, specialize. 2152 */ 2153 /* op vAA, vBB, vCC */ 2154 FETCH_B r2, 1, 0 @ r2<- BB 2155 mov r9, rINST, lsr #8 @ r9<- AA 2156 FETCH_B r3, 1, 1 @ r3<- CC 2157 GET_VREG r0, r2 @ r0<- vBB (array object) 2158 GET_VREG r1, r3 @ r1<- vCC (requested index) 2159 cmp r0, #0 @ null array object? 2160 beq common_errNullObject @ yes, bail 2161 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2162 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2163 cmp r1, r3 @ compare unsigned index, length 2164 bcs common_errArrayIndex @ index >= length, bail 2165 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2166 GET_VREG r2, r9 @ r2<- vAA 2167 GET_INST_OPCODE ip @ extract opcode from rINST 2168 strb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 2169 GOTO_OPCODE ip @ jump to next instruction 2170 2171 2172/* ------------------------------ */ 2173 .balign 128 2174.L_op_aput_char: /* 0x50 */ 2175/* File: arm/op_aput_char.S */ 2176/* File: arm/op_aput.S */ 2177 /* 2178 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2179 * 2180 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2181 * instructions. We use a pair of FETCH_Bs instead. 2182 * 2183 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2184 * 2185 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2186 * If this changes, specialize. 2187 */ 2188 /* op vAA, vBB, vCC */ 2189 FETCH_B r2, 1, 0 @ r2<- BB 2190 mov r9, rINST, lsr #8 @ r9<- AA 2191 FETCH_B r3, 1, 1 @ r3<- CC 2192 GET_VREG r0, r2 @ r0<- vBB (array object) 2193 GET_VREG r1, r3 @ r1<- vCC (requested index) 2194 cmp r0, #0 @ null array object? 2195 beq common_errNullObject @ yes, bail 2196 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2197 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2198 cmp r1, r3 @ compare unsigned index, length 2199 bcs common_errArrayIndex @ index >= length, bail 2200 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2201 GET_VREG r2, r9 @ r2<- vAA 2202 GET_INST_OPCODE ip @ extract opcode from rINST 2203 strh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 2204 GOTO_OPCODE ip @ jump to next instruction 2205 2206 2207/* ------------------------------ */ 2208 .balign 128 2209.L_op_aput_short: /* 0x51 */ 2210/* File: arm/op_aput_short.S */ 2211/* File: arm/op_aput.S */ 2212 /* 2213 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2214 * 2215 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2216 * instructions. We use a pair of FETCH_Bs instead. 2217 * 2218 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2219 * 2220 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2221 * If this changes, specialize. 2222 */ 2223 /* op vAA, vBB, vCC */ 2224 FETCH_B r2, 1, 0 @ r2<- BB 2225 mov r9, rINST, lsr #8 @ r9<- AA 2226 FETCH_B r3, 1, 1 @ r3<- CC 2227 GET_VREG r0, r2 @ r0<- vBB (array object) 2228 GET_VREG r1, r3 @ r1<- vCC (requested index) 2229 cmp r0, #0 @ null array object? 2230 beq common_errNullObject @ yes, bail 2231 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2232 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2233 cmp r1, r3 @ compare unsigned index, length 2234 bcs common_errArrayIndex @ index >= length, bail 2235 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2236 GET_VREG r2, r9 @ r2<- vAA 2237 GET_INST_OPCODE ip @ extract opcode from rINST 2238 strh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 2239 GOTO_OPCODE ip @ jump to next instruction 2240 2241 2242/* ------------------------------ */ 2243 .balign 128 2244.L_op_iget: /* 0x52 */ 2245/* File: arm/op_iget.S */ 2246 /* 2247 * General instance field get. 2248 * 2249 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2250 */ 2251 EXPORT_PC 2252 FETCH r0, 1 @ r0<- field ref CCCC 2253 mov r1, rINST, lsr #12 @ r1<- B 2254 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2255 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2256 mov r3, rSELF @ r3<- self 2257 bl artGet32InstanceFromCode 2258 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2259 ubfx r2, rINST, #8, #4 @ r2<- A 2260 PREFETCH_INST 2 2261 cmp r3, #0 2262 bne MterpPossibleException @ bail out 2263 .if 0 2264 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2265 .else 2266 SET_VREG r0, r2 @ fp[A]<- r0 2267 .endif 2268 ADVANCE 2 2269 GET_INST_OPCODE ip @ extract opcode from rINST 2270 GOTO_OPCODE ip @ jump to next instruction 2271 2272/* ------------------------------ */ 2273 .balign 128 2274.L_op_iget_wide: /* 0x53 */ 2275/* File: arm/op_iget_wide.S */ 2276 /* 2277 * 64-bit instance field get. 2278 * 2279 * for: iget-wide 2280 */ 2281 EXPORT_PC 2282 FETCH r0, 1 @ r0<- field ref CCCC 2283 mov r1, rINST, lsr #12 @ r1<- B 2284 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2285 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2286 mov r3, rSELF @ r3<- self 2287 bl artGet64InstanceFromCode 2288 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2289 ubfx r2, rINST, #8, #4 @ r2<- A 2290 PREFETCH_INST 2 2291 cmp r3, #0 2292 bne MterpException @ bail out 2293 CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs 2294 VREG_INDEX_TO_ADDR r3, r2 @ r3<- &fp[A] 2295 stmia r3, {r0-r1} @ fp[A]<- r0/r1 2296 ADVANCE 2 2297 GET_INST_OPCODE ip @ extract opcode from rINST 2298 GOTO_OPCODE ip @ jump to next instruction 2299 2300/* ------------------------------ */ 2301 .balign 128 2302.L_op_iget_object: /* 0x54 */ 2303/* File: arm/op_iget_object.S */ 2304/* File: arm/op_iget.S */ 2305 /* 2306 * General instance field get. 2307 * 2308 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2309 */ 2310 EXPORT_PC 2311 FETCH r0, 1 @ r0<- field ref CCCC 2312 mov r1, rINST, lsr #12 @ r1<- B 2313 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2314 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2315 mov r3, rSELF @ r3<- self 2316 bl artGetObjInstanceFromCode 2317 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2318 ubfx r2, rINST, #8, #4 @ r2<- A 2319 PREFETCH_INST 2 2320 cmp r3, #0 2321 bne MterpPossibleException @ bail out 2322 .if 1 2323 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2324 .else 2325 SET_VREG r0, r2 @ fp[A]<- r0 2326 .endif 2327 ADVANCE 2 2328 GET_INST_OPCODE ip @ extract opcode from rINST 2329 GOTO_OPCODE ip @ jump to next instruction 2330 2331 2332/* ------------------------------ */ 2333 .balign 128 2334.L_op_iget_boolean: /* 0x55 */ 2335/* File: arm/op_iget_boolean.S */ 2336/* File: arm/op_iget.S */ 2337 /* 2338 * General instance field get. 2339 * 2340 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2341 */ 2342 EXPORT_PC 2343 FETCH r0, 1 @ r0<- field ref CCCC 2344 mov r1, rINST, lsr #12 @ r1<- B 2345 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2346 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2347 mov r3, rSELF @ r3<- self 2348 bl artGetBooleanInstanceFromCode 2349 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2350 ubfx r2, rINST, #8, #4 @ r2<- A 2351 PREFETCH_INST 2 2352 cmp r3, #0 2353 bne MterpPossibleException @ bail out 2354 .if 0 2355 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2356 .else 2357 SET_VREG r0, r2 @ fp[A]<- r0 2358 .endif 2359 ADVANCE 2 2360 GET_INST_OPCODE ip @ extract opcode from rINST 2361 GOTO_OPCODE ip @ jump to next instruction 2362 2363 2364/* ------------------------------ */ 2365 .balign 128 2366.L_op_iget_byte: /* 0x56 */ 2367/* File: arm/op_iget_byte.S */ 2368/* File: arm/op_iget.S */ 2369 /* 2370 * General instance field get. 2371 * 2372 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2373 */ 2374 EXPORT_PC 2375 FETCH r0, 1 @ r0<- field ref CCCC 2376 mov r1, rINST, lsr #12 @ r1<- B 2377 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2378 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2379 mov r3, rSELF @ r3<- self 2380 bl artGetByteInstanceFromCode 2381 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2382 ubfx r2, rINST, #8, #4 @ r2<- A 2383 PREFETCH_INST 2 2384 cmp r3, #0 2385 bne MterpPossibleException @ bail out 2386 .if 0 2387 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2388 .else 2389 SET_VREG r0, r2 @ fp[A]<- r0 2390 .endif 2391 ADVANCE 2 2392 GET_INST_OPCODE ip @ extract opcode from rINST 2393 GOTO_OPCODE ip @ jump to next instruction 2394 2395 2396/* ------------------------------ */ 2397 .balign 128 2398.L_op_iget_char: /* 0x57 */ 2399/* File: arm/op_iget_char.S */ 2400/* File: arm/op_iget.S */ 2401 /* 2402 * General instance field get. 2403 * 2404 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2405 */ 2406 EXPORT_PC 2407 FETCH r0, 1 @ r0<- field ref CCCC 2408 mov r1, rINST, lsr #12 @ r1<- B 2409 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2410 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2411 mov r3, rSELF @ r3<- self 2412 bl artGetCharInstanceFromCode 2413 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2414 ubfx r2, rINST, #8, #4 @ r2<- A 2415 PREFETCH_INST 2 2416 cmp r3, #0 2417 bne MterpPossibleException @ bail out 2418 .if 0 2419 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2420 .else 2421 SET_VREG r0, r2 @ fp[A]<- r0 2422 .endif 2423 ADVANCE 2 2424 GET_INST_OPCODE ip @ extract opcode from rINST 2425 GOTO_OPCODE ip @ jump to next instruction 2426 2427 2428/* ------------------------------ */ 2429 .balign 128 2430.L_op_iget_short: /* 0x58 */ 2431/* File: arm/op_iget_short.S */ 2432/* File: arm/op_iget.S */ 2433 /* 2434 * General instance field get. 2435 * 2436 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2437 */ 2438 EXPORT_PC 2439 FETCH r0, 1 @ r0<- field ref CCCC 2440 mov r1, rINST, lsr #12 @ r1<- B 2441 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2442 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2443 mov r3, rSELF @ r3<- self 2444 bl artGetShortInstanceFromCode 2445 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2446 ubfx r2, rINST, #8, #4 @ r2<- A 2447 PREFETCH_INST 2 2448 cmp r3, #0 2449 bne MterpPossibleException @ bail out 2450 .if 0 2451 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2452 .else 2453 SET_VREG r0, r2 @ fp[A]<- r0 2454 .endif 2455 ADVANCE 2 2456 GET_INST_OPCODE ip @ extract opcode from rINST 2457 GOTO_OPCODE ip @ jump to next instruction 2458 2459 2460/* ------------------------------ */ 2461 .balign 128 2462.L_op_iput: /* 0x59 */ 2463/* File: arm/op_iput.S */ 2464 /* 2465 * General 32-bit instance field put. 2466 * 2467 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2468 */ 2469 /* op vA, vB, field@CCCC */ 2470 .extern artSet32InstanceFromMterp 2471 EXPORT_PC 2472 FETCH r0, 1 @ r0<- field ref CCCC 2473 mov r1, rINST, lsr #12 @ r1<- B 2474 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2475 ubfx r2, rINST, #8, #4 @ r2<- A 2476 GET_VREG r2, r2 @ r2<- fp[A] 2477 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2478 PREFETCH_INST 2 2479 bl artSet32InstanceFromMterp 2480 cmp r0, #0 2481 bne MterpPossibleException 2482 ADVANCE 2 @ advance rPC 2483 GET_INST_OPCODE ip @ extract opcode from rINST 2484 GOTO_OPCODE ip @ jump to next instruction 2485 2486/* ------------------------------ */ 2487 .balign 128 2488.L_op_iput_wide: /* 0x5a */ 2489/* File: arm/op_iput_wide.S */ 2490 /* iput-wide vA, vB, field@CCCC */ 2491 .extern artSet64InstanceFromMterp 2492 EXPORT_PC 2493 FETCH r0, 1 @ r0<- field ref CCCC 2494 mov r1, rINST, lsr #12 @ r1<- B 2495 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2496 ubfx r2, rINST, #8, #4 @ r2<- A 2497 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[A] 2498 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2499 PREFETCH_INST 2 2500 bl artSet64InstanceFromMterp 2501 cmp r0, #0 2502 bne MterpPossibleException 2503 ADVANCE 2 @ advance rPC 2504 GET_INST_OPCODE ip @ extract opcode from rINST 2505 GOTO_OPCODE ip @ jump to next instruction 2506 2507/* ------------------------------ */ 2508 .balign 128 2509.L_op_iput_object: /* 0x5b */ 2510/* File: arm/op_iput_object.S */ 2511 EXPORT_PC 2512 add r0, rFP, #OFF_FP_SHADOWFRAME 2513 mov r1, rPC 2514 mov r2, rINST 2515 mov r3, rSELF 2516 bl MterpIputObject 2517 cmp r0, #0 2518 beq MterpException 2519 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2520 GET_INST_OPCODE ip @ extract opcode from rINST 2521 GOTO_OPCODE ip @ jump to next instruction 2522 2523/* ------------------------------ */ 2524 .balign 128 2525.L_op_iput_boolean: /* 0x5c */ 2526/* File: arm/op_iput_boolean.S */ 2527/* File: arm/op_iput.S */ 2528 /* 2529 * General 32-bit instance field put. 2530 * 2531 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2532 */ 2533 /* op vA, vB, field@CCCC */ 2534 .extern artSet8InstanceFromMterp 2535 EXPORT_PC 2536 FETCH r0, 1 @ r0<- field ref CCCC 2537 mov r1, rINST, lsr #12 @ r1<- B 2538 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2539 ubfx r2, rINST, #8, #4 @ r2<- A 2540 GET_VREG r2, r2 @ r2<- fp[A] 2541 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2542 PREFETCH_INST 2 2543 bl artSet8InstanceFromMterp 2544 cmp r0, #0 2545 bne MterpPossibleException 2546 ADVANCE 2 @ advance rPC 2547 GET_INST_OPCODE ip @ extract opcode from rINST 2548 GOTO_OPCODE ip @ jump to next instruction 2549 2550 2551/* ------------------------------ */ 2552 .balign 128 2553.L_op_iput_byte: /* 0x5d */ 2554/* File: arm/op_iput_byte.S */ 2555/* File: arm/op_iput.S */ 2556 /* 2557 * General 32-bit instance field put. 2558 * 2559 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2560 */ 2561 /* op vA, vB, field@CCCC */ 2562 .extern artSet8InstanceFromMterp 2563 EXPORT_PC 2564 FETCH r0, 1 @ r0<- field ref CCCC 2565 mov r1, rINST, lsr #12 @ r1<- B 2566 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2567 ubfx r2, rINST, #8, #4 @ r2<- A 2568 GET_VREG r2, r2 @ r2<- fp[A] 2569 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2570 PREFETCH_INST 2 2571 bl artSet8InstanceFromMterp 2572 cmp r0, #0 2573 bne MterpPossibleException 2574 ADVANCE 2 @ advance rPC 2575 GET_INST_OPCODE ip @ extract opcode from rINST 2576 GOTO_OPCODE ip @ jump to next instruction 2577 2578 2579/* ------------------------------ */ 2580 .balign 128 2581.L_op_iput_char: /* 0x5e */ 2582/* File: arm/op_iput_char.S */ 2583/* File: arm/op_iput.S */ 2584 /* 2585 * General 32-bit instance field put. 2586 * 2587 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2588 */ 2589 /* op vA, vB, field@CCCC */ 2590 .extern artSet16InstanceFromMterp 2591 EXPORT_PC 2592 FETCH r0, 1 @ r0<- field ref CCCC 2593 mov r1, rINST, lsr #12 @ r1<- B 2594 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2595 ubfx r2, rINST, #8, #4 @ r2<- A 2596 GET_VREG r2, r2 @ r2<- fp[A] 2597 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2598 PREFETCH_INST 2 2599 bl artSet16InstanceFromMterp 2600 cmp r0, #0 2601 bne MterpPossibleException 2602 ADVANCE 2 @ advance rPC 2603 GET_INST_OPCODE ip @ extract opcode from rINST 2604 GOTO_OPCODE ip @ jump to next instruction 2605 2606 2607/* ------------------------------ */ 2608 .balign 128 2609.L_op_iput_short: /* 0x5f */ 2610/* File: arm/op_iput_short.S */ 2611/* File: arm/op_iput.S */ 2612 /* 2613 * General 32-bit instance field put. 2614 * 2615 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2616 */ 2617 /* op vA, vB, field@CCCC */ 2618 .extern artSet16InstanceFromMterp 2619 EXPORT_PC 2620 FETCH r0, 1 @ r0<- field ref CCCC 2621 mov r1, rINST, lsr #12 @ r1<- B 2622 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2623 ubfx r2, rINST, #8, #4 @ r2<- A 2624 GET_VREG r2, r2 @ r2<- fp[A] 2625 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2626 PREFETCH_INST 2 2627 bl artSet16InstanceFromMterp 2628 cmp r0, #0 2629 bne MterpPossibleException 2630 ADVANCE 2 @ advance rPC 2631 GET_INST_OPCODE ip @ extract opcode from rINST 2632 GOTO_OPCODE ip @ jump to next instruction 2633 2634 2635/* ------------------------------ */ 2636 .balign 128 2637.L_op_sget: /* 0x60 */ 2638/* File: arm/op_sget.S */ 2639 /* 2640 * General SGET handler wrapper. 2641 * 2642 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2643 */ 2644 /* op vAA, field@BBBB */ 2645 2646 .extern MterpGet32Static 2647 EXPORT_PC 2648 FETCH r0, 1 @ r0<- field ref BBBB 2649 ldr r1, [rFP, #OFF_FP_METHOD] 2650 mov r2, rSELF 2651 bl MterpGet32Static 2652 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2653 mov r2, rINST, lsr #8 @ r2<- AA 2654 PREFETCH_INST 2 2655 cmp r3, #0 @ Fail to resolve? 2656 bne MterpException @ bail out 2657.if 0 2658 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2659.else 2660 SET_VREG r0, r2 @ fp[AA]<- r0 2661.endif 2662 ADVANCE 2 2663 GET_INST_OPCODE ip @ extract opcode from rINST 2664 GOTO_OPCODE ip 2665 2666/* ------------------------------ */ 2667 .balign 128 2668.L_op_sget_wide: /* 0x61 */ 2669/* File: arm/op_sget_wide.S */ 2670 /* 2671 * SGET_WIDE handler wrapper. 2672 * 2673 */ 2674 /* sget-wide vAA, field@BBBB */ 2675 2676 .extern MterpGet64Static 2677 EXPORT_PC 2678 FETCH r0, 1 @ r0<- field ref BBBB 2679 ldr r1, [rFP, #OFF_FP_METHOD] 2680 mov r2, rSELF 2681 bl MterpGet64Static 2682 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2683 mov r9, rINST, lsr #8 @ r9<- AA 2684 VREG_INDEX_TO_ADDR lr, r9 @ r9<- &fp[AA] 2685 cmp r3, #0 @ Fail to resolve? 2686 bne MterpException @ bail out 2687 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2688 CLEAR_SHADOW_PAIR r9, r2, ip @ Zero out the shadow regs 2689 stmia lr, {r0-r1} @ vAA/vAA+1<- r0/r1 2690 GET_INST_OPCODE ip @ extract opcode from rINST 2691 GOTO_OPCODE ip @ jump to next instruction 2692 2693/* ------------------------------ */ 2694 .balign 128 2695.L_op_sget_object: /* 0x62 */ 2696/* File: arm/op_sget_object.S */ 2697/* File: arm/op_sget.S */ 2698 /* 2699 * General SGET handler wrapper. 2700 * 2701 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2702 */ 2703 /* op vAA, field@BBBB */ 2704 2705 .extern MterpGetObjStatic 2706 EXPORT_PC 2707 FETCH r0, 1 @ r0<- field ref BBBB 2708 ldr r1, [rFP, #OFF_FP_METHOD] 2709 mov r2, rSELF 2710 bl MterpGetObjStatic 2711 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2712 mov r2, rINST, lsr #8 @ r2<- AA 2713 PREFETCH_INST 2 2714 cmp r3, #0 @ Fail to resolve? 2715 bne MterpException @ bail out 2716.if 1 2717 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2718.else 2719 SET_VREG r0, r2 @ fp[AA]<- r0 2720.endif 2721 ADVANCE 2 2722 GET_INST_OPCODE ip @ extract opcode from rINST 2723 GOTO_OPCODE ip 2724 2725 2726/* ------------------------------ */ 2727 .balign 128 2728.L_op_sget_boolean: /* 0x63 */ 2729/* File: arm/op_sget_boolean.S */ 2730/* File: arm/op_sget.S */ 2731 /* 2732 * General SGET handler wrapper. 2733 * 2734 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2735 */ 2736 /* op vAA, field@BBBB */ 2737 2738 .extern MterpGetBooleanStatic 2739 EXPORT_PC 2740 FETCH r0, 1 @ r0<- field ref BBBB 2741 ldr r1, [rFP, #OFF_FP_METHOD] 2742 mov r2, rSELF 2743 bl MterpGetBooleanStatic 2744 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2745 mov r2, rINST, lsr #8 @ r2<- AA 2746 PREFETCH_INST 2 2747 cmp r3, #0 @ Fail to resolve? 2748 bne MterpException @ bail out 2749.if 0 2750 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2751.else 2752 SET_VREG r0, r2 @ fp[AA]<- r0 2753.endif 2754 ADVANCE 2 2755 GET_INST_OPCODE ip @ extract opcode from rINST 2756 GOTO_OPCODE ip 2757 2758 2759/* ------------------------------ */ 2760 .balign 128 2761.L_op_sget_byte: /* 0x64 */ 2762/* File: arm/op_sget_byte.S */ 2763/* File: arm/op_sget.S */ 2764 /* 2765 * General SGET handler wrapper. 2766 * 2767 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2768 */ 2769 /* op vAA, field@BBBB */ 2770 2771 .extern MterpGetByteStatic 2772 EXPORT_PC 2773 FETCH r0, 1 @ r0<- field ref BBBB 2774 ldr r1, [rFP, #OFF_FP_METHOD] 2775 mov r2, rSELF 2776 bl MterpGetByteStatic 2777 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2778 mov r2, rINST, lsr #8 @ r2<- AA 2779 PREFETCH_INST 2 2780 cmp r3, #0 @ Fail to resolve? 2781 bne MterpException @ bail out 2782.if 0 2783 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2784.else 2785 SET_VREG r0, r2 @ fp[AA]<- r0 2786.endif 2787 ADVANCE 2 2788 GET_INST_OPCODE ip @ extract opcode from rINST 2789 GOTO_OPCODE ip 2790 2791 2792/* ------------------------------ */ 2793 .balign 128 2794.L_op_sget_char: /* 0x65 */ 2795/* File: arm/op_sget_char.S */ 2796/* File: arm/op_sget.S */ 2797 /* 2798 * General SGET handler wrapper. 2799 * 2800 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2801 */ 2802 /* op vAA, field@BBBB */ 2803 2804 .extern MterpGetCharStatic 2805 EXPORT_PC 2806 FETCH r0, 1 @ r0<- field ref BBBB 2807 ldr r1, [rFP, #OFF_FP_METHOD] 2808 mov r2, rSELF 2809 bl MterpGetCharStatic 2810 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2811 mov r2, rINST, lsr #8 @ r2<- AA 2812 PREFETCH_INST 2 2813 cmp r3, #0 @ Fail to resolve? 2814 bne MterpException @ bail out 2815.if 0 2816 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2817.else 2818 SET_VREG r0, r2 @ fp[AA]<- r0 2819.endif 2820 ADVANCE 2 2821 GET_INST_OPCODE ip @ extract opcode from rINST 2822 GOTO_OPCODE ip 2823 2824 2825/* ------------------------------ */ 2826 .balign 128 2827.L_op_sget_short: /* 0x66 */ 2828/* File: arm/op_sget_short.S */ 2829/* File: arm/op_sget.S */ 2830 /* 2831 * General SGET handler wrapper. 2832 * 2833 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2834 */ 2835 /* op vAA, field@BBBB */ 2836 2837 .extern MterpGetShortStatic 2838 EXPORT_PC 2839 FETCH r0, 1 @ r0<- field ref BBBB 2840 ldr r1, [rFP, #OFF_FP_METHOD] 2841 mov r2, rSELF 2842 bl MterpGetShortStatic 2843 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2844 mov r2, rINST, lsr #8 @ r2<- AA 2845 PREFETCH_INST 2 2846 cmp r3, #0 @ Fail to resolve? 2847 bne MterpException @ bail out 2848.if 0 2849 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2850.else 2851 SET_VREG r0, r2 @ fp[AA]<- r0 2852.endif 2853 ADVANCE 2 2854 GET_INST_OPCODE ip @ extract opcode from rINST 2855 GOTO_OPCODE ip 2856 2857 2858/* ------------------------------ */ 2859 .balign 128 2860.L_op_sput: /* 0x67 */ 2861/* File: arm/op_sput.S */ 2862 /* 2863 * General SPUT handler wrapper. 2864 * 2865 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2866 */ 2867 /* op vAA, field@BBBB */ 2868 EXPORT_PC 2869 FETCH r0, 1 @ r0<- field ref BBBB 2870 mov r3, rINST, lsr #8 @ r3<- AA 2871 GET_VREG r1, r3 @ r1<= fp[AA] 2872 ldr r2, [rFP, #OFF_FP_METHOD] 2873 mov r3, rSELF 2874 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 2875 bl MterpSet32Static 2876 cmp r0, #0 @ 0 on success, -1 on failure 2877 bne MterpException 2878 ADVANCE 2 @ Past exception point - now advance rPC 2879 GET_INST_OPCODE ip @ extract opcode from rINST 2880 GOTO_OPCODE ip @ jump to next instruction 2881 2882/* ------------------------------ */ 2883 .balign 128 2884.L_op_sput_wide: /* 0x68 */ 2885/* File: arm/op_sput_wide.S */ 2886 /* 2887 * SPUT_WIDE handler wrapper. 2888 * 2889 */ 2890 /* sput-wide vAA, field@BBBB */ 2891 .extern MterpSet64Static 2892 EXPORT_PC 2893 FETCH r0, 1 @ r0<- field ref BBBB 2894 mov r1, rINST, lsr #8 @ r1<- AA 2895 VREG_INDEX_TO_ADDR r1, r1 2896 ldr r2, [rFP, #OFF_FP_METHOD] 2897 mov r3, rSELF 2898 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 2899 bl MterpSet64Static 2900 cmp r0, #0 @ 0 on success, -1 on failure 2901 bne MterpException 2902 ADVANCE 2 @ Past exception point - now advance rPC 2903 GET_INST_OPCODE ip @ extract opcode from rINST 2904 GOTO_OPCODE ip @ jump to next instruction 2905 2906/* ------------------------------ */ 2907 .balign 128 2908.L_op_sput_object: /* 0x69 */ 2909/* File: arm/op_sput_object.S */ 2910 EXPORT_PC 2911 add r0, rFP, #OFF_FP_SHADOWFRAME 2912 mov r1, rPC 2913 mov r2, rINST 2914 mov r3, rSELF 2915 bl MterpSputObject 2916 cmp r0, #0 2917 beq MterpException 2918 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2919 GET_INST_OPCODE ip @ extract opcode from rINST 2920 GOTO_OPCODE ip @ jump to next instruction 2921 2922/* ------------------------------ */ 2923 .balign 128 2924.L_op_sput_boolean: /* 0x6a */ 2925/* File: arm/op_sput_boolean.S */ 2926/* File: arm/op_sput.S */ 2927 /* 2928 * General SPUT handler wrapper. 2929 * 2930 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2931 */ 2932 /* op vAA, field@BBBB */ 2933 EXPORT_PC 2934 FETCH r0, 1 @ r0<- field ref BBBB 2935 mov r3, rINST, lsr #8 @ r3<- AA 2936 GET_VREG r1, r3 @ r1<= fp[AA] 2937 ldr r2, [rFP, #OFF_FP_METHOD] 2938 mov r3, rSELF 2939 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 2940 bl MterpSetBooleanStatic 2941 cmp r0, #0 @ 0 on success, -1 on failure 2942 bne MterpException 2943 ADVANCE 2 @ Past exception point - now advance rPC 2944 GET_INST_OPCODE ip @ extract opcode from rINST 2945 GOTO_OPCODE ip @ jump to next instruction 2946 2947 2948/* ------------------------------ */ 2949 .balign 128 2950.L_op_sput_byte: /* 0x6b */ 2951/* File: arm/op_sput_byte.S */ 2952/* File: arm/op_sput.S */ 2953 /* 2954 * General SPUT handler wrapper. 2955 * 2956 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2957 */ 2958 /* op vAA, field@BBBB */ 2959 EXPORT_PC 2960 FETCH r0, 1 @ r0<- field ref BBBB 2961 mov r3, rINST, lsr #8 @ r3<- AA 2962 GET_VREG r1, r3 @ r1<= fp[AA] 2963 ldr r2, [rFP, #OFF_FP_METHOD] 2964 mov r3, rSELF 2965 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 2966 bl MterpSetByteStatic 2967 cmp r0, #0 @ 0 on success, -1 on failure 2968 bne MterpException 2969 ADVANCE 2 @ Past exception point - now advance rPC 2970 GET_INST_OPCODE ip @ extract opcode from rINST 2971 GOTO_OPCODE ip @ jump to next instruction 2972 2973 2974/* ------------------------------ */ 2975 .balign 128 2976.L_op_sput_char: /* 0x6c */ 2977/* File: arm/op_sput_char.S */ 2978/* File: arm/op_sput.S */ 2979 /* 2980 * General SPUT handler wrapper. 2981 * 2982 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2983 */ 2984 /* op vAA, field@BBBB */ 2985 EXPORT_PC 2986 FETCH r0, 1 @ r0<- field ref BBBB 2987 mov r3, rINST, lsr #8 @ r3<- AA 2988 GET_VREG r1, r3 @ r1<= fp[AA] 2989 ldr r2, [rFP, #OFF_FP_METHOD] 2990 mov r3, rSELF 2991 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 2992 bl MterpSetCharStatic 2993 cmp r0, #0 @ 0 on success, -1 on failure 2994 bne MterpException 2995 ADVANCE 2 @ Past exception point - now advance rPC 2996 GET_INST_OPCODE ip @ extract opcode from rINST 2997 GOTO_OPCODE ip @ jump to next instruction 2998 2999 3000/* ------------------------------ */ 3001 .balign 128 3002.L_op_sput_short: /* 0x6d */ 3003/* File: arm/op_sput_short.S */ 3004/* File: arm/op_sput.S */ 3005 /* 3006 * General SPUT handler wrapper. 3007 * 3008 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3009 */ 3010 /* op vAA, field@BBBB */ 3011 EXPORT_PC 3012 FETCH r0, 1 @ r0<- field ref BBBB 3013 mov r3, rINST, lsr #8 @ r3<- AA 3014 GET_VREG r1, r3 @ r1<= fp[AA] 3015 ldr r2, [rFP, #OFF_FP_METHOD] 3016 mov r3, rSELF 3017 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 3018 bl MterpSetShortStatic 3019 cmp r0, #0 @ 0 on success, -1 on failure 3020 bne MterpException 3021 ADVANCE 2 @ Past exception point - now advance rPC 3022 GET_INST_OPCODE ip @ extract opcode from rINST 3023 GOTO_OPCODE ip @ jump to next instruction 3024 3025 3026/* ------------------------------ */ 3027 .balign 128 3028.L_op_invoke_virtual: /* 0x6e */ 3029/* File: arm/op_invoke_virtual.S */ 3030/* File: arm/invoke.S */ 3031 /* 3032 * Generic invoke handler wrapper. 3033 */ 3034 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3035 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3036 .extern MterpInvokeVirtual 3037 EXPORT_PC 3038 mov r0, rSELF 3039 add r1, rFP, #OFF_FP_SHADOWFRAME 3040 mov r2, rPC 3041 mov r3, rINST 3042 bl MterpInvokeVirtual 3043 cmp r0, #0 3044 beq MterpException 3045 FETCH_ADVANCE_INST 3 3046 bl MterpShouldSwitchInterpreters 3047 cmp r0, #0 3048 bne MterpFallback 3049 GET_INST_OPCODE ip 3050 GOTO_OPCODE ip 3051 3052 3053 /* 3054 * Handle a virtual method call. 3055 * 3056 * for: invoke-virtual, invoke-virtual/range 3057 */ 3058 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3059 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3060 3061/* ------------------------------ */ 3062 .balign 128 3063.L_op_invoke_super: /* 0x6f */ 3064/* File: arm/op_invoke_super.S */ 3065/* File: arm/invoke.S */ 3066 /* 3067 * Generic invoke handler wrapper. 3068 */ 3069 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3070 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3071 .extern MterpInvokeSuper 3072 EXPORT_PC 3073 mov r0, rSELF 3074 add r1, rFP, #OFF_FP_SHADOWFRAME 3075 mov r2, rPC 3076 mov r3, rINST 3077 bl MterpInvokeSuper 3078 cmp r0, #0 3079 beq MterpException 3080 FETCH_ADVANCE_INST 3 3081 bl MterpShouldSwitchInterpreters 3082 cmp r0, #0 3083 bne MterpFallback 3084 GET_INST_OPCODE ip 3085 GOTO_OPCODE ip 3086 3087 3088 /* 3089 * Handle a "super" method call. 3090 * 3091 * for: invoke-super, invoke-super/range 3092 */ 3093 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3094 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3095 3096/* ------------------------------ */ 3097 .balign 128 3098.L_op_invoke_direct: /* 0x70 */ 3099/* File: arm/op_invoke_direct.S */ 3100/* File: arm/invoke.S */ 3101 /* 3102 * Generic invoke handler wrapper. 3103 */ 3104 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3105 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3106 .extern MterpInvokeDirect 3107 EXPORT_PC 3108 mov r0, rSELF 3109 add r1, rFP, #OFF_FP_SHADOWFRAME 3110 mov r2, rPC 3111 mov r3, rINST 3112 bl MterpInvokeDirect 3113 cmp r0, #0 3114 beq MterpException 3115 FETCH_ADVANCE_INST 3 3116 bl MterpShouldSwitchInterpreters 3117 cmp r0, #0 3118 bne MterpFallback 3119 GET_INST_OPCODE ip 3120 GOTO_OPCODE ip 3121 3122 3123 3124/* ------------------------------ */ 3125 .balign 128 3126.L_op_invoke_static: /* 0x71 */ 3127/* File: arm/op_invoke_static.S */ 3128/* File: arm/invoke.S */ 3129 /* 3130 * Generic invoke handler wrapper. 3131 */ 3132 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3133 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3134 .extern MterpInvokeStatic 3135 EXPORT_PC 3136 mov r0, rSELF 3137 add r1, rFP, #OFF_FP_SHADOWFRAME 3138 mov r2, rPC 3139 mov r3, rINST 3140 bl MterpInvokeStatic 3141 cmp r0, #0 3142 beq MterpException 3143 FETCH_ADVANCE_INST 3 3144 bl MterpShouldSwitchInterpreters 3145 cmp r0, #0 3146 bne MterpFallback 3147 GET_INST_OPCODE ip 3148 GOTO_OPCODE ip 3149 3150 3151 3152 3153/* ------------------------------ */ 3154 .balign 128 3155.L_op_invoke_interface: /* 0x72 */ 3156/* File: arm/op_invoke_interface.S */ 3157/* File: arm/invoke.S */ 3158 /* 3159 * Generic invoke handler wrapper. 3160 */ 3161 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3162 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3163 .extern MterpInvokeInterface 3164 EXPORT_PC 3165 mov r0, rSELF 3166 add r1, rFP, #OFF_FP_SHADOWFRAME 3167 mov r2, rPC 3168 mov r3, rINST 3169 bl MterpInvokeInterface 3170 cmp r0, #0 3171 beq MterpException 3172 FETCH_ADVANCE_INST 3 3173 bl MterpShouldSwitchInterpreters 3174 cmp r0, #0 3175 bne MterpFallback 3176 GET_INST_OPCODE ip 3177 GOTO_OPCODE ip 3178 3179 3180 /* 3181 * Handle an interface method call. 3182 * 3183 * for: invoke-interface, invoke-interface/range 3184 */ 3185 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3186 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3187 3188/* ------------------------------ */ 3189 .balign 128 3190.L_op_return_void_no_barrier: /* 0x73 */ 3191/* File: arm/op_return_void_no_barrier.S */ 3192 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 3193 mov r0, rSELF 3194 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 3195 blne MterpSuspendCheck @ (self) 3196 mov r0, #0 3197 mov r1, #0 3198 b MterpReturn 3199 3200/* ------------------------------ */ 3201 .balign 128 3202.L_op_invoke_virtual_range: /* 0x74 */ 3203/* File: arm/op_invoke_virtual_range.S */ 3204/* File: arm/invoke.S */ 3205 /* 3206 * Generic invoke handler wrapper. 3207 */ 3208 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3209 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3210 .extern MterpInvokeVirtualRange 3211 EXPORT_PC 3212 mov r0, rSELF 3213 add r1, rFP, #OFF_FP_SHADOWFRAME 3214 mov r2, rPC 3215 mov r3, rINST 3216 bl MterpInvokeVirtualRange 3217 cmp r0, #0 3218 beq MterpException 3219 FETCH_ADVANCE_INST 3 3220 bl MterpShouldSwitchInterpreters 3221 cmp r0, #0 3222 bne MterpFallback 3223 GET_INST_OPCODE ip 3224 GOTO_OPCODE ip 3225 3226 3227 3228/* ------------------------------ */ 3229 .balign 128 3230.L_op_invoke_super_range: /* 0x75 */ 3231/* File: arm/op_invoke_super_range.S */ 3232/* File: arm/invoke.S */ 3233 /* 3234 * Generic invoke handler wrapper. 3235 */ 3236 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3237 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3238 .extern MterpInvokeSuperRange 3239 EXPORT_PC 3240 mov r0, rSELF 3241 add r1, rFP, #OFF_FP_SHADOWFRAME 3242 mov r2, rPC 3243 mov r3, rINST 3244 bl MterpInvokeSuperRange 3245 cmp r0, #0 3246 beq MterpException 3247 FETCH_ADVANCE_INST 3 3248 bl MterpShouldSwitchInterpreters 3249 cmp r0, #0 3250 bne MterpFallback 3251 GET_INST_OPCODE ip 3252 GOTO_OPCODE ip 3253 3254 3255 3256/* ------------------------------ */ 3257 .balign 128 3258.L_op_invoke_direct_range: /* 0x76 */ 3259/* File: arm/op_invoke_direct_range.S */ 3260/* File: arm/invoke.S */ 3261 /* 3262 * Generic invoke handler wrapper. 3263 */ 3264 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3265 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3266 .extern MterpInvokeDirectRange 3267 EXPORT_PC 3268 mov r0, rSELF 3269 add r1, rFP, #OFF_FP_SHADOWFRAME 3270 mov r2, rPC 3271 mov r3, rINST 3272 bl MterpInvokeDirectRange 3273 cmp r0, #0 3274 beq MterpException 3275 FETCH_ADVANCE_INST 3 3276 bl MterpShouldSwitchInterpreters 3277 cmp r0, #0 3278 bne MterpFallback 3279 GET_INST_OPCODE ip 3280 GOTO_OPCODE ip 3281 3282 3283 3284/* ------------------------------ */ 3285 .balign 128 3286.L_op_invoke_static_range: /* 0x77 */ 3287/* File: arm/op_invoke_static_range.S */ 3288/* File: arm/invoke.S */ 3289 /* 3290 * Generic invoke handler wrapper. 3291 */ 3292 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3293 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3294 .extern MterpInvokeStaticRange 3295 EXPORT_PC 3296 mov r0, rSELF 3297 add r1, rFP, #OFF_FP_SHADOWFRAME 3298 mov r2, rPC 3299 mov r3, rINST 3300 bl MterpInvokeStaticRange 3301 cmp r0, #0 3302 beq MterpException 3303 FETCH_ADVANCE_INST 3 3304 bl MterpShouldSwitchInterpreters 3305 cmp r0, #0 3306 bne MterpFallback 3307 GET_INST_OPCODE ip 3308 GOTO_OPCODE ip 3309 3310 3311 3312/* ------------------------------ */ 3313 .balign 128 3314.L_op_invoke_interface_range: /* 0x78 */ 3315/* File: arm/op_invoke_interface_range.S */ 3316/* File: arm/invoke.S */ 3317 /* 3318 * Generic invoke handler wrapper. 3319 */ 3320 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3321 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3322 .extern MterpInvokeInterfaceRange 3323 EXPORT_PC 3324 mov r0, rSELF 3325 add r1, rFP, #OFF_FP_SHADOWFRAME 3326 mov r2, rPC 3327 mov r3, rINST 3328 bl MterpInvokeInterfaceRange 3329 cmp r0, #0 3330 beq MterpException 3331 FETCH_ADVANCE_INST 3 3332 bl MterpShouldSwitchInterpreters 3333 cmp r0, #0 3334 bne MterpFallback 3335 GET_INST_OPCODE ip 3336 GOTO_OPCODE ip 3337 3338 3339 3340/* ------------------------------ */ 3341 .balign 128 3342.L_op_unused_79: /* 0x79 */ 3343/* File: arm/op_unused_79.S */ 3344/* File: arm/unused.S */ 3345/* 3346 * Bail to reference interpreter to throw. 3347 */ 3348 b MterpFallback 3349 3350 3351/* ------------------------------ */ 3352 .balign 128 3353.L_op_unused_7a: /* 0x7a */ 3354/* File: arm/op_unused_7a.S */ 3355/* File: arm/unused.S */ 3356/* 3357 * Bail to reference interpreter to throw. 3358 */ 3359 b MterpFallback 3360 3361 3362/* ------------------------------ */ 3363 .balign 128 3364.L_op_neg_int: /* 0x7b */ 3365/* File: arm/op_neg_int.S */ 3366/* File: arm/unop.S */ 3367 /* 3368 * Generic 32-bit unary operation. Provide an "instr" line that 3369 * specifies an instruction that performs "result = op r0". 3370 * This could be an ARM instruction or a function call. 3371 * 3372 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3373 * int-to-byte, int-to-char, int-to-short 3374 */ 3375 /* unop vA, vB */ 3376 mov r3, rINST, lsr #12 @ r3<- B 3377 ubfx r9, rINST, #8, #4 @ r9<- A 3378 GET_VREG r0, r3 @ r0<- vB 3379 @ optional op; may set condition codes 3380 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3381 rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3382 GET_INST_OPCODE ip @ extract opcode from rINST 3383 SET_VREG r0, r9 @ vAA<- r0 3384 GOTO_OPCODE ip @ jump to next instruction 3385 /* 8-9 instructions */ 3386 3387 3388/* ------------------------------ */ 3389 .balign 128 3390.L_op_not_int: /* 0x7c */ 3391/* File: arm/op_not_int.S */ 3392/* File: arm/unop.S */ 3393 /* 3394 * Generic 32-bit unary operation. Provide an "instr" line that 3395 * specifies an instruction that performs "result = op r0". 3396 * This could be an ARM instruction or a function call. 3397 * 3398 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3399 * int-to-byte, int-to-char, int-to-short 3400 */ 3401 /* unop vA, vB */ 3402 mov r3, rINST, lsr #12 @ r3<- B 3403 ubfx r9, rINST, #8, #4 @ r9<- A 3404 GET_VREG r0, r3 @ r0<- vB 3405 @ optional op; may set condition codes 3406 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3407 mvn r0, r0 @ r0<- op, r0-r3 changed 3408 GET_INST_OPCODE ip @ extract opcode from rINST 3409 SET_VREG r0, r9 @ vAA<- r0 3410 GOTO_OPCODE ip @ jump to next instruction 3411 /* 8-9 instructions */ 3412 3413 3414/* ------------------------------ */ 3415 .balign 128 3416.L_op_neg_long: /* 0x7d */ 3417/* File: arm/op_neg_long.S */ 3418/* File: arm/unopWide.S */ 3419 /* 3420 * Generic 64-bit unary operation. Provide an "instr" line that 3421 * specifies an instruction that performs "result = op r0/r1". 3422 * This could be an ARM instruction or a function call. 3423 * 3424 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3425 */ 3426 /* unop vA, vB */ 3427 mov r3, rINST, lsr #12 @ r3<- B 3428 ubfx rINST, rINST, #8, #4 @ rINST<- A 3429 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3430 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3431 ldmia r3, {r0-r1} @ r0/r1<- vAA 3432 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3433 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3434 rsbs r0, r0, #0 @ optional op; may set condition codes 3435 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3436 GET_INST_OPCODE ip @ extract opcode from rINST 3437 stmia r9, {r0-r1} @ vAA<- r0/r1 3438 GOTO_OPCODE ip @ jump to next instruction 3439 /* 10-11 instructions */ 3440 3441 3442/* ------------------------------ */ 3443 .balign 128 3444.L_op_not_long: /* 0x7e */ 3445/* File: arm/op_not_long.S */ 3446/* File: arm/unopWide.S */ 3447 /* 3448 * Generic 64-bit unary operation. Provide an "instr" line that 3449 * specifies an instruction that performs "result = op r0/r1". 3450 * This could be an ARM instruction or a function call. 3451 * 3452 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3453 */ 3454 /* unop vA, vB */ 3455 mov r3, rINST, lsr #12 @ r3<- B 3456 ubfx rINST, rINST, #8, #4 @ rINST<- A 3457 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3458 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3459 ldmia r3, {r0-r1} @ r0/r1<- vAA 3460 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3461 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3462 mvn r0, r0 @ optional op; may set condition codes 3463 mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3464 GET_INST_OPCODE ip @ extract opcode from rINST 3465 stmia r9, {r0-r1} @ vAA<- r0/r1 3466 GOTO_OPCODE ip @ jump to next instruction 3467 /* 10-11 instructions */ 3468 3469 3470/* ------------------------------ */ 3471 .balign 128 3472.L_op_neg_float: /* 0x7f */ 3473/* File: arm/op_neg_float.S */ 3474/* File: arm/unop.S */ 3475 /* 3476 * Generic 32-bit unary operation. Provide an "instr" line that 3477 * specifies an instruction that performs "result = op r0". 3478 * This could be an ARM instruction or a function call. 3479 * 3480 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3481 * int-to-byte, int-to-char, int-to-short 3482 */ 3483 /* unop vA, vB */ 3484 mov r3, rINST, lsr #12 @ r3<- B 3485 ubfx r9, rINST, #8, #4 @ r9<- A 3486 GET_VREG r0, r3 @ r0<- vB 3487 @ optional op; may set condition codes 3488 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3489 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3490 GET_INST_OPCODE ip @ extract opcode from rINST 3491 SET_VREG r0, r9 @ vAA<- r0 3492 GOTO_OPCODE ip @ jump to next instruction 3493 /* 8-9 instructions */ 3494 3495 3496/* ------------------------------ */ 3497 .balign 128 3498.L_op_neg_double: /* 0x80 */ 3499/* File: arm/op_neg_double.S */ 3500/* File: arm/unopWide.S */ 3501 /* 3502 * Generic 64-bit unary operation. Provide an "instr" line that 3503 * specifies an instruction that performs "result = op r0/r1". 3504 * This could be an ARM instruction or a function call. 3505 * 3506 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3507 */ 3508 /* unop vA, vB */ 3509 mov r3, rINST, lsr #12 @ r3<- B 3510 ubfx rINST, rINST, #8, #4 @ rINST<- A 3511 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3512 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3513 ldmia r3, {r0-r1} @ r0/r1<- vAA 3514 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3515 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3516 @ optional op; may set condition codes 3517 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3518 GET_INST_OPCODE ip @ extract opcode from rINST 3519 stmia r9, {r0-r1} @ vAA<- r0/r1 3520 GOTO_OPCODE ip @ jump to next instruction 3521 /* 10-11 instructions */ 3522 3523 3524/* ------------------------------ */ 3525 .balign 128 3526.L_op_int_to_long: /* 0x81 */ 3527/* File: arm/op_int_to_long.S */ 3528/* File: arm/unopWider.S */ 3529 /* 3530 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3531 * that specifies an instruction that performs "result = op r0", where 3532 * "result" is a 64-bit quantity in r0/r1. 3533 * 3534 * For: int-to-long, int-to-double, float-to-long, float-to-double 3535 */ 3536 /* unop vA, vB */ 3537 mov r3, rINST, lsr #12 @ r3<- B 3538 ubfx rINST, rINST, #8, #4 @ rINST<- A 3539 GET_VREG r0, r3 @ r0<- vB 3540 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3541 @ optional op; may set condition codes 3542 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3543 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3544 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3545 GET_INST_OPCODE ip @ extract opcode from rINST 3546 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3547 GOTO_OPCODE ip @ jump to next instruction 3548 /* 9-10 instructions */ 3549 3550 3551/* ------------------------------ */ 3552 .balign 128 3553.L_op_int_to_float: /* 0x82 */ 3554/* File: arm/op_int_to_float.S */ 3555/* File: arm/funop.S */ 3556 /* 3557 * Generic 32-bit unary floating-point operation. Provide an "instr" 3558 * line that specifies an instruction that performs "s1 = op s0". 3559 * 3560 * for: int-to-float, float-to-int 3561 */ 3562 /* unop vA, vB */ 3563 mov r3, rINST, lsr #12 @ r3<- B 3564 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3565 flds s0, [r3] @ s0<- vB 3566 ubfx r9, rINST, #8, #4 @ r9<- A 3567 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3568 fsitos s1, s0 @ s1<- op 3569 GET_INST_OPCODE ip @ extract opcode from rINST 3570 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3571 fsts s1, [r9] @ vA<- s1 3572 GOTO_OPCODE ip @ jump to next instruction 3573 3574 3575/* ------------------------------ */ 3576 .balign 128 3577.L_op_int_to_double: /* 0x83 */ 3578/* File: arm/op_int_to_double.S */ 3579/* File: arm/funopWider.S */ 3580 /* 3581 * Generic 32bit-to-64bit floating point unary operation. Provide an 3582 * "instr" line that specifies an instruction that performs "d0 = op s0". 3583 * 3584 * For: int-to-double, float-to-double 3585 */ 3586 /* unop vA, vB */ 3587 mov r3, rINST, lsr #12 @ r3<- B 3588 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3589 flds s0, [r3] @ s0<- vB 3590 ubfx r9, rINST, #8, #4 @ r9<- A 3591 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3592 fsitod d0, s0 @ d0<- op 3593 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 3594 GET_INST_OPCODE ip @ extract opcode from rINST 3595 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3596 fstd d0, [r9] @ vA<- d0 3597 GOTO_OPCODE ip @ jump to next instruction 3598 3599 3600/* ------------------------------ */ 3601 .balign 128 3602.L_op_long_to_int: /* 0x84 */ 3603/* File: arm/op_long_to_int.S */ 3604/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3605/* File: arm/op_move.S */ 3606 /* for move, move-object, long-to-int */ 3607 /* op vA, vB */ 3608 mov r1, rINST, lsr #12 @ r1<- B from 15:12 3609 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 3610 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3611 GET_VREG r2, r1 @ r2<- fp[B] 3612 GET_INST_OPCODE ip @ ip<- opcode from rINST 3613 .if 0 3614 SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 3615 .else 3616 SET_VREG r2, r0 @ fp[A]<- r2 3617 .endif 3618 GOTO_OPCODE ip @ execute next instruction 3619 3620 3621/* ------------------------------ */ 3622 .balign 128 3623.L_op_long_to_float: /* 0x85 */ 3624/* File: arm/op_long_to_float.S */ 3625/* File: arm/unopNarrower.S */ 3626 /* 3627 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3628 * that specifies an instruction that performs "result = op r0/r1", where 3629 * "result" is a 32-bit quantity in r0. 3630 * 3631 * For: long-to-float, double-to-int, double-to-float 3632 * 3633 * (This would work for long-to-int, but that instruction is actually 3634 * an exact match for op_move.) 3635 */ 3636 /* unop vA, vB */ 3637 mov r3, rINST, lsr #12 @ r3<- B 3638 ubfx r9, rINST, #8, #4 @ r9<- A 3639 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3640 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3641 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3642 @ optional op; may set condition codes 3643 bl __aeabi_l2f @ r0<- op, r0-r3 changed 3644 GET_INST_OPCODE ip @ extract opcode from rINST 3645 SET_VREG r0, r9 @ vA<- r0 3646 GOTO_OPCODE ip @ jump to next instruction 3647 /* 9-10 instructions */ 3648 3649 3650/* ------------------------------ */ 3651 .balign 128 3652.L_op_long_to_double: /* 0x86 */ 3653/* File: arm/op_long_to_double.S */ 3654 /* 3655 * Specialised 64-bit floating point operation. 3656 * 3657 * Note: The result will be returned in d2. 3658 * 3659 * For: long-to-double 3660 */ 3661 mov r3, rINST, lsr #12 @ r3<- B 3662 ubfx r9, rINST, #8, #4 @ r9<- A 3663 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3664 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] 3665 vldr d0, [r3] @ d0<- vAA 3666 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3667 3668 vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh) 3669 vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl) 3670 vldr d3, constvalop_long_to_double 3671 vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl 3672 3673 GET_INST_OPCODE ip @ extract opcode from rINST 3674 vstr.64 d2, [r9] @ vAA<- d2 3675 GOTO_OPCODE ip @ jump to next instruction 3676 3677 /* literal pool helper */ 3678constvalop_long_to_double: 3679 .8byte 0x41f0000000000000 3680 3681/* ------------------------------ */ 3682 .balign 128 3683.L_op_float_to_int: /* 0x87 */ 3684/* File: arm/op_float_to_int.S */ 3685/* File: arm/funop.S */ 3686 /* 3687 * Generic 32-bit unary floating-point operation. Provide an "instr" 3688 * line that specifies an instruction that performs "s1 = op s0". 3689 * 3690 * for: int-to-float, float-to-int 3691 */ 3692 /* unop vA, vB */ 3693 mov r3, rINST, lsr #12 @ r3<- B 3694 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3695 flds s0, [r3] @ s0<- vB 3696 ubfx r9, rINST, #8, #4 @ r9<- A 3697 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3698 ftosizs s1, s0 @ s1<- op 3699 GET_INST_OPCODE ip @ extract opcode from rINST 3700 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3701 fsts s1, [r9] @ vA<- s1 3702 GOTO_OPCODE ip @ jump to next instruction 3703 3704 3705/* ------------------------------ */ 3706 .balign 128 3707.L_op_float_to_long: /* 0x88 */ 3708/* File: arm/op_float_to_long.S */ 3709/* File: arm/unopWider.S */ 3710 /* 3711 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3712 * that specifies an instruction that performs "result = op r0", where 3713 * "result" is a 64-bit quantity in r0/r1. 3714 * 3715 * For: int-to-long, int-to-double, float-to-long, float-to-double 3716 */ 3717 /* unop vA, vB */ 3718 mov r3, rINST, lsr #12 @ r3<- B 3719 ubfx rINST, rINST, #8, #4 @ rINST<- A 3720 GET_VREG r0, r3 @ r0<- vB 3721 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3722 @ optional op; may set condition codes 3723 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3724 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3725 bl f2l_doconv @ r0<- op, r0-r3 changed 3726 GET_INST_OPCODE ip @ extract opcode from rINST 3727 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3728 GOTO_OPCODE ip @ jump to next instruction 3729 /* 9-10 instructions */ 3730 3731 3732 3733/* ------------------------------ */ 3734 .balign 128 3735.L_op_float_to_double: /* 0x89 */ 3736/* File: arm/op_float_to_double.S */ 3737/* File: arm/funopWider.S */ 3738 /* 3739 * Generic 32bit-to-64bit floating point unary operation. Provide an 3740 * "instr" line that specifies an instruction that performs "d0 = op s0". 3741 * 3742 * For: int-to-double, float-to-double 3743 */ 3744 /* unop vA, vB */ 3745 mov r3, rINST, lsr #12 @ r3<- B 3746 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3747 flds s0, [r3] @ s0<- vB 3748 ubfx r9, rINST, #8, #4 @ r9<- A 3749 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3750 vcvt.f64.f32 d0, s0 @ d0<- op 3751 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 3752 GET_INST_OPCODE ip @ extract opcode from rINST 3753 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3754 fstd d0, [r9] @ vA<- d0 3755 GOTO_OPCODE ip @ jump to next instruction 3756 3757 3758/* ------------------------------ */ 3759 .balign 128 3760.L_op_double_to_int: /* 0x8a */ 3761/* File: arm/op_double_to_int.S */ 3762/* File: arm/funopNarrower.S */ 3763 /* 3764 * Generic 64bit-to-32bit unary floating point operation. Provide an 3765 * "instr" line that specifies an instruction that performs "s0 = op d0". 3766 * 3767 * For: double-to-int, double-to-float 3768 */ 3769 /* unop vA, vB */ 3770 mov r3, rINST, lsr #12 @ r3<- B 3771 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3772 fldd d0, [r3] @ d0<- vB 3773 ubfx r9, rINST, #8, #4 @ r9<- A 3774 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3775 ftosizd s0, d0 @ s0<- op 3776 GET_INST_OPCODE ip @ extract opcode from rINST 3777 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3778 fsts s0, [r9] @ vA<- s0 3779 GOTO_OPCODE ip @ jump to next instruction 3780 3781 3782/* ------------------------------ */ 3783 .balign 128 3784.L_op_double_to_long: /* 0x8b */ 3785/* File: arm/op_double_to_long.S */ 3786/* File: arm/unopWide.S */ 3787 /* 3788 * Generic 64-bit unary operation. Provide an "instr" line that 3789 * specifies an instruction that performs "result = op r0/r1". 3790 * This could be an ARM instruction or a function call. 3791 * 3792 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3793 */ 3794 /* unop vA, vB */ 3795 mov r3, rINST, lsr #12 @ r3<- B 3796 ubfx rINST, rINST, #8, #4 @ rINST<- A 3797 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3798 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3799 ldmia r3, {r0-r1} @ r0/r1<- vAA 3800 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3801 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3802 @ optional op; may set condition codes 3803 bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3804 GET_INST_OPCODE ip @ extract opcode from rINST 3805 stmia r9, {r0-r1} @ vAA<- r0/r1 3806 GOTO_OPCODE ip @ jump to next instruction 3807 /* 10-11 instructions */ 3808 3809 3810 3811/* ------------------------------ */ 3812 .balign 128 3813.L_op_double_to_float: /* 0x8c */ 3814/* File: arm/op_double_to_float.S */ 3815/* File: arm/funopNarrower.S */ 3816 /* 3817 * Generic 64bit-to-32bit unary floating point operation. Provide an 3818 * "instr" line that specifies an instruction that performs "s0 = op d0". 3819 * 3820 * For: double-to-int, double-to-float 3821 */ 3822 /* unop vA, vB */ 3823 mov r3, rINST, lsr #12 @ r3<- B 3824 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3825 fldd d0, [r3] @ d0<- vB 3826 ubfx r9, rINST, #8, #4 @ r9<- A 3827 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3828 vcvt.f32.f64 s0, d0 @ s0<- op 3829 GET_INST_OPCODE ip @ extract opcode from rINST 3830 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3831 fsts s0, [r9] @ vA<- s0 3832 GOTO_OPCODE ip @ jump to next instruction 3833 3834 3835/* ------------------------------ */ 3836 .balign 128 3837.L_op_int_to_byte: /* 0x8d */ 3838/* File: arm/op_int_to_byte.S */ 3839/* File: arm/unop.S */ 3840 /* 3841 * Generic 32-bit unary operation. Provide an "instr" line that 3842 * specifies an instruction that performs "result = op r0". 3843 * This could be an ARM instruction or a function call. 3844 * 3845 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3846 * int-to-byte, int-to-char, int-to-short 3847 */ 3848 /* unop vA, vB */ 3849 mov r3, rINST, lsr #12 @ r3<- B 3850 ubfx r9, rINST, #8, #4 @ r9<- A 3851 GET_VREG r0, r3 @ r0<- vB 3852 @ optional op; may set condition codes 3853 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3854 sxtb r0, r0 @ r0<- op, r0-r3 changed 3855 GET_INST_OPCODE ip @ extract opcode from rINST 3856 SET_VREG r0, r9 @ vAA<- r0 3857 GOTO_OPCODE ip @ jump to next instruction 3858 /* 8-9 instructions */ 3859 3860 3861/* ------------------------------ */ 3862 .balign 128 3863.L_op_int_to_char: /* 0x8e */ 3864/* File: arm/op_int_to_char.S */ 3865/* File: arm/unop.S */ 3866 /* 3867 * Generic 32-bit unary operation. Provide an "instr" line that 3868 * specifies an instruction that performs "result = op r0". 3869 * This could be an ARM instruction or a function call. 3870 * 3871 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3872 * int-to-byte, int-to-char, int-to-short 3873 */ 3874 /* unop vA, vB */ 3875 mov r3, rINST, lsr #12 @ r3<- B 3876 ubfx r9, rINST, #8, #4 @ r9<- A 3877 GET_VREG r0, r3 @ r0<- vB 3878 @ optional op; may set condition codes 3879 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3880 uxth r0, r0 @ r0<- op, r0-r3 changed 3881 GET_INST_OPCODE ip @ extract opcode from rINST 3882 SET_VREG r0, r9 @ vAA<- r0 3883 GOTO_OPCODE ip @ jump to next instruction 3884 /* 8-9 instructions */ 3885 3886 3887/* ------------------------------ */ 3888 .balign 128 3889.L_op_int_to_short: /* 0x8f */ 3890/* File: arm/op_int_to_short.S */ 3891/* File: arm/unop.S */ 3892 /* 3893 * Generic 32-bit unary operation. Provide an "instr" line that 3894 * specifies an instruction that performs "result = op r0". 3895 * This could be an ARM instruction or a function call. 3896 * 3897 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3898 * int-to-byte, int-to-char, int-to-short 3899 */ 3900 /* unop vA, vB */ 3901 mov r3, rINST, lsr #12 @ r3<- B 3902 ubfx r9, rINST, #8, #4 @ r9<- A 3903 GET_VREG r0, r3 @ r0<- vB 3904 @ optional op; may set condition codes 3905 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3906 sxth r0, r0 @ r0<- op, r0-r3 changed 3907 GET_INST_OPCODE ip @ extract opcode from rINST 3908 SET_VREG r0, r9 @ vAA<- r0 3909 GOTO_OPCODE ip @ jump to next instruction 3910 /* 8-9 instructions */ 3911 3912 3913/* ------------------------------ */ 3914 .balign 128 3915.L_op_add_int: /* 0x90 */ 3916/* File: arm/op_add_int.S */ 3917/* File: arm/binop.S */ 3918 /* 3919 * Generic 32-bit binary operation. Provide an "instr" line that 3920 * specifies an instruction that performs "result = r0 op r1". 3921 * This could be an ARM instruction or a function call. (If the result 3922 * comes back in a register other than r0, you can override "result".) 3923 * 3924 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3925 * vCC (r1). Useful for integer division and modulus. Note that we 3926 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3927 * handles it correctly. 3928 * 3929 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3930 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3931 * mul-float, div-float, rem-float 3932 */ 3933 /* binop vAA, vBB, vCC */ 3934 FETCH r0, 1 @ r0<- CCBB 3935 mov r9, rINST, lsr #8 @ r9<- AA 3936 mov r3, r0, lsr #8 @ r3<- CC 3937 and r2, r0, #255 @ r2<- BB 3938 GET_VREG r1, r3 @ r1<- vCC 3939 GET_VREG r0, r2 @ r0<- vBB 3940 .if 0 3941 cmp r1, #0 @ is second operand zero? 3942 beq common_errDivideByZero 3943 .endif 3944 3945 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 3946 @ optional op; may set condition codes 3947 add r0, r0, r1 @ r0<- op, r0-r3 changed 3948 GET_INST_OPCODE ip @ extract opcode from rINST 3949 SET_VREG r0, r9 @ vAA<- r0 3950 GOTO_OPCODE ip @ jump to next instruction 3951 /* 11-14 instructions */ 3952 3953 3954/* ------------------------------ */ 3955 .balign 128 3956.L_op_sub_int: /* 0x91 */ 3957/* File: arm/op_sub_int.S */ 3958/* File: arm/binop.S */ 3959 /* 3960 * Generic 32-bit binary operation. Provide an "instr" line that 3961 * specifies an instruction that performs "result = r0 op r1". 3962 * This could be an ARM instruction or a function call. (If the result 3963 * comes back in a register other than r0, you can override "result".) 3964 * 3965 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3966 * vCC (r1). Useful for integer division and modulus. Note that we 3967 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3968 * handles it correctly. 3969 * 3970 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3971 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3972 * mul-float, div-float, rem-float 3973 */ 3974 /* binop vAA, vBB, vCC */ 3975 FETCH r0, 1 @ r0<- CCBB 3976 mov r9, rINST, lsr #8 @ r9<- AA 3977 mov r3, r0, lsr #8 @ r3<- CC 3978 and r2, r0, #255 @ r2<- BB 3979 GET_VREG r1, r3 @ r1<- vCC 3980 GET_VREG r0, r2 @ r0<- vBB 3981 .if 0 3982 cmp r1, #0 @ is second operand zero? 3983 beq common_errDivideByZero 3984 .endif 3985 3986 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 3987 @ optional op; may set condition codes 3988 sub r0, r0, r1 @ r0<- op, r0-r3 changed 3989 GET_INST_OPCODE ip @ extract opcode from rINST 3990 SET_VREG r0, r9 @ vAA<- r0 3991 GOTO_OPCODE ip @ jump to next instruction 3992 /* 11-14 instructions */ 3993 3994 3995/* ------------------------------ */ 3996 .balign 128 3997.L_op_mul_int: /* 0x92 */ 3998/* File: arm/op_mul_int.S */ 3999/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4000/* File: arm/binop.S */ 4001 /* 4002 * Generic 32-bit binary operation. Provide an "instr" line that 4003 * specifies an instruction that performs "result = r0 op r1". 4004 * This could be an ARM instruction or a function call. (If the result 4005 * comes back in a register other than r0, you can override "result".) 4006 * 4007 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4008 * vCC (r1). Useful for integer division and modulus. Note that we 4009 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4010 * handles it correctly. 4011 * 4012 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4013 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4014 * mul-float, div-float, rem-float 4015 */ 4016 /* binop vAA, vBB, vCC */ 4017 FETCH r0, 1 @ r0<- CCBB 4018 mov r9, rINST, lsr #8 @ r9<- AA 4019 mov r3, r0, lsr #8 @ r3<- CC 4020 and r2, r0, #255 @ r2<- BB 4021 GET_VREG r1, r3 @ r1<- vCC 4022 GET_VREG r0, r2 @ r0<- vBB 4023 .if 0 4024 cmp r1, #0 @ is second operand zero? 4025 beq common_errDivideByZero 4026 .endif 4027 4028 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4029 @ optional op; may set condition codes 4030 mul r0, r1, r0 @ r0<- op, r0-r3 changed 4031 GET_INST_OPCODE ip @ extract opcode from rINST 4032 SET_VREG r0, r9 @ vAA<- r0 4033 GOTO_OPCODE ip @ jump to next instruction 4034 /* 11-14 instructions */ 4035 4036 4037/* ------------------------------ */ 4038 .balign 128 4039.L_op_div_int: /* 0x93 */ 4040/* File: arm/op_div_int.S */ 4041 /* 4042 * Specialized 32-bit binary operation 4043 * 4044 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper 4045 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 4046 * ARMv7 CPUs that have hardware division support). 4047 * 4048 * div-int 4049 * 4050 */ 4051 FETCH r0, 1 @ r0<- CCBB 4052 mov r9, rINST, lsr #8 @ r9<- AA 4053 mov r3, r0, lsr #8 @ r3<- CC 4054 and r2, r0, #255 @ r2<- BB 4055 GET_VREG r1, r3 @ r1<- vCC 4056 GET_VREG r0, r2 @ r0<- vBB 4057 cmp r1, #0 @ is second operand zero? 4058 beq common_errDivideByZero 4059 4060 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4061#ifdef __ARM_ARCH_EXT_IDIV__ 4062 sdiv r0, r0, r1 @ r0<- op 4063#else 4064 bl __aeabi_idiv @ r0<- op, r0-r3 changed 4065#endif 4066 GET_INST_OPCODE ip @ extract opcode from rINST 4067 SET_VREG r0, r9 @ vAA<- r0 4068 GOTO_OPCODE ip @ jump to next instruction 4069 /* 11-14 instructions */ 4070 4071/* ------------------------------ */ 4072 .balign 128 4073.L_op_rem_int: /* 0x94 */ 4074/* File: arm/op_rem_int.S */ 4075 /* 4076 * Specialized 32-bit binary operation 4077 * 4078 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 4079 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 4080 * ARMv7 CPUs that have hardware division support). 4081 * 4082 * NOTE: idivmod returns quotient in r0 and remainder in r1 4083 * 4084 * rem-int 4085 * 4086 */ 4087 FETCH r0, 1 @ r0<- CCBB 4088 mov r9, rINST, lsr #8 @ r9<- AA 4089 mov r3, r0, lsr #8 @ r3<- CC 4090 and r2, r0, #255 @ r2<- BB 4091 GET_VREG r1, r3 @ r1<- vCC 4092 GET_VREG r0, r2 @ r0<- vBB 4093 cmp r1, #0 @ is second operand zero? 4094 beq common_errDivideByZero 4095 4096 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4097#ifdef __ARM_ARCH_EXT_IDIV__ 4098 sdiv r2, r0, r1 4099 mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed 4100#else 4101 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4102#endif 4103 GET_INST_OPCODE ip @ extract opcode from rINST 4104 SET_VREG r1, r9 @ vAA<- r1 4105 GOTO_OPCODE ip @ jump to next instruction 4106 /* 11-14 instructions */ 4107 4108/* ------------------------------ */ 4109 .balign 128 4110.L_op_and_int: /* 0x95 */ 4111/* File: arm/op_and_int.S */ 4112/* File: arm/binop.S */ 4113 /* 4114 * Generic 32-bit binary operation. Provide an "instr" line that 4115 * specifies an instruction that performs "result = r0 op r1". 4116 * This could be an ARM instruction or a function call. (If the result 4117 * comes back in a register other than r0, you can override "result".) 4118 * 4119 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4120 * vCC (r1). Useful for integer division and modulus. Note that we 4121 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4122 * handles it correctly. 4123 * 4124 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4125 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4126 * mul-float, div-float, rem-float 4127 */ 4128 /* binop vAA, vBB, vCC */ 4129 FETCH r0, 1 @ r0<- CCBB 4130 mov r9, rINST, lsr #8 @ r9<- AA 4131 mov r3, r0, lsr #8 @ r3<- CC 4132 and r2, r0, #255 @ r2<- BB 4133 GET_VREG r1, r3 @ r1<- vCC 4134 GET_VREG r0, r2 @ r0<- vBB 4135 .if 0 4136 cmp r1, #0 @ is second operand zero? 4137 beq common_errDivideByZero 4138 .endif 4139 4140 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4141 @ optional op; may set condition codes 4142 and r0, r0, r1 @ r0<- op, r0-r3 changed 4143 GET_INST_OPCODE ip @ extract opcode from rINST 4144 SET_VREG r0, r9 @ vAA<- r0 4145 GOTO_OPCODE ip @ jump to next instruction 4146 /* 11-14 instructions */ 4147 4148 4149/* ------------------------------ */ 4150 .balign 128 4151.L_op_or_int: /* 0x96 */ 4152/* File: arm/op_or_int.S */ 4153/* File: arm/binop.S */ 4154 /* 4155 * Generic 32-bit binary operation. Provide an "instr" line that 4156 * specifies an instruction that performs "result = r0 op r1". 4157 * This could be an ARM instruction or a function call. (If the result 4158 * comes back in a register other than r0, you can override "result".) 4159 * 4160 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4161 * vCC (r1). Useful for integer division and modulus. Note that we 4162 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4163 * handles it correctly. 4164 * 4165 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4166 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4167 * mul-float, div-float, rem-float 4168 */ 4169 /* binop vAA, vBB, vCC */ 4170 FETCH r0, 1 @ r0<- CCBB 4171 mov r9, rINST, lsr #8 @ r9<- AA 4172 mov r3, r0, lsr #8 @ r3<- CC 4173 and r2, r0, #255 @ r2<- BB 4174 GET_VREG r1, r3 @ r1<- vCC 4175 GET_VREG r0, r2 @ r0<- vBB 4176 .if 0 4177 cmp r1, #0 @ is second operand zero? 4178 beq common_errDivideByZero 4179 .endif 4180 4181 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4182 @ optional op; may set condition codes 4183 orr r0, r0, r1 @ r0<- op, r0-r3 changed 4184 GET_INST_OPCODE ip @ extract opcode from rINST 4185 SET_VREG r0, r9 @ vAA<- r0 4186 GOTO_OPCODE ip @ jump to next instruction 4187 /* 11-14 instructions */ 4188 4189 4190/* ------------------------------ */ 4191 .balign 128 4192.L_op_xor_int: /* 0x97 */ 4193/* File: arm/op_xor_int.S */ 4194/* File: arm/binop.S */ 4195 /* 4196 * Generic 32-bit binary operation. Provide an "instr" line that 4197 * specifies an instruction that performs "result = r0 op r1". 4198 * This could be an ARM instruction or a function call. (If the result 4199 * comes back in a register other than r0, you can override "result".) 4200 * 4201 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4202 * vCC (r1). Useful for integer division and modulus. Note that we 4203 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4204 * handles it correctly. 4205 * 4206 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4207 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4208 * mul-float, div-float, rem-float 4209 */ 4210 /* binop vAA, vBB, vCC */ 4211 FETCH r0, 1 @ r0<- CCBB 4212 mov r9, rINST, lsr #8 @ r9<- AA 4213 mov r3, r0, lsr #8 @ r3<- CC 4214 and r2, r0, #255 @ r2<- BB 4215 GET_VREG r1, r3 @ r1<- vCC 4216 GET_VREG r0, r2 @ r0<- vBB 4217 .if 0 4218 cmp r1, #0 @ is second operand zero? 4219 beq common_errDivideByZero 4220 .endif 4221 4222 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4223 @ optional op; may set condition codes 4224 eor r0, r0, r1 @ r0<- op, r0-r3 changed 4225 GET_INST_OPCODE ip @ extract opcode from rINST 4226 SET_VREG r0, r9 @ vAA<- r0 4227 GOTO_OPCODE ip @ jump to next instruction 4228 /* 11-14 instructions */ 4229 4230 4231/* ------------------------------ */ 4232 .balign 128 4233.L_op_shl_int: /* 0x98 */ 4234/* File: arm/op_shl_int.S */ 4235/* File: arm/binop.S */ 4236 /* 4237 * Generic 32-bit binary operation. Provide an "instr" line that 4238 * specifies an instruction that performs "result = r0 op r1". 4239 * This could be an ARM instruction or a function call. (If the result 4240 * comes back in a register other than r0, you can override "result".) 4241 * 4242 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4243 * vCC (r1). Useful for integer division and modulus. Note that we 4244 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4245 * handles it correctly. 4246 * 4247 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4248 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4249 * mul-float, div-float, rem-float 4250 */ 4251 /* binop vAA, vBB, vCC */ 4252 FETCH r0, 1 @ r0<- CCBB 4253 mov r9, rINST, lsr #8 @ r9<- AA 4254 mov r3, r0, lsr #8 @ r3<- CC 4255 and r2, r0, #255 @ r2<- BB 4256 GET_VREG r1, r3 @ r1<- vCC 4257 GET_VREG r0, r2 @ r0<- vBB 4258 .if 0 4259 cmp r1, #0 @ is second operand zero? 4260 beq common_errDivideByZero 4261 .endif 4262 4263 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4264 and r1, r1, #31 @ optional op; may set condition codes 4265 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4266 GET_INST_OPCODE ip @ extract opcode from rINST 4267 SET_VREG r0, r9 @ vAA<- r0 4268 GOTO_OPCODE ip @ jump to next instruction 4269 /* 11-14 instructions */ 4270 4271 4272/* ------------------------------ */ 4273 .balign 128 4274.L_op_shr_int: /* 0x99 */ 4275/* File: arm/op_shr_int.S */ 4276/* File: arm/binop.S */ 4277 /* 4278 * Generic 32-bit binary operation. Provide an "instr" line that 4279 * specifies an instruction that performs "result = r0 op r1". 4280 * This could be an ARM instruction or a function call. (If the result 4281 * comes back in a register other than r0, you can override "result".) 4282 * 4283 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4284 * vCC (r1). Useful for integer division and modulus. Note that we 4285 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4286 * handles it correctly. 4287 * 4288 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4289 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4290 * mul-float, div-float, rem-float 4291 */ 4292 /* binop vAA, vBB, vCC */ 4293 FETCH r0, 1 @ r0<- CCBB 4294 mov r9, rINST, lsr #8 @ r9<- AA 4295 mov r3, r0, lsr #8 @ r3<- CC 4296 and r2, r0, #255 @ r2<- BB 4297 GET_VREG r1, r3 @ r1<- vCC 4298 GET_VREG r0, r2 @ r0<- vBB 4299 .if 0 4300 cmp r1, #0 @ is second operand zero? 4301 beq common_errDivideByZero 4302 .endif 4303 4304 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4305 and r1, r1, #31 @ optional op; may set condition codes 4306 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4307 GET_INST_OPCODE ip @ extract opcode from rINST 4308 SET_VREG r0, r9 @ vAA<- r0 4309 GOTO_OPCODE ip @ jump to next instruction 4310 /* 11-14 instructions */ 4311 4312 4313/* ------------------------------ */ 4314 .balign 128 4315.L_op_ushr_int: /* 0x9a */ 4316/* File: arm/op_ushr_int.S */ 4317/* File: arm/binop.S */ 4318 /* 4319 * Generic 32-bit binary operation. Provide an "instr" line that 4320 * specifies an instruction that performs "result = r0 op r1". 4321 * This could be an ARM instruction or a function call. (If the result 4322 * comes back in a register other than r0, you can override "result".) 4323 * 4324 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4325 * vCC (r1). Useful for integer division and modulus. Note that we 4326 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4327 * handles it correctly. 4328 * 4329 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4330 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4331 * mul-float, div-float, rem-float 4332 */ 4333 /* binop vAA, vBB, vCC */ 4334 FETCH r0, 1 @ r0<- CCBB 4335 mov r9, rINST, lsr #8 @ r9<- AA 4336 mov r3, r0, lsr #8 @ r3<- CC 4337 and r2, r0, #255 @ r2<- BB 4338 GET_VREG r1, r3 @ r1<- vCC 4339 GET_VREG r0, r2 @ r0<- vBB 4340 .if 0 4341 cmp r1, #0 @ is second operand zero? 4342 beq common_errDivideByZero 4343 .endif 4344 4345 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4346 and r1, r1, #31 @ optional op; may set condition codes 4347 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4348 GET_INST_OPCODE ip @ extract opcode from rINST 4349 SET_VREG r0, r9 @ vAA<- r0 4350 GOTO_OPCODE ip @ jump to next instruction 4351 /* 11-14 instructions */ 4352 4353 4354/* ------------------------------ */ 4355 .balign 128 4356.L_op_add_long: /* 0x9b */ 4357/* File: arm/op_add_long.S */ 4358/* File: arm/binopWide.S */ 4359 /* 4360 * Generic 64-bit binary operation. Provide an "instr" line that 4361 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4362 * This could be an ARM instruction or a function call. (If the result 4363 * comes back in a register other than r0, you can override "result".) 4364 * 4365 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4366 * vCC (r1). Useful for integer division and modulus. 4367 * 4368 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4369 * xor-long, add-double, sub-double, mul-double, div-double, 4370 * rem-double 4371 * 4372 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4373 */ 4374 /* binop vAA, vBB, vCC */ 4375 FETCH r0, 1 @ r0<- CCBB 4376 mov rINST, rINST, lsr #8 @ rINST<- AA 4377 and r2, r0, #255 @ r2<- BB 4378 mov r3, r0, lsr #8 @ r3<- CC 4379 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4380 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4381 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4382 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4383 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4384 .if 0 4385 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4386 beq common_errDivideByZero 4387 .endif 4388 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4389 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4390 adds r0, r0, r2 @ optional op; may set condition codes 4391 adc r1, r1, r3 @ result<- op, r0-r3 changed 4392 GET_INST_OPCODE ip @ extract opcode from rINST 4393 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4394 GOTO_OPCODE ip @ jump to next instruction 4395 /* 14-17 instructions */ 4396 4397 4398/* ------------------------------ */ 4399 .balign 128 4400.L_op_sub_long: /* 0x9c */ 4401/* File: arm/op_sub_long.S */ 4402/* File: arm/binopWide.S */ 4403 /* 4404 * Generic 64-bit binary operation. Provide an "instr" line that 4405 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4406 * This could be an ARM instruction or a function call. (If the result 4407 * comes back in a register other than r0, you can override "result".) 4408 * 4409 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4410 * vCC (r1). Useful for integer division and modulus. 4411 * 4412 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4413 * xor-long, add-double, sub-double, mul-double, div-double, 4414 * rem-double 4415 * 4416 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4417 */ 4418 /* binop vAA, vBB, vCC */ 4419 FETCH r0, 1 @ r0<- CCBB 4420 mov rINST, rINST, lsr #8 @ rINST<- AA 4421 and r2, r0, #255 @ r2<- BB 4422 mov r3, r0, lsr #8 @ r3<- CC 4423 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4424 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4425 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4426 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4427 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4428 .if 0 4429 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4430 beq common_errDivideByZero 4431 .endif 4432 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4433 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4434 subs r0, r0, r2 @ optional op; may set condition codes 4435 sbc r1, r1, r3 @ result<- op, r0-r3 changed 4436 GET_INST_OPCODE ip @ extract opcode from rINST 4437 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4438 GOTO_OPCODE ip @ jump to next instruction 4439 /* 14-17 instructions */ 4440 4441 4442/* ------------------------------ */ 4443 .balign 128 4444.L_op_mul_long: /* 0x9d */ 4445/* File: arm/op_mul_long.S */ 4446 /* 4447 * Signed 64-bit integer multiply. 4448 * 4449 * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4450 * WX 4451 * x YZ 4452 * -------- 4453 * ZW ZX 4454 * YW YX 4455 * 4456 * The low word of the result holds ZX, the high word holds 4457 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4458 * it doesn't fit in the low 64 bits. 4459 * 4460 * Unlike most ARM math operations, multiply instructions have 4461 * restrictions on using the same register more than once (Rd and Rm 4462 * cannot be the same). 4463 */ 4464 /* mul-long vAA, vBB, vCC */ 4465 FETCH r0, 1 @ r0<- CCBB 4466 and r2, r0, #255 @ r2<- BB 4467 mov r3, r0, lsr #8 @ r3<- CC 4468 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4469 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4470 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4471 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4472 mul ip, r2, r1 @ ip<- ZxW 4473 umull r1, lr, r2, r0 @ r1/lr <- ZxX 4474 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4475 mov r0, rINST, lsr #8 @ r0<- AA 4476 add r2, r2, lr @ r2<- lr + low(ZxW + (YxX)) 4477 VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[AA] 4478 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4479 GET_INST_OPCODE ip @ extract opcode from rINST 4480 stmia r0, {r1-r2 } @ vAA/vAA+1<- r1/r2 4481 GOTO_OPCODE ip @ jump to next instruction 4482 4483/* ------------------------------ */ 4484 .balign 128 4485.L_op_div_long: /* 0x9e */ 4486/* File: arm/op_div_long.S */ 4487/* File: arm/binopWide.S */ 4488 /* 4489 * Generic 64-bit binary operation. Provide an "instr" line that 4490 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4491 * This could be an ARM instruction or a function call. (If the result 4492 * comes back in a register other than r0, you can override "result".) 4493 * 4494 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4495 * vCC (r1). Useful for integer division and modulus. 4496 * 4497 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4498 * xor-long, add-double, sub-double, mul-double, div-double, 4499 * rem-double 4500 * 4501 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4502 */ 4503 /* binop vAA, vBB, vCC */ 4504 FETCH r0, 1 @ r0<- CCBB 4505 mov rINST, rINST, lsr #8 @ rINST<- AA 4506 and r2, r0, #255 @ r2<- BB 4507 mov r3, r0, lsr #8 @ r3<- CC 4508 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4509 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4510 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4511 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4512 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4513 .if 1 4514 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4515 beq common_errDivideByZero 4516 .endif 4517 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4518 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4519 @ optional op; may set condition codes 4520 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4521 GET_INST_OPCODE ip @ extract opcode from rINST 4522 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4523 GOTO_OPCODE ip @ jump to next instruction 4524 /* 14-17 instructions */ 4525 4526 4527/* ------------------------------ */ 4528 .balign 128 4529.L_op_rem_long: /* 0x9f */ 4530/* File: arm/op_rem_long.S */ 4531/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4532/* File: arm/binopWide.S */ 4533 /* 4534 * Generic 64-bit binary operation. Provide an "instr" line that 4535 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4536 * This could be an ARM instruction or a function call. (If the result 4537 * comes back in a register other than r0, you can override "result".) 4538 * 4539 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4540 * vCC (r1). Useful for integer division and modulus. 4541 * 4542 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4543 * xor-long, add-double, sub-double, mul-double, div-double, 4544 * rem-double 4545 * 4546 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4547 */ 4548 /* binop vAA, vBB, vCC */ 4549 FETCH r0, 1 @ r0<- CCBB 4550 mov rINST, rINST, lsr #8 @ rINST<- AA 4551 and r2, r0, #255 @ r2<- BB 4552 mov r3, r0, lsr #8 @ r3<- CC 4553 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4554 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4555 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4556 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4557 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4558 .if 1 4559 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4560 beq common_errDivideByZero 4561 .endif 4562 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4563 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4564 @ optional op; may set condition codes 4565 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4566 GET_INST_OPCODE ip @ extract opcode from rINST 4567 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4568 GOTO_OPCODE ip @ jump to next instruction 4569 /* 14-17 instructions */ 4570 4571 4572/* ------------------------------ */ 4573 .balign 128 4574.L_op_and_long: /* 0xa0 */ 4575/* File: arm/op_and_long.S */ 4576/* File: arm/binopWide.S */ 4577 /* 4578 * Generic 64-bit binary operation. Provide an "instr" line that 4579 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4580 * This could be an ARM instruction or a function call. (If the result 4581 * comes back in a register other than r0, you can override "result".) 4582 * 4583 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4584 * vCC (r1). Useful for integer division and modulus. 4585 * 4586 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4587 * xor-long, add-double, sub-double, mul-double, div-double, 4588 * rem-double 4589 * 4590 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4591 */ 4592 /* binop vAA, vBB, vCC */ 4593 FETCH r0, 1 @ r0<- CCBB 4594 mov rINST, rINST, lsr #8 @ rINST<- AA 4595 and r2, r0, #255 @ r2<- BB 4596 mov r3, r0, lsr #8 @ r3<- CC 4597 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4598 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4599 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4600 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4601 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4602 .if 0 4603 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4604 beq common_errDivideByZero 4605 .endif 4606 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4607 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4608 and r0, r0, r2 @ optional op; may set condition codes 4609 and r1, r1, r3 @ result<- op, r0-r3 changed 4610 GET_INST_OPCODE ip @ extract opcode from rINST 4611 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4612 GOTO_OPCODE ip @ jump to next instruction 4613 /* 14-17 instructions */ 4614 4615 4616/* ------------------------------ */ 4617 .balign 128 4618.L_op_or_long: /* 0xa1 */ 4619/* File: arm/op_or_long.S */ 4620/* File: arm/binopWide.S */ 4621 /* 4622 * Generic 64-bit binary operation. Provide an "instr" line that 4623 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4624 * This could be an ARM instruction or a function call. (If the result 4625 * comes back in a register other than r0, you can override "result".) 4626 * 4627 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4628 * vCC (r1). Useful for integer division and modulus. 4629 * 4630 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4631 * xor-long, add-double, sub-double, mul-double, div-double, 4632 * rem-double 4633 * 4634 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4635 */ 4636 /* binop vAA, vBB, vCC */ 4637 FETCH r0, 1 @ r0<- CCBB 4638 mov rINST, rINST, lsr #8 @ rINST<- AA 4639 and r2, r0, #255 @ r2<- BB 4640 mov r3, r0, lsr #8 @ r3<- CC 4641 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4642 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4643 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4644 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4645 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4646 .if 0 4647 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4648 beq common_errDivideByZero 4649 .endif 4650 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4651 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4652 orr r0, r0, r2 @ optional op; may set condition codes 4653 orr r1, r1, r3 @ result<- op, r0-r3 changed 4654 GET_INST_OPCODE ip @ extract opcode from rINST 4655 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4656 GOTO_OPCODE ip @ jump to next instruction 4657 /* 14-17 instructions */ 4658 4659 4660/* ------------------------------ */ 4661 .balign 128 4662.L_op_xor_long: /* 0xa2 */ 4663/* File: arm/op_xor_long.S */ 4664/* File: arm/binopWide.S */ 4665 /* 4666 * Generic 64-bit binary operation. Provide an "instr" line that 4667 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4668 * This could be an ARM instruction or a function call. (If the result 4669 * comes back in a register other than r0, you can override "result".) 4670 * 4671 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4672 * vCC (r1). Useful for integer division and modulus. 4673 * 4674 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4675 * xor-long, add-double, sub-double, mul-double, div-double, 4676 * rem-double 4677 * 4678 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4679 */ 4680 /* binop vAA, vBB, vCC */ 4681 FETCH r0, 1 @ r0<- CCBB 4682 mov rINST, rINST, lsr #8 @ rINST<- AA 4683 and r2, r0, #255 @ r2<- BB 4684 mov r3, r0, lsr #8 @ r3<- CC 4685 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4686 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4687 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4688 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4689 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4690 .if 0 4691 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4692 beq common_errDivideByZero 4693 .endif 4694 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4695 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4696 eor r0, r0, r2 @ optional op; may set condition codes 4697 eor r1, r1, r3 @ result<- op, r0-r3 changed 4698 GET_INST_OPCODE ip @ extract opcode from rINST 4699 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4700 GOTO_OPCODE ip @ jump to next instruction 4701 /* 14-17 instructions */ 4702 4703 4704/* ------------------------------ */ 4705 .balign 128 4706.L_op_shl_long: /* 0xa3 */ 4707/* File: arm/op_shl_long.S */ 4708 /* 4709 * Long integer shift. This is different from the generic 32/64-bit 4710 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4711 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4712 * 6 bits of the shift distance. 4713 */ 4714 /* shl-long vAA, vBB, vCC */ 4715 FETCH r0, 1 @ r0<- CCBB 4716 mov r9, rINST, lsr #8 @ r9<- AA 4717 and r3, r0, #255 @ r3<- BB 4718 mov r0, r0, lsr #8 @ r0<- CC 4719 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] 4720 GET_VREG r2, r0 @ r2<- vCC 4721 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4722 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 4723 and r2, r2, #63 @ r2<- r2 & 0x3f 4724 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 4725 mov r1, r1, asl r2 @ r1<- r1 << r2 4726 rsb r3, r2, #32 @ r3<- 32 - r2 4727 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4728 subs ip, r2, #32 @ ip<- r2 - 32 4729 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4730 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4731 mov r0, r0, asl r2 @ r0<- r0 << r2 4732 GET_INST_OPCODE ip @ extract opcode from rINST 4733 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 4734 GOTO_OPCODE ip @ jump to next instruction 4735 4736/* ------------------------------ */ 4737 .balign 128 4738.L_op_shr_long: /* 0xa4 */ 4739/* File: arm/op_shr_long.S */ 4740 /* 4741 * Long integer shift. This is different from the generic 32/64-bit 4742 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4743 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4744 * 6 bits of the shift distance. 4745 */ 4746 /* shr-long vAA, vBB, vCC */ 4747 FETCH r0, 1 @ r0<- CCBB 4748 mov r9, rINST, lsr #8 @ r9<- AA 4749 and r3, r0, #255 @ r3<- BB 4750 mov r0, r0, lsr #8 @ r0<- CC 4751 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] 4752 GET_VREG r2, r0 @ r2<- vCC 4753 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4754 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 4755 and r2, r2, #63 @ r0<- r0 & 0x3f 4756 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 4757 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4758 rsb r3, r2, #32 @ r3<- 32 - r2 4759 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4760 subs ip, r2, #32 @ ip<- r2 - 32 4761 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4762 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4763 mov r1, r1, asr r2 @ r1<- r1 >> r2 4764 GET_INST_OPCODE ip @ extract opcode from rINST 4765 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 4766 GOTO_OPCODE ip @ jump to next instruction 4767 4768/* ------------------------------ */ 4769 .balign 128 4770.L_op_ushr_long: /* 0xa5 */ 4771/* File: arm/op_ushr_long.S */ 4772 /* 4773 * Long integer shift. This is different from the generic 32/64-bit 4774 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4775 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4776 * 6 bits of the shift distance. 4777 */ 4778 /* ushr-long vAA, vBB, vCC */ 4779 FETCH r0, 1 @ r0<- CCBB 4780 mov r9, rINST, lsr #8 @ r9<- AA 4781 and r3, r0, #255 @ r3<- BB 4782 mov r0, r0, lsr #8 @ r0<- CC 4783 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] 4784 GET_VREG r2, r0 @ r2<- vCC 4785 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4786 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 4787 and r2, r2, #63 @ r0<- r0 & 0x3f 4788 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 4789 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4790 rsb r3, r2, #32 @ r3<- 32 - r2 4791 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4792 subs ip, r2, #32 @ ip<- r2 - 32 4793 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4794 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4795 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 4796 GET_INST_OPCODE ip @ extract opcode from rINST 4797 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 4798 GOTO_OPCODE ip @ jump to next instruction 4799 4800/* ------------------------------ */ 4801 .balign 128 4802.L_op_add_float: /* 0xa6 */ 4803/* File: arm/op_add_float.S */ 4804/* File: arm/fbinop.S */ 4805 /* 4806 * Generic 32-bit floating-point operation. Provide an "instr" line that 4807 * specifies an instruction that performs "s2 = s0 op s1". Because we 4808 * use the "softfp" ABI, this must be an instruction, not a function call. 4809 * 4810 * For: add-float, sub-float, mul-float, div-float 4811 */ 4812 /* floatop vAA, vBB, vCC */ 4813 FETCH r0, 1 @ r0<- CCBB 4814 mov r9, rINST, lsr #8 @ r9<- AA 4815 mov r3, r0, lsr #8 @ r3<- CC 4816 and r2, r0, #255 @ r2<- BB 4817 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4818 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4819 flds s1, [r3] @ s1<- vCC 4820 flds s0, [r2] @ s0<- vBB 4821 4822 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4823 fadds s2, s0, s1 @ s2<- op 4824 GET_INST_OPCODE ip @ extract opcode from rINST 4825 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 4826 fsts s2, [r9] @ vAA<- s2 4827 GOTO_OPCODE ip @ jump to next instruction 4828 4829 4830/* ------------------------------ */ 4831 .balign 128 4832.L_op_sub_float: /* 0xa7 */ 4833/* File: arm/op_sub_float.S */ 4834/* File: arm/fbinop.S */ 4835 /* 4836 * Generic 32-bit floating-point operation. Provide an "instr" line that 4837 * specifies an instruction that performs "s2 = s0 op s1". Because we 4838 * use the "softfp" ABI, this must be an instruction, not a function call. 4839 * 4840 * For: add-float, sub-float, mul-float, div-float 4841 */ 4842 /* floatop vAA, vBB, vCC */ 4843 FETCH r0, 1 @ r0<- CCBB 4844 mov r9, rINST, lsr #8 @ r9<- AA 4845 mov r3, r0, lsr #8 @ r3<- CC 4846 and r2, r0, #255 @ r2<- BB 4847 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4848 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4849 flds s1, [r3] @ s1<- vCC 4850 flds s0, [r2] @ s0<- vBB 4851 4852 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4853 fsubs s2, s0, s1 @ s2<- op 4854 GET_INST_OPCODE ip @ extract opcode from rINST 4855 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 4856 fsts s2, [r9] @ vAA<- s2 4857 GOTO_OPCODE ip @ jump to next instruction 4858 4859 4860/* ------------------------------ */ 4861 .balign 128 4862.L_op_mul_float: /* 0xa8 */ 4863/* File: arm/op_mul_float.S */ 4864/* File: arm/fbinop.S */ 4865 /* 4866 * Generic 32-bit floating-point operation. Provide an "instr" line that 4867 * specifies an instruction that performs "s2 = s0 op s1". Because we 4868 * use the "softfp" ABI, this must be an instruction, not a function call. 4869 * 4870 * For: add-float, sub-float, mul-float, div-float 4871 */ 4872 /* floatop vAA, vBB, vCC */ 4873 FETCH r0, 1 @ r0<- CCBB 4874 mov r9, rINST, lsr #8 @ r9<- AA 4875 mov r3, r0, lsr #8 @ r3<- CC 4876 and r2, r0, #255 @ r2<- BB 4877 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4878 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4879 flds s1, [r3] @ s1<- vCC 4880 flds s0, [r2] @ s0<- vBB 4881 4882 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4883 fmuls s2, s0, s1 @ s2<- op 4884 GET_INST_OPCODE ip @ extract opcode from rINST 4885 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 4886 fsts s2, [r9] @ vAA<- s2 4887 GOTO_OPCODE ip @ jump to next instruction 4888 4889 4890/* ------------------------------ */ 4891 .balign 128 4892.L_op_div_float: /* 0xa9 */ 4893/* File: arm/op_div_float.S */ 4894/* File: arm/fbinop.S */ 4895 /* 4896 * Generic 32-bit floating-point operation. Provide an "instr" line that 4897 * specifies an instruction that performs "s2 = s0 op s1". Because we 4898 * use the "softfp" ABI, this must be an instruction, not a function call. 4899 * 4900 * For: add-float, sub-float, mul-float, div-float 4901 */ 4902 /* floatop vAA, vBB, vCC */ 4903 FETCH r0, 1 @ r0<- CCBB 4904 mov r9, rINST, lsr #8 @ r9<- AA 4905 mov r3, r0, lsr #8 @ r3<- CC 4906 and r2, r0, #255 @ r2<- BB 4907 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4908 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4909 flds s1, [r3] @ s1<- vCC 4910 flds s0, [r2] @ s0<- vBB 4911 4912 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4913 fdivs s2, s0, s1 @ s2<- op 4914 GET_INST_OPCODE ip @ extract opcode from rINST 4915 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 4916 fsts s2, [r9] @ vAA<- s2 4917 GOTO_OPCODE ip @ jump to next instruction 4918 4919 4920/* ------------------------------ */ 4921 .balign 128 4922.L_op_rem_float: /* 0xaa */ 4923/* File: arm/op_rem_float.S */ 4924/* EABI doesn't define a float remainder function, but libm does */ 4925/* File: arm/binop.S */ 4926 /* 4927 * Generic 32-bit binary operation. Provide an "instr" line that 4928 * specifies an instruction that performs "result = r0 op r1". 4929 * This could be an ARM instruction or a function call. (If the result 4930 * comes back in a register other than r0, you can override "result".) 4931 * 4932 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4933 * vCC (r1). Useful for integer division and modulus. Note that we 4934 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4935 * handles it correctly. 4936 * 4937 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4938 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4939 * mul-float, div-float, rem-float 4940 */ 4941 /* binop vAA, vBB, vCC */ 4942 FETCH r0, 1 @ r0<- CCBB 4943 mov r9, rINST, lsr #8 @ r9<- AA 4944 mov r3, r0, lsr #8 @ r3<- CC 4945 and r2, r0, #255 @ r2<- BB 4946 GET_VREG r1, r3 @ r1<- vCC 4947 GET_VREG r0, r2 @ r0<- vBB 4948 .if 0 4949 cmp r1, #0 @ is second operand zero? 4950 beq common_errDivideByZero 4951 .endif 4952 4953 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4954 @ optional op; may set condition codes 4955 bl fmodf @ r0<- op, r0-r3 changed 4956 GET_INST_OPCODE ip @ extract opcode from rINST 4957 SET_VREG r0, r9 @ vAA<- r0 4958 GOTO_OPCODE ip @ jump to next instruction 4959 /* 11-14 instructions */ 4960 4961 4962/* ------------------------------ */ 4963 .balign 128 4964.L_op_add_double: /* 0xab */ 4965/* File: arm/op_add_double.S */ 4966/* File: arm/fbinopWide.S */ 4967 /* 4968 * Generic 64-bit double-precision floating point binary operation. 4969 * Provide an "instr" line that specifies an instruction that performs 4970 * "d2 = d0 op d1". 4971 * 4972 * for: add-double, sub-double, mul-double, div-double 4973 */ 4974 /* doubleop vAA, vBB, vCC */ 4975 FETCH r0, 1 @ r0<- CCBB 4976 mov r9, rINST, lsr #8 @ r9<- AA 4977 mov r3, r0, lsr #8 @ r3<- CC 4978 and r2, r0, #255 @ r2<- BB 4979 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4980 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4981 fldd d1, [r3] @ d1<- vCC 4982 fldd d0, [r2] @ d0<- vBB 4983 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4984 faddd d2, d0, d1 @ s2<- op 4985 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 4986 GET_INST_OPCODE ip @ extract opcode from rINST 4987 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 4988 fstd d2, [r9] @ vAA<- d2 4989 GOTO_OPCODE ip @ jump to next instruction 4990 4991 4992/* ------------------------------ */ 4993 .balign 128 4994.L_op_sub_double: /* 0xac */ 4995/* File: arm/op_sub_double.S */ 4996/* File: arm/fbinopWide.S */ 4997 /* 4998 * Generic 64-bit double-precision floating point binary operation. 4999 * Provide an "instr" line that specifies an instruction that performs 5000 * "d2 = d0 op d1". 5001 * 5002 * for: add-double, sub-double, mul-double, div-double 5003 */ 5004 /* doubleop vAA, vBB, vCC */ 5005 FETCH r0, 1 @ r0<- CCBB 5006 mov r9, rINST, lsr #8 @ r9<- AA 5007 mov r3, r0, lsr #8 @ r3<- CC 5008 and r2, r0, #255 @ r2<- BB 5009 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 5010 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 5011 fldd d1, [r3] @ d1<- vCC 5012 fldd d0, [r2] @ d0<- vBB 5013 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 5014 fsubd d2, d0, d1 @ s2<- op 5015 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 5016 GET_INST_OPCODE ip @ extract opcode from rINST 5017 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 5018 fstd d2, [r9] @ vAA<- d2 5019 GOTO_OPCODE ip @ jump to next instruction 5020 5021 5022/* ------------------------------ */ 5023 .balign 128 5024.L_op_mul_double: /* 0xad */ 5025/* File: arm/op_mul_double.S */ 5026/* File: arm/fbinopWide.S */ 5027 /* 5028 * Generic 64-bit double-precision floating point binary operation. 5029 * Provide an "instr" line that specifies an instruction that performs 5030 * "d2 = d0 op d1". 5031 * 5032 * for: add-double, sub-double, mul-double, div-double 5033 */ 5034 /* doubleop vAA, vBB, vCC */ 5035 FETCH r0, 1 @ r0<- CCBB 5036 mov r9, rINST, lsr #8 @ r9<- AA 5037 mov r3, r0, lsr #8 @ r3<- CC 5038 and r2, r0, #255 @ r2<- BB 5039 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 5040 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 5041 fldd d1, [r3] @ d1<- vCC 5042 fldd d0, [r2] @ d0<- vBB 5043 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 5044 fmuld d2, d0, d1 @ s2<- op 5045 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 5046 GET_INST_OPCODE ip @ extract opcode from rINST 5047 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 5048 fstd d2, [r9] @ vAA<- d2 5049 GOTO_OPCODE ip @ jump to next instruction 5050 5051 5052/* ------------------------------ */ 5053 .balign 128 5054.L_op_div_double: /* 0xae */ 5055/* File: arm/op_div_double.S */ 5056/* File: arm/fbinopWide.S */ 5057 /* 5058 * Generic 64-bit double-precision floating point binary operation. 5059 * Provide an "instr" line that specifies an instruction that performs 5060 * "d2 = d0 op d1". 5061 * 5062 * for: add-double, sub-double, mul-double, div-double 5063 */ 5064 /* doubleop vAA, vBB, vCC */ 5065 FETCH r0, 1 @ r0<- CCBB 5066 mov r9, rINST, lsr #8 @ r9<- AA 5067 mov r3, r0, lsr #8 @ r3<- CC 5068 and r2, r0, #255 @ r2<- BB 5069 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 5070 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 5071 fldd d1, [r3] @ d1<- vCC 5072 fldd d0, [r2] @ d0<- vBB 5073 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 5074 fdivd d2, d0, d1 @ s2<- op 5075 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 5076 GET_INST_OPCODE ip @ extract opcode from rINST 5077 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 5078 fstd d2, [r9] @ vAA<- d2 5079 GOTO_OPCODE ip @ jump to next instruction 5080 5081 5082/* ------------------------------ */ 5083 .balign 128 5084.L_op_rem_double: /* 0xaf */ 5085/* File: arm/op_rem_double.S */ 5086/* EABI doesn't define a double remainder function, but libm does */ 5087/* File: arm/binopWide.S */ 5088 /* 5089 * Generic 64-bit binary operation. Provide an "instr" line that 5090 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5091 * This could be an ARM instruction or a function call. (If the result 5092 * comes back in a register other than r0, you can override "result".) 5093 * 5094 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5095 * vCC (r1). Useful for integer division and modulus. 5096 * 5097 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5098 * xor-long, add-double, sub-double, mul-double, div-double, 5099 * rem-double 5100 * 5101 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5102 */ 5103 /* binop vAA, vBB, vCC */ 5104 FETCH r0, 1 @ r0<- CCBB 5105 mov rINST, rINST, lsr #8 @ rINST<- AA 5106 and r2, r0, #255 @ r2<- BB 5107 mov r3, r0, lsr #8 @ r3<- CC 5108 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 5109 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 5110 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 5111 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5112 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5113 .if 0 5114 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5115 beq common_errDivideByZero 5116 .endif 5117 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 5118 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 5119 @ optional op; may set condition codes 5120 bl fmod @ result<- op, r0-r3 changed 5121 GET_INST_OPCODE ip @ extract opcode from rINST 5122 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5123 GOTO_OPCODE ip @ jump to next instruction 5124 /* 14-17 instructions */ 5125 5126 5127/* ------------------------------ */ 5128 .balign 128 5129.L_op_add_int_2addr: /* 0xb0 */ 5130/* File: arm/op_add_int_2addr.S */ 5131/* File: arm/binop2addr.S */ 5132 /* 5133 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5134 * that specifies an instruction that performs "result = r0 op r1". 5135 * This could be an ARM instruction or a function call. (If the result 5136 * comes back in a register other than r0, you can override "result".) 5137 * 5138 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5139 * vCC (r1). Useful for integer division and modulus. 5140 * 5141 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5142 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5143 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5144 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5145 */ 5146 /* binop/2addr vA, vB */ 5147 mov r3, rINST, lsr #12 @ r3<- B 5148 ubfx r9, rINST, #8, #4 @ r9<- A 5149 GET_VREG r1, r3 @ r1<- vB 5150 GET_VREG r0, r9 @ r0<- vA 5151 .if 0 5152 cmp r1, #0 @ is second operand zero? 5153 beq common_errDivideByZero 5154 .endif 5155 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5156 5157 @ optional op; may set condition codes 5158 add r0, r0, r1 @ r0<- op, r0-r3 changed 5159 GET_INST_OPCODE ip @ extract opcode from rINST 5160 SET_VREG r0, r9 @ vAA<- r0 5161 GOTO_OPCODE ip @ jump to next instruction 5162 /* 10-13 instructions */ 5163 5164 5165/* ------------------------------ */ 5166 .balign 128 5167.L_op_sub_int_2addr: /* 0xb1 */ 5168/* File: arm/op_sub_int_2addr.S */ 5169/* File: arm/binop2addr.S */ 5170 /* 5171 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5172 * that specifies an instruction that performs "result = r0 op r1". 5173 * This could be an ARM instruction or a function call. (If the result 5174 * comes back in a register other than r0, you can override "result".) 5175 * 5176 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5177 * vCC (r1). Useful for integer division and modulus. 5178 * 5179 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5180 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5181 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5182 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5183 */ 5184 /* binop/2addr vA, vB */ 5185 mov r3, rINST, lsr #12 @ r3<- B 5186 ubfx r9, rINST, #8, #4 @ r9<- A 5187 GET_VREG r1, r3 @ r1<- vB 5188 GET_VREG r0, r9 @ r0<- vA 5189 .if 0 5190 cmp r1, #0 @ is second operand zero? 5191 beq common_errDivideByZero 5192 .endif 5193 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5194 5195 @ optional op; may set condition codes 5196 sub r0, r0, r1 @ r0<- op, r0-r3 changed 5197 GET_INST_OPCODE ip @ extract opcode from rINST 5198 SET_VREG r0, r9 @ vAA<- r0 5199 GOTO_OPCODE ip @ jump to next instruction 5200 /* 10-13 instructions */ 5201 5202 5203/* ------------------------------ */ 5204 .balign 128 5205.L_op_mul_int_2addr: /* 0xb2 */ 5206/* File: arm/op_mul_int_2addr.S */ 5207/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5208/* File: arm/binop2addr.S */ 5209 /* 5210 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5211 * that specifies an instruction that performs "result = r0 op r1". 5212 * This could be an ARM instruction or a function call. (If the result 5213 * comes back in a register other than r0, you can override "result".) 5214 * 5215 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5216 * vCC (r1). Useful for integer division and modulus. 5217 * 5218 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5219 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5220 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5221 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5222 */ 5223 /* binop/2addr vA, vB */ 5224 mov r3, rINST, lsr #12 @ r3<- B 5225 ubfx r9, rINST, #8, #4 @ r9<- A 5226 GET_VREG r1, r3 @ r1<- vB 5227 GET_VREG r0, r9 @ r0<- vA 5228 .if 0 5229 cmp r1, #0 @ is second operand zero? 5230 beq common_errDivideByZero 5231 .endif 5232 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5233 5234 @ optional op; may set condition codes 5235 mul r0, r1, r0 @ r0<- op, r0-r3 changed 5236 GET_INST_OPCODE ip @ extract opcode from rINST 5237 SET_VREG r0, r9 @ vAA<- r0 5238 GOTO_OPCODE ip @ jump to next instruction 5239 /* 10-13 instructions */ 5240 5241 5242/* ------------------------------ */ 5243 .balign 128 5244.L_op_div_int_2addr: /* 0xb3 */ 5245/* File: arm/op_div_int_2addr.S */ 5246 /* 5247 * Specialized 32-bit binary operation 5248 * 5249 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper 5250 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 5251 * ARMv7 CPUs that have hardware division support). 5252 * 5253 * div-int/2addr 5254 * 5255 */ 5256 mov r3, rINST, lsr #12 @ r3<- B 5257 ubfx r9, rINST, #8, #4 @ r9<- A 5258 GET_VREG r1, r3 @ r1<- vB 5259 GET_VREG r0, r9 @ r0<- vA 5260 cmp r1, #0 @ is second operand zero? 5261 beq common_errDivideByZero 5262 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5263 5264#ifdef __ARM_ARCH_EXT_IDIV__ 5265 sdiv r0, r0, r1 @ r0<- op 5266#else 5267 bl __aeabi_idiv @ r0<- op, r0-r3 changed 5268#endif 5269 GET_INST_OPCODE ip @ extract opcode from rINST 5270 SET_VREG r0, r9 @ vAA<- r0 5271 GOTO_OPCODE ip @ jump to next instruction 5272 /* 10-13 instructions */ 5273 5274 5275/* ------------------------------ */ 5276 .balign 128 5277.L_op_rem_int_2addr: /* 0xb4 */ 5278/* File: arm/op_rem_int_2addr.S */ 5279 /* 5280 * Specialized 32-bit binary operation 5281 * 5282 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 5283 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 5284 * ARMv7 CPUs that have hardware division support). 5285 * 5286 * NOTE: idivmod returns quotient in r0 and remainder in r1 5287 * 5288 * rem-int/2addr 5289 * 5290 */ 5291 mov r3, rINST, lsr #12 @ r3<- B 5292 ubfx r9, rINST, #8, #4 @ r9<- A 5293 GET_VREG r1, r3 @ r1<- vB 5294 GET_VREG r0, r9 @ r0<- vA 5295 cmp r1, #0 @ is second operand zero? 5296 beq common_errDivideByZero 5297 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5298 5299#ifdef __ARM_ARCH_EXT_IDIV__ 5300 sdiv r2, r0, r1 5301 mls r1, r1, r2, r0 @ r1<- op 5302#else 5303 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5304#endif 5305 GET_INST_OPCODE ip @ extract opcode from rINST 5306 SET_VREG r1, r9 @ vAA<- r1 5307 GOTO_OPCODE ip @ jump to next instruction 5308 /* 10-13 instructions */ 5309 5310 5311/* ------------------------------ */ 5312 .balign 128 5313.L_op_and_int_2addr: /* 0xb5 */ 5314/* File: arm/op_and_int_2addr.S */ 5315/* File: arm/binop2addr.S */ 5316 /* 5317 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5318 * that specifies an instruction that performs "result = r0 op r1". 5319 * This could be an ARM instruction or a function call. (If the result 5320 * comes back in a register other than r0, you can override "result".) 5321 * 5322 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5323 * vCC (r1). Useful for integer division and modulus. 5324 * 5325 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5326 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5327 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5328 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5329 */ 5330 /* binop/2addr vA, vB */ 5331 mov r3, rINST, lsr #12 @ r3<- B 5332 ubfx r9, rINST, #8, #4 @ r9<- A 5333 GET_VREG r1, r3 @ r1<- vB 5334 GET_VREG r0, r9 @ r0<- vA 5335 .if 0 5336 cmp r1, #0 @ is second operand zero? 5337 beq common_errDivideByZero 5338 .endif 5339 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5340 5341 @ optional op; may set condition codes 5342 and r0, r0, r1 @ r0<- op, r0-r3 changed 5343 GET_INST_OPCODE ip @ extract opcode from rINST 5344 SET_VREG r0, r9 @ vAA<- r0 5345 GOTO_OPCODE ip @ jump to next instruction 5346 /* 10-13 instructions */ 5347 5348 5349/* ------------------------------ */ 5350 .balign 128 5351.L_op_or_int_2addr: /* 0xb6 */ 5352/* File: arm/op_or_int_2addr.S */ 5353/* File: arm/binop2addr.S */ 5354 /* 5355 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5356 * that specifies an instruction that performs "result = r0 op r1". 5357 * This could be an ARM instruction or a function call. (If the result 5358 * comes back in a register other than r0, you can override "result".) 5359 * 5360 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5361 * vCC (r1). Useful for integer division and modulus. 5362 * 5363 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5364 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5365 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5366 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5367 */ 5368 /* binop/2addr vA, vB */ 5369 mov r3, rINST, lsr #12 @ r3<- B 5370 ubfx r9, rINST, #8, #4 @ r9<- A 5371 GET_VREG r1, r3 @ r1<- vB 5372 GET_VREG r0, r9 @ r0<- vA 5373 .if 0 5374 cmp r1, #0 @ is second operand zero? 5375 beq common_errDivideByZero 5376 .endif 5377 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5378 5379 @ optional op; may set condition codes 5380 orr r0, r0, r1 @ r0<- op, r0-r3 changed 5381 GET_INST_OPCODE ip @ extract opcode from rINST 5382 SET_VREG r0, r9 @ vAA<- r0 5383 GOTO_OPCODE ip @ jump to next instruction 5384 /* 10-13 instructions */ 5385 5386 5387/* ------------------------------ */ 5388 .balign 128 5389.L_op_xor_int_2addr: /* 0xb7 */ 5390/* File: arm/op_xor_int_2addr.S */ 5391/* File: arm/binop2addr.S */ 5392 /* 5393 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5394 * that specifies an instruction that performs "result = r0 op r1". 5395 * This could be an ARM instruction or a function call. (If the result 5396 * comes back in a register other than r0, you can override "result".) 5397 * 5398 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5399 * vCC (r1). Useful for integer division and modulus. 5400 * 5401 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5402 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5403 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5404 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5405 */ 5406 /* binop/2addr vA, vB */ 5407 mov r3, rINST, lsr #12 @ r3<- B 5408 ubfx r9, rINST, #8, #4 @ r9<- A 5409 GET_VREG r1, r3 @ r1<- vB 5410 GET_VREG r0, r9 @ r0<- vA 5411 .if 0 5412 cmp r1, #0 @ is second operand zero? 5413 beq common_errDivideByZero 5414 .endif 5415 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5416 5417 @ optional op; may set condition codes 5418 eor r0, r0, r1 @ r0<- op, r0-r3 changed 5419 GET_INST_OPCODE ip @ extract opcode from rINST 5420 SET_VREG r0, r9 @ vAA<- r0 5421 GOTO_OPCODE ip @ jump to next instruction 5422 /* 10-13 instructions */ 5423 5424 5425/* ------------------------------ */ 5426 .balign 128 5427.L_op_shl_int_2addr: /* 0xb8 */ 5428/* File: arm/op_shl_int_2addr.S */ 5429/* File: arm/binop2addr.S */ 5430 /* 5431 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5432 * that specifies an instruction that performs "result = r0 op r1". 5433 * This could be an ARM instruction or a function call. (If the result 5434 * comes back in a register other than r0, you can override "result".) 5435 * 5436 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5437 * vCC (r1). Useful for integer division and modulus. 5438 * 5439 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5440 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5441 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5442 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5443 */ 5444 /* binop/2addr vA, vB */ 5445 mov r3, rINST, lsr #12 @ r3<- B 5446 ubfx r9, rINST, #8, #4 @ r9<- A 5447 GET_VREG r1, r3 @ r1<- vB 5448 GET_VREG r0, r9 @ r0<- vA 5449 .if 0 5450 cmp r1, #0 @ is second operand zero? 5451 beq common_errDivideByZero 5452 .endif 5453 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5454 5455 and r1, r1, #31 @ optional op; may set condition codes 5456 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5457 GET_INST_OPCODE ip @ extract opcode from rINST 5458 SET_VREG r0, r9 @ vAA<- r0 5459 GOTO_OPCODE ip @ jump to next instruction 5460 /* 10-13 instructions */ 5461 5462 5463/* ------------------------------ */ 5464 .balign 128 5465.L_op_shr_int_2addr: /* 0xb9 */ 5466/* File: arm/op_shr_int_2addr.S */ 5467/* File: arm/binop2addr.S */ 5468 /* 5469 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5470 * that specifies an instruction that performs "result = r0 op r1". 5471 * This could be an ARM instruction or a function call. (If the result 5472 * comes back in a register other than r0, you can override "result".) 5473 * 5474 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5475 * vCC (r1). Useful for integer division and modulus. 5476 * 5477 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5478 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5479 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5480 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5481 */ 5482 /* binop/2addr vA, vB */ 5483 mov r3, rINST, lsr #12 @ r3<- B 5484 ubfx r9, rINST, #8, #4 @ r9<- A 5485 GET_VREG r1, r3 @ r1<- vB 5486 GET_VREG r0, r9 @ r0<- vA 5487 .if 0 5488 cmp r1, #0 @ is second operand zero? 5489 beq common_errDivideByZero 5490 .endif 5491 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5492 5493 and r1, r1, #31 @ optional op; may set condition codes 5494 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5495 GET_INST_OPCODE ip @ extract opcode from rINST 5496 SET_VREG r0, r9 @ vAA<- r0 5497 GOTO_OPCODE ip @ jump to next instruction 5498 /* 10-13 instructions */ 5499 5500 5501/* ------------------------------ */ 5502 .balign 128 5503.L_op_ushr_int_2addr: /* 0xba */ 5504/* File: arm/op_ushr_int_2addr.S */ 5505/* File: arm/binop2addr.S */ 5506 /* 5507 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5508 * that specifies an instruction that performs "result = r0 op r1". 5509 * This could be an ARM instruction or a function call. (If the result 5510 * comes back in a register other than r0, you can override "result".) 5511 * 5512 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5513 * vCC (r1). Useful for integer division and modulus. 5514 * 5515 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5516 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5517 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5518 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5519 */ 5520 /* binop/2addr vA, vB */ 5521 mov r3, rINST, lsr #12 @ r3<- B 5522 ubfx r9, rINST, #8, #4 @ r9<- A 5523 GET_VREG r1, r3 @ r1<- vB 5524 GET_VREG r0, r9 @ r0<- vA 5525 .if 0 5526 cmp r1, #0 @ is second operand zero? 5527 beq common_errDivideByZero 5528 .endif 5529 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5530 5531 and r1, r1, #31 @ optional op; may set condition codes 5532 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5533 GET_INST_OPCODE ip @ extract opcode from rINST 5534 SET_VREG r0, r9 @ vAA<- r0 5535 GOTO_OPCODE ip @ jump to next instruction 5536 /* 10-13 instructions */ 5537 5538 5539/* ------------------------------ */ 5540 .balign 128 5541.L_op_add_long_2addr: /* 0xbb */ 5542/* File: arm/op_add_long_2addr.S */ 5543/* File: arm/binopWide2addr.S */ 5544 /* 5545 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5546 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5547 * This could be an ARM instruction or a function call. (If the result 5548 * comes back in a register other than r0, you can override "result".) 5549 * 5550 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5551 * vCC (r1). Useful for integer division and modulus. 5552 * 5553 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5554 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5555 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5556 * rem-double/2addr 5557 */ 5558 /* binop/2addr vA, vB */ 5559 mov r1, rINST, lsr #12 @ r1<- B 5560 ubfx rINST, rINST, #8, #4 @ rINST<- A 5561 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5562 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5563 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5564 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5565 .if 0 5566 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5567 beq common_errDivideByZero 5568 .endif 5569 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5570 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5571 adds r0, r0, r2 @ optional op; may set condition codes 5572 adc r1, r1, r3 @ result<- op, r0-r3 changed 5573 GET_INST_OPCODE ip @ extract opcode from rINST 5574 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5575 GOTO_OPCODE ip @ jump to next instruction 5576 /* 12-15 instructions */ 5577 5578 5579/* ------------------------------ */ 5580 .balign 128 5581.L_op_sub_long_2addr: /* 0xbc */ 5582/* File: arm/op_sub_long_2addr.S */ 5583/* File: arm/binopWide2addr.S */ 5584 /* 5585 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5586 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5587 * This could be an ARM instruction or a function call. (If the result 5588 * comes back in a register other than r0, you can override "result".) 5589 * 5590 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5591 * vCC (r1). Useful for integer division and modulus. 5592 * 5593 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5594 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5595 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5596 * rem-double/2addr 5597 */ 5598 /* binop/2addr vA, vB */ 5599 mov r1, rINST, lsr #12 @ r1<- B 5600 ubfx rINST, rINST, #8, #4 @ rINST<- A 5601 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5602 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5603 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5604 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5605 .if 0 5606 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5607 beq common_errDivideByZero 5608 .endif 5609 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5610 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5611 subs r0, r0, r2 @ optional op; may set condition codes 5612 sbc r1, r1, r3 @ result<- op, r0-r3 changed 5613 GET_INST_OPCODE ip @ extract opcode from rINST 5614 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5615 GOTO_OPCODE ip @ jump to next instruction 5616 /* 12-15 instructions */ 5617 5618 5619/* ------------------------------ */ 5620 .balign 128 5621.L_op_mul_long_2addr: /* 0xbd */ 5622/* File: arm/op_mul_long_2addr.S */ 5623 /* 5624 * Signed 64-bit integer multiply, "/2addr" version. 5625 * 5626 * See op_mul_long for an explanation. 5627 * 5628 * We get a little tight on registers, so to avoid looking up &fp[A] 5629 * again we stuff it into rINST. 5630 */ 5631 /* mul-long/2addr vA, vB */ 5632 mov r1, rINST, lsr #12 @ r1<- B 5633 ubfx r9, rINST, #8, #4 @ r9<- A 5634 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5635 VREG_INDEX_TO_ADDR rINST, r9 @ rINST<- &fp[A] 5636 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5637 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5638 mul ip, r2, r1 @ ip<- ZxW 5639 umull r1, lr, r2, r0 @ r1/lr <- ZxX 5640 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5641 mov r0, rINST @ r0<- &fp[A] (free up rINST) 5642 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5643 add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX)) 5644 GET_INST_OPCODE ip @ extract opcode from rINST 5645 stmia r0, {r1-r2} @ vAA/vAA+1<- r1/r2 5646 GOTO_OPCODE ip @ jump to next instruction 5647 5648/* ------------------------------ */ 5649 .balign 128 5650.L_op_div_long_2addr: /* 0xbe */ 5651/* File: arm/op_div_long_2addr.S */ 5652/* File: arm/binopWide2addr.S */ 5653 /* 5654 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5655 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5656 * This could be an ARM instruction or a function call. (If the result 5657 * comes back in a register other than r0, you can override "result".) 5658 * 5659 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5660 * vCC (r1). Useful for integer division and modulus. 5661 * 5662 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5663 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5664 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5665 * rem-double/2addr 5666 */ 5667 /* binop/2addr vA, vB */ 5668 mov r1, rINST, lsr #12 @ r1<- B 5669 ubfx rINST, rINST, #8, #4 @ rINST<- A 5670 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5671 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5672 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5673 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5674 .if 1 5675 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5676 beq common_errDivideByZero 5677 .endif 5678 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5679 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5680 @ optional op; may set condition codes 5681 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5682 GET_INST_OPCODE ip @ extract opcode from rINST 5683 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5684 GOTO_OPCODE ip @ jump to next instruction 5685 /* 12-15 instructions */ 5686 5687 5688/* ------------------------------ */ 5689 .balign 128 5690.L_op_rem_long_2addr: /* 0xbf */ 5691/* File: arm/op_rem_long_2addr.S */ 5692/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5693/* File: arm/binopWide2addr.S */ 5694 /* 5695 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5696 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5697 * This could be an ARM instruction or a function call. (If the result 5698 * comes back in a register other than r0, you can override "result".) 5699 * 5700 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5701 * vCC (r1). Useful for integer division and modulus. 5702 * 5703 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5704 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5705 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5706 * rem-double/2addr 5707 */ 5708 /* binop/2addr vA, vB */ 5709 mov r1, rINST, lsr #12 @ r1<- B 5710 ubfx rINST, rINST, #8, #4 @ rINST<- A 5711 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5712 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5713 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5714 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5715 .if 1 5716 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5717 beq common_errDivideByZero 5718 .endif 5719 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5720 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5721 @ optional op; may set condition codes 5722 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5723 GET_INST_OPCODE ip @ extract opcode from rINST 5724 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5725 GOTO_OPCODE ip @ jump to next instruction 5726 /* 12-15 instructions */ 5727 5728 5729/* ------------------------------ */ 5730 .balign 128 5731.L_op_and_long_2addr: /* 0xc0 */ 5732/* File: arm/op_and_long_2addr.S */ 5733/* File: arm/binopWide2addr.S */ 5734 /* 5735 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5736 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5737 * This could be an ARM instruction or a function call. (If the result 5738 * comes back in a register other than r0, you can override "result".) 5739 * 5740 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5741 * vCC (r1). Useful for integer division and modulus. 5742 * 5743 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5744 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5745 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5746 * rem-double/2addr 5747 */ 5748 /* binop/2addr vA, vB */ 5749 mov r1, rINST, lsr #12 @ r1<- B 5750 ubfx rINST, rINST, #8, #4 @ rINST<- A 5751 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5752 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5753 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5754 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5755 .if 0 5756 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5757 beq common_errDivideByZero 5758 .endif 5759 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5760 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5761 and r0, r0, r2 @ optional op; may set condition codes 5762 and r1, r1, r3 @ result<- op, r0-r3 changed 5763 GET_INST_OPCODE ip @ extract opcode from rINST 5764 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5765 GOTO_OPCODE ip @ jump to next instruction 5766 /* 12-15 instructions */ 5767 5768 5769/* ------------------------------ */ 5770 .balign 128 5771.L_op_or_long_2addr: /* 0xc1 */ 5772/* File: arm/op_or_long_2addr.S */ 5773/* File: arm/binopWide2addr.S */ 5774 /* 5775 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5776 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5777 * This could be an ARM instruction or a function call. (If the result 5778 * comes back in a register other than r0, you can override "result".) 5779 * 5780 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5781 * vCC (r1). Useful for integer division and modulus. 5782 * 5783 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5784 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5785 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5786 * rem-double/2addr 5787 */ 5788 /* binop/2addr vA, vB */ 5789 mov r1, rINST, lsr #12 @ r1<- B 5790 ubfx rINST, rINST, #8, #4 @ rINST<- A 5791 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5792 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5793 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5794 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5795 .if 0 5796 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5797 beq common_errDivideByZero 5798 .endif 5799 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5800 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5801 orr r0, r0, r2 @ optional op; may set condition codes 5802 orr r1, r1, r3 @ result<- op, r0-r3 changed 5803 GET_INST_OPCODE ip @ extract opcode from rINST 5804 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5805 GOTO_OPCODE ip @ jump to next instruction 5806 /* 12-15 instructions */ 5807 5808 5809/* ------------------------------ */ 5810 .balign 128 5811.L_op_xor_long_2addr: /* 0xc2 */ 5812/* File: arm/op_xor_long_2addr.S */ 5813/* File: arm/binopWide2addr.S */ 5814 /* 5815 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5816 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5817 * This could be an ARM instruction or a function call. (If the result 5818 * comes back in a register other than r0, you can override "result".) 5819 * 5820 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5821 * vCC (r1). Useful for integer division and modulus. 5822 * 5823 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5824 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5825 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5826 * rem-double/2addr 5827 */ 5828 /* binop/2addr vA, vB */ 5829 mov r1, rINST, lsr #12 @ r1<- B 5830 ubfx rINST, rINST, #8, #4 @ rINST<- A 5831 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5832 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5833 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5834 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5835 .if 0 5836 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5837 beq common_errDivideByZero 5838 .endif 5839 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5840 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5841 eor r0, r0, r2 @ optional op; may set condition codes 5842 eor r1, r1, r3 @ result<- op, r0-r3 changed 5843 GET_INST_OPCODE ip @ extract opcode from rINST 5844 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5845 GOTO_OPCODE ip @ jump to next instruction 5846 /* 12-15 instructions */ 5847 5848 5849/* ------------------------------ */ 5850 .balign 128 5851.L_op_shl_long_2addr: /* 0xc3 */ 5852/* File: arm/op_shl_long_2addr.S */ 5853 /* 5854 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5855 * 32-bit shift distance. 5856 */ 5857 /* shl-long/2addr vA, vB */ 5858 mov r3, rINST, lsr #12 @ r3<- B 5859 ubfx r9, rINST, #8, #4 @ r9<- A 5860 GET_VREG r2, r3 @ r2<- vB 5861 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 5862 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] 5863 and r2, r2, #63 @ r2<- r2 & 0x3f 5864 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5865 mov r1, r1, asl r2 @ r1<- r1 << r2 5866 rsb r3, r2, #32 @ r3<- 32 - r2 5867 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 5868 subs ip, r2, #32 @ ip<- r2 - 32 5869 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5870 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 5871 mov r0, r0, asl r2 @ r0<- r0 << r2 5872 GET_INST_OPCODE ip @ extract opcode from rINST 5873 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 5874 GOTO_OPCODE ip @ jump to next instruction 5875 5876/* ------------------------------ */ 5877 .balign 128 5878.L_op_shr_long_2addr: /* 0xc4 */ 5879/* File: arm/op_shr_long_2addr.S */ 5880 /* 5881 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5882 * 32-bit shift distance. 5883 */ 5884 /* shr-long/2addr vA, vB */ 5885 mov r3, rINST, lsr #12 @ r3<- B 5886 ubfx r9, rINST, #8, #4 @ r9<- A 5887 GET_VREG r2, r3 @ r2<- vB 5888 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 5889 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] 5890 and r2, r2, #63 @ r2<- r2 & 0x3f 5891 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5892 mov r0, r0, lsr r2 @ r0<- r2 >> r2 5893 rsb r3, r2, #32 @ r3<- 32 - r2 5894 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 5895 subs ip, r2, #32 @ ip<- r2 - 32 5896 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5897 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 5898 mov r1, r1, asr r2 @ r1<- r1 >> r2 5899 GET_INST_OPCODE ip @ extract opcode from rINST 5900 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 5901 GOTO_OPCODE ip @ jump to next instruction 5902 5903/* ------------------------------ */ 5904 .balign 128 5905.L_op_ushr_long_2addr: /* 0xc5 */ 5906/* File: arm/op_ushr_long_2addr.S */ 5907 /* 5908 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5909 * 32-bit shift distance. 5910 */ 5911 /* ushr-long/2addr vA, vB */ 5912 mov r3, rINST, lsr #12 @ r3<- B 5913 ubfx r9, rINST, #8, #4 @ r9<- A 5914 GET_VREG r2, r3 @ r2<- vB 5915 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 5916 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] 5917 and r2, r2, #63 @ r2<- r2 & 0x3f 5918 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5919 mov r0, r0, lsr r2 @ r0<- r2 >> r2 5920 rsb r3, r2, #32 @ r3<- 32 - r2 5921 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 5922 subs ip, r2, #32 @ ip<- r2 - 32 5923 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5924 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 5925 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 5926 GET_INST_OPCODE ip @ extract opcode from rINST 5927 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 5928 GOTO_OPCODE ip @ jump to next instruction 5929 5930/* ------------------------------ */ 5931 .balign 128 5932.L_op_add_float_2addr: /* 0xc6 */ 5933/* File: arm/op_add_float_2addr.S */ 5934/* File: arm/fbinop2addr.S */ 5935 /* 5936 * Generic 32-bit floating point "/2addr" binary operation. Provide 5937 * an "instr" line that specifies an instruction that performs 5938 * "s2 = s0 op s1". 5939 * 5940 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5941 */ 5942 /* binop/2addr vA, vB */ 5943 mov r3, rINST, lsr #12 @ r3<- B 5944 ubfx r9, rINST, #8, #4 @ r9<- A 5945 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 5946 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 5947 flds s1, [r3] @ s1<- vB 5948 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5949 flds s0, [r9] @ s0<- vA 5950 fadds s2, s0, s1 @ s2<- op 5951 GET_INST_OPCODE ip @ extract opcode from rINST 5952 fsts s2, [r9] @ vAA<- s2 5953 GOTO_OPCODE ip @ jump to next instruction 5954 5955 5956/* ------------------------------ */ 5957 .balign 128 5958.L_op_sub_float_2addr: /* 0xc7 */ 5959/* File: arm/op_sub_float_2addr.S */ 5960/* File: arm/fbinop2addr.S */ 5961 /* 5962 * Generic 32-bit floating point "/2addr" binary operation. Provide 5963 * an "instr" line that specifies an instruction that performs 5964 * "s2 = s0 op s1". 5965 * 5966 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5967 */ 5968 /* binop/2addr vA, vB */ 5969 mov r3, rINST, lsr #12 @ r3<- B 5970 ubfx r9, rINST, #8, #4 @ r9<- A 5971 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 5972 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 5973 flds s1, [r3] @ s1<- vB 5974 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5975 flds s0, [r9] @ s0<- vA 5976 fsubs s2, s0, s1 @ s2<- op 5977 GET_INST_OPCODE ip @ extract opcode from rINST 5978 fsts s2, [r9] @ vAA<- s2 5979 GOTO_OPCODE ip @ jump to next instruction 5980 5981 5982/* ------------------------------ */ 5983 .balign 128 5984.L_op_mul_float_2addr: /* 0xc8 */ 5985/* File: arm/op_mul_float_2addr.S */ 5986/* File: arm/fbinop2addr.S */ 5987 /* 5988 * Generic 32-bit floating point "/2addr" binary operation. Provide 5989 * an "instr" line that specifies an instruction that performs 5990 * "s2 = s0 op s1". 5991 * 5992 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5993 */ 5994 /* binop/2addr vA, vB */ 5995 mov r3, rINST, lsr #12 @ r3<- B 5996 ubfx r9, rINST, #8, #4 @ r9<- A 5997 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 5998 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 5999 flds s1, [r3] @ s1<- vB 6000 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6001 flds s0, [r9] @ s0<- vA 6002 fmuls s2, s0, s1 @ s2<- op 6003 GET_INST_OPCODE ip @ extract opcode from rINST 6004 fsts s2, [r9] @ vAA<- s2 6005 GOTO_OPCODE ip @ jump to next instruction 6006 6007 6008/* ------------------------------ */ 6009 .balign 128 6010.L_op_div_float_2addr: /* 0xc9 */ 6011/* File: arm/op_div_float_2addr.S */ 6012/* File: arm/fbinop2addr.S */ 6013 /* 6014 * Generic 32-bit floating point "/2addr" binary operation. Provide 6015 * an "instr" line that specifies an instruction that performs 6016 * "s2 = s0 op s1". 6017 * 6018 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6019 */ 6020 /* binop/2addr vA, vB */ 6021 mov r3, rINST, lsr #12 @ r3<- B 6022 ubfx r9, rINST, #8, #4 @ r9<- A 6023 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 6024 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 6025 flds s1, [r3] @ s1<- vB 6026 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6027 flds s0, [r9] @ s0<- vA 6028 fdivs s2, s0, s1 @ s2<- op 6029 GET_INST_OPCODE ip @ extract opcode from rINST 6030 fsts s2, [r9] @ vAA<- s2 6031 GOTO_OPCODE ip @ jump to next instruction 6032 6033 6034/* ------------------------------ */ 6035 .balign 128 6036.L_op_rem_float_2addr: /* 0xca */ 6037/* File: arm/op_rem_float_2addr.S */ 6038/* EABI doesn't define a float remainder function, but libm does */ 6039/* File: arm/binop2addr.S */ 6040 /* 6041 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6042 * that specifies an instruction that performs "result = r0 op r1". 6043 * This could be an ARM instruction or a function call. (If the result 6044 * comes back in a register other than r0, you can override "result".) 6045 * 6046 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6047 * vCC (r1). Useful for integer division and modulus. 6048 * 6049 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6050 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6051 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6052 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6053 */ 6054 /* binop/2addr vA, vB */ 6055 mov r3, rINST, lsr #12 @ r3<- B 6056 ubfx r9, rINST, #8, #4 @ r9<- A 6057 GET_VREG r1, r3 @ r1<- vB 6058 GET_VREG r0, r9 @ r0<- vA 6059 .if 0 6060 cmp r1, #0 @ is second operand zero? 6061 beq common_errDivideByZero 6062 .endif 6063 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6064 6065 @ optional op; may set condition codes 6066 bl fmodf @ r0<- op, r0-r3 changed 6067 GET_INST_OPCODE ip @ extract opcode from rINST 6068 SET_VREG r0, r9 @ vAA<- r0 6069 GOTO_OPCODE ip @ jump to next instruction 6070 /* 10-13 instructions */ 6071 6072 6073/* ------------------------------ */ 6074 .balign 128 6075.L_op_add_double_2addr: /* 0xcb */ 6076/* File: arm/op_add_double_2addr.S */ 6077/* File: arm/fbinopWide2addr.S */ 6078 /* 6079 * Generic 64-bit floating point "/2addr" binary operation. Provide 6080 * an "instr" line that specifies an instruction that performs 6081 * "d2 = d0 op d1". 6082 * 6083 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6084 * div-double/2addr 6085 */ 6086 /* binop/2addr vA, vB */ 6087 mov r3, rINST, lsr #12 @ r3<- B 6088 ubfx r9, rINST, #8, #4 @ r9<- A 6089 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 6090 CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs 6091 fldd d1, [r3] @ d1<- vB 6092 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 6093 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6094 fldd d0, [r9] @ d0<- vA 6095 faddd d2, d0, d1 @ d2<- op 6096 GET_INST_OPCODE ip @ extract opcode from rINST 6097 fstd d2, [r9] @ vAA<- d2 6098 GOTO_OPCODE ip @ jump to next instruction 6099 6100 6101/* ------------------------------ */ 6102 .balign 128 6103.L_op_sub_double_2addr: /* 0xcc */ 6104/* File: arm/op_sub_double_2addr.S */ 6105/* File: arm/fbinopWide2addr.S */ 6106 /* 6107 * Generic 64-bit floating point "/2addr" binary operation. Provide 6108 * an "instr" line that specifies an instruction that performs 6109 * "d2 = d0 op d1". 6110 * 6111 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6112 * div-double/2addr 6113 */ 6114 /* binop/2addr vA, vB */ 6115 mov r3, rINST, lsr #12 @ r3<- B 6116 ubfx r9, rINST, #8, #4 @ r9<- A 6117 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 6118 CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs 6119 fldd d1, [r3] @ d1<- vB 6120 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 6121 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6122 fldd d0, [r9] @ d0<- vA 6123 fsubd d2, d0, d1 @ d2<- op 6124 GET_INST_OPCODE ip @ extract opcode from rINST 6125 fstd d2, [r9] @ vAA<- d2 6126 GOTO_OPCODE ip @ jump to next instruction 6127 6128 6129/* ------------------------------ */ 6130 .balign 128 6131.L_op_mul_double_2addr: /* 0xcd */ 6132/* File: arm/op_mul_double_2addr.S */ 6133/* File: arm/fbinopWide2addr.S */ 6134 /* 6135 * Generic 64-bit floating point "/2addr" binary operation. Provide 6136 * an "instr" line that specifies an instruction that performs 6137 * "d2 = d0 op d1". 6138 * 6139 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6140 * div-double/2addr 6141 */ 6142 /* binop/2addr vA, vB */ 6143 mov r3, rINST, lsr #12 @ r3<- B 6144 ubfx r9, rINST, #8, #4 @ r9<- A 6145 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 6146 CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs 6147 fldd d1, [r3] @ d1<- vB 6148 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 6149 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6150 fldd d0, [r9] @ d0<- vA 6151 fmuld d2, d0, d1 @ d2<- op 6152 GET_INST_OPCODE ip @ extract opcode from rINST 6153 fstd d2, [r9] @ vAA<- d2 6154 GOTO_OPCODE ip @ jump to next instruction 6155 6156 6157/* ------------------------------ */ 6158 .balign 128 6159.L_op_div_double_2addr: /* 0xce */ 6160/* File: arm/op_div_double_2addr.S */ 6161/* File: arm/fbinopWide2addr.S */ 6162 /* 6163 * Generic 64-bit floating point "/2addr" binary operation. Provide 6164 * an "instr" line that specifies an instruction that performs 6165 * "d2 = d0 op d1". 6166 * 6167 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6168 * div-double/2addr 6169 */ 6170 /* binop/2addr vA, vB */ 6171 mov r3, rINST, lsr #12 @ r3<- B 6172 ubfx r9, rINST, #8, #4 @ r9<- A 6173 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 6174 CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs 6175 fldd d1, [r3] @ d1<- vB 6176 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 6177 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6178 fldd d0, [r9] @ d0<- vA 6179 fdivd d2, d0, d1 @ d2<- op 6180 GET_INST_OPCODE ip @ extract opcode from rINST 6181 fstd d2, [r9] @ vAA<- d2 6182 GOTO_OPCODE ip @ jump to next instruction 6183 6184 6185/* ------------------------------ */ 6186 .balign 128 6187.L_op_rem_double_2addr: /* 0xcf */ 6188/* File: arm/op_rem_double_2addr.S */ 6189/* EABI doesn't define a double remainder function, but libm does */ 6190/* File: arm/binopWide2addr.S */ 6191 /* 6192 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6193 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6194 * This could be an ARM instruction or a function call. (If the result 6195 * comes back in a register other than r0, you can override "result".) 6196 * 6197 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6198 * vCC (r1). Useful for integer division and modulus. 6199 * 6200 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6201 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6202 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6203 * rem-double/2addr 6204 */ 6205 /* binop/2addr vA, vB */ 6206 mov r1, rINST, lsr #12 @ r1<- B 6207 ubfx rINST, rINST, #8, #4 @ rINST<- A 6208 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 6209 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 6210 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6211 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6212 .if 0 6213 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6214 beq common_errDivideByZero 6215 .endif 6216 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 6217 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6218 @ optional op; may set condition codes 6219 bl fmod @ result<- op, r0-r3 changed 6220 GET_INST_OPCODE ip @ extract opcode from rINST 6221 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6222 GOTO_OPCODE ip @ jump to next instruction 6223 /* 12-15 instructions */ 6224 6225 6226/* ------------------------------ */ 6227 .balign 128 6228.L_op_add_int_lit16: /* 0xd0 */ 6229/* File: arm/op_add_int_lit16.S */ 6230/* File: arm/binopLit16.S */ 6231 /* 6232 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6233 * that specifies an instruction that performs "result = r0 op r1". 6234 * This could be an ARM instruction or a function call. (If the result 6235 * comes back in a register other than r0, you can override "result".) 6236 * 6237 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6238 * vCC (r1). Useful for integer division and modulus. 6239 * 6240 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6241 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6242 */ 6243 /* binop/lit16 vA, vB, #+CCCC */ 6244 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6245 mov r2, rINST, lsr #12 @ r2<- B 6246 ubfx r9, rINST, #8, #4 @ r9<- A 6247 GET_VREG r0, r2 @ r0<- vB 6248 .if 0 6249 cmp r1, #0 @ is second operand zero? 6250 beq common_errDivideByZero 6251 .endif 6252 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6253 6254 add r0, r0, r1 @ r0<- op, r0-r3 changed 6255 GET_INST_OPCODE ip @ extract opcode from rINST 6256 SET_VREG r0, r9 @ vAA<- r0 6257 GOTO_OPCODE ip @ jump to next instruction 6258 /* 10-13 instructions */ 6259 6260 6261/* ------------------------------ */ 6262 .balign 128 6263.L_op_rsub_int: /* 0xd1 */ 6264/* File: arm/op_rsub_int.S */ 6265/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6266/* File: arm/binopLit16.S */ 6267 /* 6268 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6269 * that specifies an instruction that performs "result = r0 op r1". 6270 * This could be an ARM instruction or a function call. (If the result 6271 * comes back in a register other than r0, you can override "result".) 6272 * 6273 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6274 * vCC (r1). Useful for integer division and modulus. 6275 * 6276 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6277 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6278 */ 6279 /* binop/lit16 vA, vB, #+CCCC */ 6280 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6281 mov r2, rINST, lsr #12 @ r2<- B 6282 ubfx r9, rINST, #8, #4 @ r9<- A 6283 GET_VREG r0, r2 @ r0<- vB 6284 .if 0 6285 cmp r1, #0 @ is second operand zero? 6286 beq common_errDivideByZero 6287 .endif 6288 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6289 6290 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6291 GET_INST_OPCODE ip @ extract opcode from rINST 6292 SET_VREG r0, r9 @ vAA<- r0 6293 GOTO_OPCODE ip @ jump to next instruction 6294 /* 10-13 instructions */ 6295 6296 6297/* ------------------------------ */ 6298 .balign 128 6299.L_op_mul_int_lit16: /* 0xd2 */ 6300/* File: arm/op_mul_int_lit16.S */ 6301/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6302/* File: arm/binopLit16.S */ 6303 /* 6304 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6305 * that specifies an instruction that performs "result = r0 op r1". 6306 * This could be an ARM instruction or a function call. (If the result 6307 * comes back in a register other than r0, you can override "result".) 6308 * 6309 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6310 * vCC (r1). Useful for integer division and modulus. 6311 * 6312 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6313 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6314 */ 6315 /* binop/lit16 vA, vB, #+CCCC */ 6316 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6317 mov r2, rINST, lsr #12 @ r2<- B 6318 ubfx r9, rINST, #8, #4 @ r9<- A 6319 GET_VREG r0, r2 @ r0<- vB 6320 .if 0 6321 cmp r1, #0 @ is second operand zero? 6322 beq common_errDivideByZero 6323 .endif 6324 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6325 6326 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6327 GET_INST_OPCODE ip @ extract opcode from rINST 6328 SET_VREG r0, r9 @ vAA<- r0 6329 GOTO_OPCODE ip @ jump to next instruction 6330 /* 10-13 instructions */ 6331 6332 6333/* ------------------------------ */ 6334 .balign 128 6335.L_op_div_int_lit16: /* 0xd3 */ 6336/* File: arm/op_div_int_lit16.S */ 6337 /* 6338 * Specialized 32-bit binary operation 6339 * 6340 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper 6341 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 6342 * ARMv7 CPUs that have hardware division support). 6343 * 6344 * div-int/lit16 6345 * 6346 */ 6347 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6348 mov r2, rINST, lsr #12 @ r2<- B 6349 ubfx r9, rINST, #8, #4 @ r9<- A 6350 GET_VREG r0, r2 @ r0<- vB 6351 cmp r1, #0 @ is second operand zero? 6352 beq common_errDivideByZero 6353 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6354 6355#ifdef __ARM_ARCH_EXT_IDIV__ 6356 sdiv r0, r0, r1 @ r0<- op 6357#else 6358 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6359#endif 6360 GET_INST_OPCODE ip @ extract opcode from rINST 6361 SET_VREG r0, r9 @ vAA<- r0 6362 GOTO_OPCODE ip @ jump to next instruction 6363 /* 10-13 instructions */ 6364 6365/* ------------------------------ */ 6366 .balign 128 6367.L_op_rem_int_lit16: /* 0xd4 */ 6368/* File: arm/op_rem_int_lit16.S */ 6369 /* 6370 * Specialized 32-bit binary operation 6371 * 6372 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 6373 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 6374 * ARMv7 CPUs that have hardware division support). 6375 * 6376 * NOTE: idivmod returns quotient in r0 and remainder in r1 6377 * 6378 * rem-int/lit16 6379 * 6380 */ 6381 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6382 mov r2, rINST, lsr #12 @ r2<- B 6383 ubfx r9, rINST, #8, #4 @ r9<- A 6384 GET_VREG r0, r2 @ r0<- vB 6385 cmp r1, #0 @ is second operand zero? 6386 beq common_errDivideByZero 6387 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6388 6389#ifdef __ARM_ARCH_EXT_IDIV__ 6390 sdiv r2, r0, r1 6391 mls r1, r1, r2, r0 @ r1<- op 6392#else 6393 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6394#endif 6395 GET_INST_OPCODE ip @ extract opcode from rINST 6396 SET_VREG r1, r9 @ vAA<- r1 6397 GOTO_OPCODE ip @ jump to next instruction 6398 /* 10-13 instructions */ 6399 6400/* ------------------------------ */ 6401 .balign 128 6402.L_op_and_int_lit16: /* 0xd5 */ 6403/* File: arm/op_and_int_lit16.S */ 6404/* File: arm/binopLit16.S */ 6405 /* 6406 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6407 * that specifies an instruction that performs "result = r0 op r1". 6408 * This could be an ARM instruction or a function call. (If the result 6409 * comes back in a register other than r0, you can override "result".) 6410 * 6411 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6412 * vCC (r1). Useful for integer division and modulus. 6413 * 6414 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6415 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6416 */ 6417 /* binop/lit16 vA, vB, #+CCCC */ 6418 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6419 mov r2, rINST, lsr #12 @ r2<- B 6420 ubfx r9, rINST, #8, #4 @ r9<- A 6421 GET_VREG r0, r2 @ r0<- vB 6422 .if 0 6423 cmp r1, #0 @ is second operand zero? 6424 beq common_errDivideByZero 6425 .endif 6426 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6427 6428 and r0, r0, r1 @ r0<- op, r0-r3 changed 6429 GET_INST_OPCODE ip @ extract opcode from rINST 6430 SET_VREG r0, r9 @ vAA<- r0 6431 GOTO_OPCODE ip @ jump to next instruction 6432 /* 10-13 instructions */ 6433 6434 6435/* ------------------------------ */ 6436 .balign 128 6437.L_op_or_int_lit16: /* 0xd6 */ 6438/* File: arm/op_or_int_lit16.S */ 6439/* File: arm/binopLit16.S */ 6440 /* 6441 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6442 * that specifies an instruction that performs "result = r0 op r1". 6443 * This could be an ARM instruction or a function call. (If the result 6444 * comes back in a register other than r0, you can override "result".) 6445 * 6446 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6447 * vCC (r1). Useful for integer division and modulus. 6448 * 6449 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6450 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6451 */ 6452 /* binop/lit16 vA, vB, #+CCCC */ 6453 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6454 mov r2, rINST, lsr #12 @ r2<- B 6455 ubfx r9, rINST, #8, #4 @ r9<- A 6456 GET_VREG r0, r2 @ r0<- vB 6457 .if 0 6458 cmp r1, #0 @ is second operand zero? 6459 beq common_errDivideByZero 6460 .endif 6461 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6462 6463 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6464 GET_INST_OPCODE ip @ extract opcode from rINST 6465 SET_VREG r0, r9 @ vAA<- r0 6466 GOTO_OPCODE ip @ jump to next instruction 6467 /* 10-13 instructions */ 6468 6469 6470/* ------------------------------ */ 6471 .balign 128 6472.L_op_xor_int_lit16: /* 0xd7 */ 6473/* File: arm/op_xor_int_lit16.S */ 6474/* File: arm/binopLit16.S */ 6475 /* 6476 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6477 * that specifies an instruction that performs "result = r0 op r1". 6478 * This could be an ARM instruction or a function call. (If the result 6479 * comes back in a register other than r0, you can override "result".) 6480 * 6481 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6482 * vCC (r1). Useful for integer division and modulus. 6483 * 6484 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6485 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6486 */ 6487 /* binop/lit16 vA, vB, #+CCCC */ 6488 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6489 mov r2, rINST, lsr #12 @ r2<- B 6490 ubfx r9, rINST, #8, #4 @ r9<- A 6491 GET_VREG r0, r2 @ r0<- vB 6492 .if 0 6493 cmp r1, #0 @ is second operand zero? 6494 beq common_errDivideByZero 6495 .endif 6496 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6497 6498 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6499 GET_INST_OPCODE ip @ extract opcode from rINST 6500 SET_VREG r0, r9 @ vAA<- r0 6501 GOTO_OPCODE ip @ jump to next instruction 6502 /* 10-13 instructions */ 6503 6504 6505/* ------------------------------ */ 6506 .balign 128 6507.L_op_add_int_lit8: /* 0xd8 */ 6508/* File: arm/op_add_int_lit8.S */ 6509/* File: arm/binopLit8.S */ 6510 /* 6511 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6512 * that specifies an instruction that performs "result = r0 op r1". 6513 * This could be an ARM instruction or a function call. (If the result 6514 * comes back in a register other than r0, you can override "result".) 6515 * 6516 * You can override "extract" if the extraction of the literal value 6517 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6518 * can be omitted completely if the shift is embedded in "instr". 6519 * 6520 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6521 * vCC (r1). Useful for integer division and modulus. 6522 * 6523 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6524 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6525 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6526 */ 6527 /* binop/lit8 vAA, vBB, #+CC */ 6528 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6529 mov r9, rINST, lsr #8 @ r9<- AA 6530 and r2, r3, #255 @ r2<- BB 6531 GET_VREG r0, r2 @ r0<- vBB 6532 @ optional; typically r1<- ssssssCC (sign extended) 6533 .if 0 6534 @cmp r1, #0 @ is second operand zero? 6535 beq common_errDivideByZero 6536 .endif 6537 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6538 6539 add r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed 6540 GET_INST_OPCODE ip @ extract opcode from rINST 6541 SET_VREG r0, r9 @ vAA<- r0 6542 GOTO_OPCODE ip @ jump to next instruction 6543 /* 10-12 instructions */ 6544 6545 6546/* ------------------------------ */ 6547 .balign 128 6548.L_op_rsub_int_lit8: /* 0xd9 */ 6549/* File: arm/op_rsub_int_lit8.S */ 6550/* File: arm/binopLit8.S */ 6551 /* 6552 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6553 * that specifies an instruction that performs "result = r0 op r1". 6554 * This could be an ARM instruction or a function call. (If the result 6555 * comes back in a register other than r0, you can override "result".) 6556 * 6557 * You can override "extract" if the extraction of the literal value 6558 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6559 * can be omitted completely if the shift is embedded in "instr". 6560 * 6561 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6562 * vCC (r1). Useful for integer division and modulus. 6563 * 6564 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6565 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6566 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6567 */ 6568 /* binop/lit8 vAA, vBB, #+CC */ 6569 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6570 mov r9, rINST, lsr #8 @ r9<- AA 6571 and r2, r3, #255 @ r2<- BB 6572 GET_VREG r0, r2 @ r0<- vBB 6573 @ optional; typically r1<- ssssssCC (sign extended) 6574 .if 0 6575 @cmp r1, #0 @ is second operand zero? 6576 beq common_errDivideByZero 6577 .endif 6578 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6579 6580 rsb r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed 6581 GET_INST_OPCODE ip @ extract opcode from rINST 6582 SET_VREG r0, r9 @ vAA<- r0 6583 GOTO_OPCODE ip @ jump to next instruction 6584 /* 10-12 instructions */ 6585 6586 6587/* ------------------------------ */ 6588 .balign 128 6589.L_op_mul_int_lit8: /* 0xda */ 6590/* File: arm/op_mul_int_lit8.S */ 6591/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6592/* File: arm/binopLit8.S */ 6593 /* 6594 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6595 * that specifies an instruction that performs "result = r0 op r1". 6596 * This could be an ARM instruction or a function call. (If the result 6597 * comes back in a register other than r0, you can override "result".) 6598 * 6599 * You can override "extract" if the extraction of the literal value 6600 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6601 * can be omitted completely if the shift is embedded in "instr". 6602 * 6603 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6604 * vCC (r1). Useful for integer division and modulus. 6605 * 6606 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6607 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6608 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6609 */ 6610 /* binop/lit8 vAA, vBB, #+CC */ 6611 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6612 mov r9, rINST, lsr #8 @ r9<- AA 6613 and r2, r3, #255 @ r2<- BB 6614 GET_VREG r0, r2 @ r0<- vBB 6615 asr r1, r3, #8 @ optional; typically r1<- ssssssCC (sign extended) 6616 .if 0 6617 @cmp r1, #0 @ is second operand zero? 6618 beq common_errDivideByZero 6619 .endif 6620 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6621 6622 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6623 GET_INST_OPCODE ip @ extract opcode from rINST 6624 SET_VREG r0, r9 @ vAA<- r0 6625 GOTO_OPCODE ip @ jump to next instruction 6626 /* 10-12 instructions */ 6627 6628 6629/* ------------------------------ */ 6630 .balign 128 6631.L_op_div_int_lit8: /* 0xdb */ 6632/* File: arm/op_div_int_lit8.S */ 6633 /* 6634 * Specialized 32-bit binary operation 6635 * 6636 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper 6637 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 6638 * ARMv7 CPUs that have hardware division support). 6639 * 6640 * div-int/lit8 6641 * 6642 */ 6643 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC 6644 mov r9, rINST, lsr #8 @ r9<- AA 6645 and r2, r3, #255 @ r2<- BB 6646 GET_VREG r0, r2 @ r0<- vBB 6647 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6648 @cmp r1, #0 @ is second operand zero? 6649 beq common_errDivideByZero 6650 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6651 6652#ifdef __ARM_ARCH_EXT_IDIV__ 6653 sdiv r0, r0, r1 @ r0<- op 6654#else 6655 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6656#endif 6657 GET_INST_OPCODE ip @ extract opcode from rINST 6658 SET_VREG r0, r9 @ vAA<- r0 6659 GOTO_OPCODE ip @ jump to next instruction 6660 /* 10-12 instructions */ 6661 6662/* ------------------------------ */ 6663 .balign 128 6664.L_op_rem_int_lit8: /* 0xdc */ 6665/* File: arm/op_rem_int_lit8.S */ 6666 /* 6667 * Specialized 32-bit binary operation 6668 * 6669 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 6670 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 6671 * ARMv7 CPUs that have hardware division support). 6672 * 6673 * NOTE: idivmod returns quotient in r0 and remainder in r1 6674 * 6675 * rem-int/lit8 6676 * 6677 */ 6678 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6679 mov r9, rINST, lsr #8 @ r9<- AA 6680 and r2, r3, #255 @ r2<- BB 6681 GET_VREG r0, r2 @ r0<- vBB 6682 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6683 @cmp r1, #0 @ is second operand zero? 6684 beq common_errDivideByZero 6685 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6686 6687#ifdef __ARM_ARCH_EXT_IDIV__ 6688 sdiv r2, r0, r1 6689 mls r1, r1, r2, r0 @ r1<- op 6690#else 6691 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6692#endif 6693 GET_INST_OPCODE ip @ extract opcode from rINST 6694 SET_VREG r1, r9 @ vAA<- r1 6695 GOTO_OPCODE ip @ jump to next instruction 6696 /* 10-12 instructions */ 6697 6698/* ------------------------------ */ 6699 .balign 128 6700.L_op_and_int_lit8: /* 0xdd */ 6701/* File: arm/op_and_int_lit8.S */ 6702/* File: arm/binopLit8.S */ 6703 /* 6704 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6705 * that specifies an instruction that performs "result = r0 op r1". 6706 * This could be an ARM instruction or a function call. (If the result 6707 * comes back in a register other than r0, you can override "result".) 6708 * 6709 * You can override "extract" if the extraction of the literal value 6710 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6711 * can be omitted completely if the shift is embedded in "instr". 6712 * 6713 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6714 * vCC (r1). Useful for integer division and modulus. 6715 * 6716 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6717 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6718 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6719 */ 6720 /* binop/lit8 vAA, vBB, #+CC */ 6721 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6722 mov r9, rINST, lsr #8 @ r9<- AA 6723 and r2, r3, #255 @ r2<- BB 6724 GET_VREG r0, r2 @ r0<- vBB 6725 @ optional; typically r1<- ssssssCC (sign extended) 6726 .if 0 6727 @cmp r1, #0 @ is second operand zero? 6728 beq common_errDivideByZero 6729 .endif 6730 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6731 6732 and r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed 6733 GET_INST_OPCODE ip @ extract opcode from rINST 6734 SET_VREG r0, r9 @ vAA<- r0 6735 GOTO_OPCODE ip @ jump to next instruction 6736 /* 10-12 instructions */ 6737 6738 6739/* ------------------------------ */ 6740 .balign 128 6741.L_op_or_int_lit8: /* 0xde */ 6742/* File: arm/op_or_int_lit8.S */ 6743/* File: arm/binopLit8.S */ 6744 /* 6745 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6746 * that specifies an instruction that performs "result = r0 op r1". 6747 * This could be an ARM instruction or a function call. (If the result 6748 * comes back in a register other than r0, you can override "result".) 6749 * 6750 * You can override "extract" if the extraction of the literal value 6751 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6752 * can be omitted completely if the shift is embedded in "instr". 6753 * 6754 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6755 * vCC (r1). Useful for integer division and modulus. 6756 * 6757 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6758 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6759 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6760 */ 6761 /* binop/lit8 vAA, vBB, #+CC */ 6762 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6763 mov r9, rINST, lsr #8 @ r9<- AA 6764 and r2, r3, #255 @ r2<- BB 6765 GET_VREG r0, r2 @ r0<- vBB 6766 @ optional; typically r1<- ssssssCC (sign extended) 6767 .if 0 6768 @cmp r1, #0 @ is second operand zero? 6769 beq common_errDivideByZero 6770 .endif 6771 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6772 6773 orr r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed 6774 GET_INST_OPCODE ip @ extract opcode from rINST 6775 SET_VREG r0, r9 @ vAA<- r0 6776 GOTO_OPCODE ip @ jump to next instruction 6777 /* 10-12 instructions */ 6778 6779 6780/* ------------------------------ */ 6781 .balign 128 6782.L_op_xor_int_lit8: /* 0xdf */ 6783/* File: arm/op_xor_int_lit8.S */ 6784/* File: arm/binopLit8.S */ 6785 /* 6786 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6787 * that specifies an instruction that performs "result = r0 op r1". 6788 * This could be an ARM instruction or a function call. (If the result 6789 * comes back in a register other than r0, you can override "result".) 6790 * 6791 * You can override "extract" if the extraction of the literal value 6792 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6793 * can be omitted completely if the shift is embedded in "instr". 6794 * 6795 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6796 * vCC (r1). Useful for integer division and modulus. 6797 * 6798 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6799 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6800 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6801 */ 6802 /* binop/lit8 vAA, vBB, #+CC */ 6803 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6804 mov r9, rINST, lsr #8 @ r9<- AA 6805 and r2, r3, #255 @ r2<- BB 6806 GET_VREG r0, r2 @ r0<- vBB 6807 @ optional; typically r1<- ssssssCC (sign extended) 6808 .if 0 6809 @cmp r1, #0 @ is second operand zero? 6810 beq common_errDivideByZero 6811 .endif 6812 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6813 6814 eor r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed 6815 GET_INST_OPCODE ip @ extract opcode from rINST 6816 SET_VREG r0, r9 @ vAA<- r0 6817 GOTO_OPCODE ip @ jump to next instruction 6818 /* 10-12 instructions */ 6819 6820 6821/* ------------------------------ */ 6822 .balign 128 6823.L_op_shl_int_lit8: /* 0xe0 */ 6824/* File: arm/op_shl_int_lit8.S */ 6825/* File: arm/binopLit8.S */ 6826 /* 6827 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6828 * that specifies an instruction that performs "result = r0 op r1". 6829 * This could be an ARM instruction or a function call. (If the result 6830 * comes back in a register other than r0, you can override "result".) 6831 * 6832 * You can override "extract" if the extraction of the literal value 6833 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6834 * can be omitted completely if the shift is embedded in "instr". 6835 * 6836 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6837 * vCC (r1). Useful for integer division and modulus. 6838 * 6839 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6840 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6841 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6842 */ 6843 /* binop/lit8 vAA, vBB, #+CC */ 6844 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6845 mov r9, rINST, lsr #8 @ r9<- AA 6846 and r2, r3, #255 @ r2<- BB 6847 GET_VREG r0, r2 @ r0<- vBB 6848 ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) 6849 .if 0 6850 @cmp r1, #0 @ is second operand zero? 6851 beq common_errDivideByZero 6852 .endif 6853 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6854 6855 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 6856 GET_INST_OPCODE ip @ extract opcode from rINST 6857 SET_VREG r0, r9 @ vAA<- r0 6858 GOTO_OPCODE ip @ jump to next instruction 6859 /* 10-12 instructions */ 6860 6861 6862/* ------------------------------ */ 6863 .balign 128 6864.L_op_shr_int_lit8: /* 0xe1 */ 6865/* File: arm/op_shr_int_lit8.S */ 6866/* File: arm/binopLit8.S */ 6867 /* 6868 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6869 * that specifies an instruction that performs "result = r0 op r1". 6870 * This could be an ARM instruction or a function call. (If the result 6871 * comes back in a register other than r0, you can override "result".) 6872 * 6873 * You can override "extract" if the extraction of the literal value 6874 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6875 * can be omitted completely if the shift is embedded in "instr". 6876 * 6877 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6878 * vCC (r1). Useful for integer division and modulus. 6879 * 6880 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6881 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6882 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6883 */ 6884 /* binop/lit8 vAA, vBB, #+CC */ 6885 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6886 mov r9, rINST, lsr #8 @ r9<- AA 6887 and r2, r3, #255 @ r2<- BB 6888 GET_VREG r0, r2 @ r0<- vBB 6889 ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) 6890 .if 0 6891 @cmp r1, #0 @ is second operand zero? 6892 beq common_errDivideByZero 6893 .endif 6894 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6895 6896 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 6897 GET_INST_OPCODE ip @ extract opcode from rINST 6898 SET_VREG r0, r9 @ vAA<- r0 6899 GOTO_OPCODE ip @ jump to next instruction 6900 /* 10-12 instructions */ 6901 6902 6903/* ------------------------------ */ 6904 .balign 128 6905.L_op_ushr_int_lit8: /* 0xe2 */ 6906/* File: arm/op_ushr_int_lit8.S */ 6907/* File: arm/binopLit8.S */ 6908 /* 6909 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6910 * that specifies an instruction that performs "result = r0 op r1". 6911 * This could be an ARM instruction or a function call. (If the result 6912 * comes back in a register other than r0, you can override "result".) 6913 * 6914 * You can override "extract" if the extraction of the literal value 6915 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6916 * can be omitted completely if the shift is embedded in "instr". 6917 * 6918 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6919 * vCC (r1). Useful for integer division and modulus. 6920 * 6921 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6922 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6923 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6924 */ 6925 /* binop/lit8 vAA, vBB, #+CC */ 6926 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6927 mov r9, rINST, lsr #8 @ r9<- AA 6928 and r2, r3, #255 @ r2<- BB 6929 GET_VREG r0, r2 @ r0<- vBB 6930 ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) 6931 .if 0 6932 @cmp r1, #0 @ is second operand zero? 6933 beq common_errDivideByZero 6934 .endif 6935 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6936 6937 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 6938 GET_INST_OPCODE ip @ extract opcode from rINST 6939 SET_VREG r0, r9 @ vAA<- r0 6940 GOTO_OPCODE ip @ jump to next instruction 6941 /* 10-12 instructions */ 6942 6943 6944/* ------------------------------ */ 6945 .balign 128 6946.L_op_iget_quick: /* 0xe3 */ 6947/* File: arm/op_iget_quick.S */ 6948 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6949 /* op vA, vB, offset@CCCC */ 6950 mov r2, rINST, lsr #12 @ r2<- B 6951 FETCH r1, 1 @ r1<- field byte offset 6952 GET_VREG r3, r2 @ r3<- object we're operating on 6953 ubfx r2, rINST, #8, #4 @ r2<- A 6954 cmp r3, #0 @ check object for null 6955 beq common_errNullObject @ object was null 6956 ldr r0, [r3, r1] @ r0<- obj.field 6957 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6958 SET_VREG r0, r2 @ fp[A]<- r0 6959 GET_INST_OPCODE ip @ extract opcode from rINST 6960 GOTO_OPCODE ip @ jump to next instruction 6961 6962/* ------------------------------ */ 6963 .balign 128 6964.L_op_iget_wide_quick: /* 0xe4 */ 6965/* File: arm/op_iget_wide_quick.S */ 6966 /* iget-wide-quick vA, vB, offset@CCCC */ 6967 mov r2, rINST, lsr #12 @ r2<- B 6968 FETCH ip, 1 @ ip<- field byte offset 6969 GET_VREG r3, r2 @ r3<- object we're operating on 6970 ubfx r2, rINST, #8, #4 @ r2<- A 6971 cmp r3, #0 @ check object for null 6972 beq common_errNullObject @ object was null 6973 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 6974 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6975 VREG_INDEX_TO_ADDR r3, r2 @ r3<- &fp[A] 6976 CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs 6977 GET_INST_OPCODE ip @ extract opcode from rINST 6978 stmia r3, {r0-r1} @ fp[A]<- r0/r1 6979 GOTO_OPCODE ip @ jump to next instruction 6980 6981/* ------------------------------ */ 6982 .balign 128 6983.L_op_iget_object_quick: /* 0xe5 */ 6984/* File: arm/op_iget_object_quick.S */ 6985 /* For: iget-object-quick */ 6986 /* op vA, vB, offset@CCCC */ 6987 mov r2, rINST, lsr #12 @ r2<- B 6988 FETCH r1, 1 @ r1<- field byte offset 6989 EXPORT_PC 6990 GET_VREG r0, r2 @ r0<- object we're operating on 6991 bl artIGetObjectFromMterp @ (obj, offset) 6992 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 6993 ubfx r2, rINST, #8, #4 @ r2<- A 6994 PREFETCH_INST 2 6995 cmp r3, #0 6996 bne MterpPossibleException @ bail out 6997 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 6998 ADVANCE 2 @ advance rPC 6999 GET_INST_OPCODE ip @ extract opcode from rINST 7000 GOTO_OPCODE ip @ jump to next instruction 7001 7002/* ------------------------------ */ 7003 .balign 128 7004.L_op_iput_quick: /* 0xe6 */ 7005/* File: arm/op_iput_quick.S */ 7006 /* For: iput-quick, iput-object-quick */ 7007 /* op vA, vB, offset@CCCC */ 7008 mov r2, rINST, lsr #12 @ r2<- B 7009 FETCH r1, 1 @ r1<- field byte offset 7010 GET_VREG r3, r2 @ r3<- fp[B], the object pointer 7011 ubfx r2, rINST, #8, #4 @ r2<- A 7012 cmp r3, #0 @ check object for null 7013 beq common_errNullObject @ object was null 7014 GET_VREG r0, r2 @ r0<- fp[A] 7015 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7016 str r0, [r3, r1] @ obj.field<- r0 7017 GET_INST_OPCODE ip @ extract opcode from rINST 7018 GOTO_OPCODE ip @ jump to next instruction 7019 7020/* ------------------------------ */ 7021 .balign 128 7022.L_op_iput_wide_quick: /* 0xe7 */ 7023/* File: arm/op_iput_wide_quick.S */ 7024 /* iput-wide-quick vA, vB, offset@CCCC */ 7025 mov r2, rINST, lsr #12 @ r2<- B 7026 FETCH r3, 1 @ r3<- field byte offset 7027 GET_VREG r2, r2 @ r2<- fp[B], the object pointer 7028 ubfx r0, rINST, #8, #4 @ r0<- A 7029 cmp r2, #0 @ check object for null 7030 beq common_errNullObject @ object was null 7031 VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[A] 7032 ldmia r0, {r0-r1} @ r0/r1<- fp[A]/fp[A+1] 7033 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7034 strd r0, [r2, r3] @ obj.field<- r0/r1 7035 GET_INST_OPCODE ip @ extract opcode from rINST 7036 GOTO_OPCODE ip @ jump to next instruction 7037 7038/* ------------------------------ */ 7039 .balign 128 7040.L_op_iput_object_quick: /* 0xe8 */ 7041/* File: arm/op_iput_object_quick.S */ 7042 EXPORT_PC 7043 add r0, rFP, #OFF_FP_SHADOWFRAME 7044 mov r1, rPC 7045 mov r2, rINST 7046 bl MterpIputObjectQuick 7047 cmp r0, #0 7048 beq MterpException 7049 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7050 GET_INST_OPCODE ip @ extract opcode from rINST 7051 GOTO_OPCODE ip @ jump to next instruction 7052 7053/* ------------------------------ */ 7054 .balign 128 7055.L_op_invoke_virtual_quick: /* 0xe9 */ 7056/* File: arm/op_invoke_virtual_quick.S */ 7057/* File: arm/invoke.S */ 7058 /* 7059 * Generic invoke handler wrapper. 7060 */ 7061 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7062 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7063 .extern MterpInvokeVirtualQuick 7064 EXPORT_PC 7065 mov r0, rSELF 7066 add r1, rFP, #OFF_FP_SHADOWFRAME 7067 mov r2, rPC 7068 mov r3, rINST 7069 bl MterpInvokeVirtualQuick 7070 cmp r0, #0 7071 beq MterpException 7072 FETCH_ADVANCE_INST 3 7073 bl MterpShouldSwitchInterpreters 7074 cmp r0, #0 7075 bne MterpFallback 7076 GET_INST_OPCODE ip 7077 GOTO_OPCODE ip 7078 7079 7080 7081/* ------------------------------ */ 7082 .balign 128 7083.L_op_invoke_virtual_range_quick: /* 0xea */ 7084/* File: arm/op_invoke_virtual_range_quick.S */ 7085/* File: arm/invoke.S */ 7086 /* 7087 * Generic invoke handler wrapper. 7088 */ 7089 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7090 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7091 .extern MterpInvokeVirtualQuickRange 7092 EXPORT_PC 7093 mov r0, rSELF 7094 add r1, rFP, #OFF_FP_SHADOWFRAME 7095 mov r2, rPC 7096 mov r3, rINST 7097 bl MterpInvokeVirtualQuickRange 7098 cmp r0, #0 7099 beq MterpException 7100 FETCH_ADVANCE_INST 3 7101 bl MterpShouldSwitchInterpreters 7102 cmp r0, #0 7103 bne MterpFallback 7104 GET_INST_OPCODE ip 7105 GOTO_OPCODE ip 7106 7107 7108 7109/* ------------------------------ */ 7110 .balign 128 7111.L_op_iput_boolean_quick: /* 0xeb */ 7112/* File: arm/op_iput_boolean_quick.S */ 7113/* File: arm/op_iput_quick.S */ 7114 /* For: iput-quick, iput-object-quick */ 7115 /* op vA, vB, offset@CCCC */ 7116 mov r2, rINST, lsr #12 @ r2<- B 7117 FETCH r1, 1 @ r1<- field byte offset 7118 GET_VREG r3, r2 @ r3<- fp[B], the object pointer 7119 ubfx r2, rINST, #8, #4 @ r2<- A 7120 cmp r3, #0 @ check object for null 7121 beq common_errNullObject @ object was null 7122 GET_VREG r0, r2 @ r0<- fp[A] 7123 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7124 strb r0, [r3, r1] @ obj.field<- r0 7125 GET_INST_OPCODE ip @ extract opcode from rINST 7126 GOTO_OPCODE ip @ jump to next instruction 7127 7128 7129/* ------------------------------ */ 7130 .balign 128 7131.L_op_iput_byte_quick: /* 0xec */ 7132/* File: arm/op_iput_byte_quick.S */ 7133/* File: arm/op_iput_quick.S */ 7134 /* For: iput-quick, iput-object-quick */ 7135 /* op vA, vB, offset@CCCC */ 7136 mov r2, rINST, lsr #12 @ r2<- B 7137 FETCH r1, 1 @ r1<- field byte offset 7138 GET_VREG r3, r2 @ r3<- fp[B], the object pointer 7139 ubfx r2, rINST, #8, #4 @ r2<- A 7140 cmp r3, #0 @ check object for null 7141 beq common_errNullObject @ object was null 7142 GET_VREG r0, r2 @ r0<- fp[A] 7143 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7144 strb r0, [r3, r1] @ obj.field<- r0 7145 GET_INST_OPCODE ip @ extract opcode from rINST 7146 GOTO_OPCODE ip @ jump to next instruction 7147 7148 7149/* ------------------------------ */ 7150 .balign 128 7151.L_op_iput_char_quick: /* 0xed */ 7152/* File: arm/op_iput_char_quick.S */ 7153/* File: arm/op_iput_quick.S */ 7154 /* For: iput-quick, iput-object-quick */ 7155 /* op vA, vB, offset@CCCC */ 7156 mov r2, rINST, lsr #12 @ r2<- B 7157 FETCH r1, 1 @ r1<- field byte offset 7158 GET_VREG r3, r2 @ r3<- fp[B], the object pointer 7159 ubfx r2, rINST, #8, #4 @ r2<- A 7160 cmp r3, #0 @ check object for null 7161 beq common_errNullObject @ object was null 7162 GET_VREG r0, r2 @ r0<- fp[A] 7163 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7164 strh r0, [r3, r1] @ obj.field<- r0 7165 GET_INST_OPCODE ip @ extract opcode from rINST 7166 GOTO_OPCODE ip @ jump to next instruction 7167 7168 7169/* ------------------------------ */ 7170 .balign 128 7171.L_op_iput_short_quick: /* 0xee */ 7172/* File: arm/op_iput_short_quick.S */ 7173/* File: arm/op_iput_quick.S */ 7174 /* For: iput-quick, iput-object-quick */ 7175 /* op vA, vB, offset@CCCC */ 7176 mov r2, rINST, lsr #12 @ r2<- B 7177 FETCH r1, 1 @ r1<- field byte offset 7178 GET_VREG r3, r2 @ r3<- fp[B], the object pointer 7179 ubfx r2, rINST, #8, #4 @ r2<- A 7180 cmp r3, #0 @ check object for null 7181 beq common_errNullObject @ object was null 7182 GET_VREG r0, r2 @ r0<- fp[A] 7183 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7184 strh r0, [r3, r1] @ obj.field<- r0 7185 GET_INST_OPCODE ip @ extract opcode from rINST 7186 GOTO_OPCODE ip @ jump to next instruction 7187 7188 7189/* ------------------------------ */ 7190 .balign 128 7191.L_op_iget_boolean_quick: /* 0xef */ 7192/* File: arm/op_iget_boolean_quick.S */ 7193/* File: arm/op_iget_quick.S */ 7194 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7195 /* op vA, vB, offset@CCCC */ 7196 mov r2, rINST, lsr #12 @ r2<- B 7197 FETCH r1, 1 @ r1<- field byte offset 7198 GET_VREG r3, r2 @ r3<- object we're operating on 7199 ubfx r2, rINST, #8, #4 @ r2<- A 7200 cmp r3, #0 @ check object for null 7201 beq common_errNullObject @ object was null 7202 ldrb r0, [r3, r1] @ r0<- obj.field 7203 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7204 SET_VREG r0, r2 @ fp[A]<- r0 7205 GET_INST_OPCODE ip @ extract opcode from rINST 7206 GOTO_OPCODE ip @ jump to next instruction 7207 7208 7209/* ------------------------------ */ 7210 .balign 128 7211.L_op_iget_byte_quick: /* 0xf0 */ 7212/* File: arm/op_iget_byte_quick.S */ 7213/* File: arm/op_iget_quick.S */ 7214 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7215 /* op vA, vB, offset@CCCC */ 7216 mov r2, rINST, lsr #12 @ r2<- B 7217 FETCH r1, 1 @ r1<- field byte offset 7218 GET_VREG r3, r2 @ r3<- object we're operating on 7219 ubfx r2, rINST, #8, #4 @ r2<- A 7220 cmp r3, #0 @ check object for null 7221 beq common_errNullObject @ object was null 7222 ldrsb r0, [r3, r1] @ r0<- obj.field 7223 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7224 SET_VREG r0, r2 @ fp[A]<- r0 7225 GET_INST_OPCODE ip @ extract opcode from rINST 7226 GOTO_OPCODE ip @ jump to next instruction 7227 7228 7229/* ------------------------------ */ 7230 .balign 128 7231.L_op_iget_char_quick: /* 0xf1 */ 7232/* File: arm/op_iget_char_quick.S */ 7233/* File: arm/op_iget_quick.S */ 7234 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7235 /* op vA, vB, offset@CCCC */ 7236 mov r2, rINST, lsr #12 @ r2<- B 7237 FETCH r1, 1 @ r1<- field byte offset 7238 GET_VREG r3, r2 @ r3<- object we're operating on 7239 ubfx r2, rINST, #8, #4 @ r2<- A 7240 cmp r3, #0 @ check object for null 7241 beq common_errNullObject @ object was null 7242 ldrh r0, [r3, r1] @ r0<- obj.field 7243 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7244 SET_VREG r0, r2 @ fp[A]<- r0 7245 GET_INST_OPCODE ip @ extract opcode from rINST 7246 GOTO_OPCODE ip @ jump to next instruction 7247 7248 7249/* ------------------------------ */ 7250 .balign 128 7251.L_op_iget_short_quick: /* 0xf2 */ 7252/* File: arm/op_iget_short_quick.S */ 7253/* File: arm/op_iget_quick.S */ 7254 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7255 /* op vA, vB, offset@CCCC */ 7256 mov r2, rINST, lsr #12 @ r2<- B 7257 FETCH r1, 1 @ r1<- field byte offset 7258 GET_VREG r3, r2 @ r3<- object we're operating on 7259 ubfx r2, rINST, #8, #4 @ r2<- A 7260 cmp r3, #0 @ check object for null 7261 beq common_errNullObject @ object was null 7262 ldrsh r0, [r3, r1] @ r0<- obj.field 7263 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7264 SET_VREG r0, r2 @ fp[A]<- r0 7265 GET_INST_OPCODE ip @ extract opcode from rINST 7266 GOTO_OPCODE ip @ jump to next instruction 7267 7268 7269/* ------------------------------ */ 7270 .balign 128 7271.L_op_unused_f3: /* 0xf3 */ 7272/* File: arm/op_unused_f3.S */ 7273/* File: arm/unused.S */ 7274/* 7275 * Bail to reference interpreter to throw. 7276 */ 7277 b MterpFallback 7278 7279 7280/* ------------------------------ */ 7281 .balign 128 7282.L_op_unused_f4: /* 0xf4 */ 7283/* File: arm/op_unused_f4.S */ 7284/* File: arm/unused.S */ 7285/* 7286 * Bail to reference interpreter to throw. 7287 */ 7288 b MterpFallback 7289 7290 7291/* ------------------------------ */ 7292 .balign 128 7293.L_op_unused_f5: /* 0xf5 */ 7294/* File: arm/op_unused_f5.S */ 7295/* File: arm/unused.S */ 7296/* 7297 * Bail to reference interpreter to throw. 7298 */ 7299 b MterpFallback 7300 7301 7302/* ------------------------------ */ 7303 .balign 128 7304.L_op_unused_f6: /* 0xf6 */ 7305/* File: arm/op_unused_f6.S */ 7306/* File: arm/unused.S */ 7307/* 7308 * Bail to reference interpreter to throw. 7309 */ 7310 b MterpFallback 7311 7312 7313/* ------------------------------ */ 7314 .balign 128 7315.L_op_unused_f7: /* 0xf7 */ 7316/* File: arm/op_unused_f7.S */ 7317/* File: arm/unused.S */ 7318/* 7319 * Bail to reference interpreter to throw. 7320 */ 7321 b MterpFallback 7322 7323 7324/* ------------------------------ */ 7325 .balign 128 7326.L_op_unused_f8: /* 0xf8 */ 7327/* File: arm/op_unused_f8.S */ 7328/* File: arm/unused.S */ 7329/* 7330 * Bail to reference interpreter to throw. 7331 */ 7332 b MterpFallback 7333 7334 7335/* ------------------------------ */ 7336 .balign 128 7337.L_op_unused_f9: /* 0xf9 */ 7338/* File: arm/op_unused_f9.S */ 7339/* File: arm/unused.S */ 7340/* 7341 * Bail to reference interpreter to throw. 7342 */ 7343 b MterpFallback 7344 7345 7346/* ------------------------------ */ 7347 .balign 128 7348.L_op_invoke_polymorphic: /* 0xfa */ 7349/* File: arm/op_invoke_polymorphic.S */ 7350/* File: arm/invoke_polymorphic.S */ 7351 /* 7352 * invoke-polymorphic handler wrapper. 7353 */ 7354 /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ 7355 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ 7356 .extern MterpInvokePolymorphic 7357 EXPORT_PC 7358 mov r0, rSELF 7359 add r1, rFP, #OFF_FP_SHADOWFRAME 7360 mov r2, rPC 7361 mov r3, rINST 7362 bl MterpInvokePolymorphic 7363 cmp r0, #0 7364 beq MterpException 7365 FETCH_ADVANCE_INST 4 7366 bl MterpShouldSwitchInterpreters 7367 cmp r0, #0 7368 bne MterpFallback 7369 GET_INST_OPCODE ip 7370 GOTO_OPCODE ip 7371 7372 7373/* ------------------------------ */ 7374 .balign 128 7375.L_op_invoke_polymorphic_range: /* 0xfb */ 7376/* File: arm/op_invoke_polymorphic_range.S */ 7377/* File: arm/invoke_polymorphic.S */ 7378 /* 7379 * invoke-polymorphic handler wrapper. 7380 */ 7381 /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ 7382 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ 7383 .extern MterpInvokePolymorphicRange 7384 EXPORT_PC 7385 mov r0, rSELF 7386 add r1, rFP, #OFF_FP_SHADOWFRAME 7387 mov r2, rPC 7388 mov r3, rINST 7389 bl MterpInvokePolymorphicRange 7390 cmp r0, #0 7391 beq MterpException 7392 FETCH_ADVANCE_INST 4 7393 bl MterpShouldSwitchInterpreters 7394 cmp r0, #0 7395 bne MterpFallback 7396 GET_INST_OPCODE ip 7397 GOTO_OPCODE ip 7398 7399 7400/* ------------------------------ */ 7401 .balign 128 7402.L_op_invoke_custom: /* 0xfc */ 7403/* File: arm/op_invoke_custom.S */ 7404/* File: arm/invoke.S */ 7405 /* 7406 * Generic invoke handler wrapper. 7407 */ 7408 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7409 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7410 .extern MterpInvokeCustom 7411 EXPORT_PC 7412 mov r0, rSELF 7413 add r1, rFP, #OFF_FP_SHADOWFRAME 7414 mov r2, rPC 7415 mov r3, rINST 7416 bl MterpInvokeCustom 7417 cmp r0, #0 7418 beq MterpException 7419 FETCH_ADVANCE_INST 3 7420 bl MterpShouldSwitchInterpreters 7421 cmp r0, #0 7422 bne MterpFallback 7423 GET_INST_OPCODE ip 7424 GOTO_OPCODE ip 7425 7426 7427 /* 7428 * Handle an invoke-custom invocation. 7429 * 7430 * for: invoke-custom, invoke-custom/range 7431 */ 7432 /* op vB, {vD, vE, vF, vG, vA}, call_site@BBBB */ 7433 /* op vAA, {vCCCC..v(CCCC+AA-1)}, call_site@BBBB */ 7434 7435/* ------------------------------ */ 7436 .balign 128 7437.L_op_invoke_custom_range: /* 0xfd */ 7438/* File: arm/op_invoke_custom_range.S */ 7439/* File: arm/invoke.S */ 7440 /* 7441 * Generic invoke handler wrapper. 7442 */ 7443 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7444 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7445 .extern MterpInvokeCustomRange 7446 EXPORT_PC 7447 mov r0, rSELF 7448 add r1, rFP, #OFF_FP_SHADOWFRAME 7449 mov r2, rPC 7450 mov r3, rINST 7451 bl MterpInvokeCustomRange 7452 cmp r0, #0 7453 beq MterpException 7454 FETCH_ADVANCE_INST 3 7455 bl MterpShouldSwitchInterpreters 7456 cmp r0, #0 7457 bne MterpFallback 7458 GET_INST_OPCODE ip 7459 GOTO_OPCODE ip 7460 7461 7462 7463/* ------------------------------ */ 7464 .balign 128 7465.L_op_const_method_handle: /* 0xfe */ 7466/* File: arm/op_const_method_handle.S */ 7467/* File: arm/const.S */ 7468 /* const/class vAA, type@BBBB */ 7469 /* const/method-handle vAA, method_handle@BBBB */ 7470 /* const/method-type vAA, proto@BBBB */ 7471 /* const/string vAA, string@@BBBB */ 7472 .extern MterpConstMethodHandle 7473 EXPORT_PC 7474 FETCH r0, 1 @ r0<- BBBB 7475 mov r1, rINST, lsr #8 @ r1<- AA 7476 add r2, rFP, #OFF_FP_SHADOWFRAME 7477 mov r3, rSELF 7478 bl MterpConstMethodHandle @ (index, tgt_reg, shadow_frame, self) 7479 PREFETCH_INST 2 @ load rINST 7480 cmp r0, #0 @ fail? 7481 bne MterpPossibleException @ let reference interpreter deal with it. 7482 ADVANCE 2 @ advance rPC 7483 GET_INST_OPCODE ip @ extract opcode from rINST 7484 GOTO_OPCODE ip @ jump to next instruction 7485 7486 7487/* ------------------------------ */ 7488 .balign 128 7489.L_op_const_method_type: /* 0xff */ 7490/* File: arm/op_const_method_type.S */ 7491/* File: arm/const.S */ 7492 /* const/class vAA, type@BBBB */ 7493 /* const/method-handle vAA, method_handle@BBBB */ 7494 /* const/method-type vAA, proto@BBBB */ 7495 /* const/string vAA, string@@BBBB */ 7496 .extern MterpConstMethodType 7497 EXPORT_PC 7498 FETCH r0, 1 @ r0<- BBBB 7499 mov r1, rINST, lsr #8 @ r1<- AA 7500 add r2, rFP, #OFF_FP_SHADOWFRAME 7501 mov r3, rSELF 7502 bl MterpConstMethodType @ (index, tgt_reg, shadow_frame, self) 7503 PREFETCH_INST 2 @ load rINST 7504 cmp r0, #0 @ fail? 7505 bne MterpPossibleException @ let reference interpreter deal with it. 7506 ADVANCE 2 @ advance rPC 7507 GET_INST_OPCODE ip @ extract opcode from rINST 7508 GOTO_OPCODE ip @ jump to next instruction 7509 7510 7511 .balign 128 7512 .global artMterpAsmInstructionEnd 7513artMterpAsmInstructionEnd: 7514 7515/* 7516 * =========================================================================== 7517 * Sister implementations 7518 * =========================================================================== 7519 */ 7520 .global artMterpAsmSisterStart 7521 .text 7522 .balign 4 7523artMterpAsmSisterStart: 7524 7525/* continuation for op_float_to_long */ 7526/* 7527 * Convert the float in r0 to a long in r0/r1. 7528 * 7529 * We have to clip values to long min/max per the specification. The 7530 * expected common case is a "reasonable" value that converts directly 7531 * to modest integer. The EABI convert function isn't doing this for us. 7532 */ 7533f2l_doconv: 7534 ubfx r2, r0, #23, #8 @ grab the exponent 7535 cmp r2, #0xbe @ MININT < x > MAXINT? 7536 bhs f2l_special_cases 7537 b __aeabi_f2lz @ tail call to convert float to long 7538f2l_special_cases: 7539 cmp r2, #0xff @ NaN or infinity? 7540 beq f2l_maybeNaN 7541f2l_notNaN: 7542 adds r0, r0, r0 @ sign bit to carry 7543 mov r0, #0xffffffff @ assume maxlong for lsw 7544 mov r1, #0x7fffffff @ assume maxlong for msw 7545 adc r0, r0, #0 7546 adc r1, r1, #0 @ convert maxlong to minlong if exp negative 7547 bx lr @ return 7548f2l_maybeNaN: 7549 lsls r3, r0, #9 7550 beq f2l_notNaN @ if fraction is non-zero, it's a NaN 7551 mov r0, #0 7552 mov r1, #0 7553 bx lr @ return 0 for NaN 7554 7555/* continuation for op_double_to_long */ 7556/* 7557 * Convert the double in r0/r1 to a long in r0/r1. 7558 * 7559 * We have to clip values to long min/max per the specification. The 7560 * expected common case is a "reasonable" value that converts directly 7561 * to modest integer. The EABI convert function isn't doing this for us. 7562 */ 7563d2l_doconv: 7564 ubfx r2, r1, #20, #11 @ grab the exponent 7565 movw r3, #0x43e 7566 cmp r2, r3 @ MINLONG < x > MAXLONG? 7567 bhs d2l_special_cases 7568 b __aeabi_d2lz @ tail call to convert double to long 7569d2l_special_cases: 7570 movw r3, #0x7ff 7571 cmp r2, r3 7572 beq d2l_maybeNaN @ NaN? 7573d2l_notNaN: 7574 adds r1, r1, r1 @ sign bit to carry 7575 mov r0, #0xffffffff @ assume maxlong for lsw 7576 mov r1, #0x7fffffff @ assume maxlong for msw 7577 adc r0, r0, #0 7578 adc r1, r1, #0 @ convert maxlong to minlong if exp negative 7579 bx lr @ return 7580d2l_maybeNaN: 7581 orrs r3, r0, r1, lsl #12 7582 beq d2l_notNaN @ if fraction is non-zero, it's a NaN 7583 mov r0, #0 7584 mov r1, #0 7585 bx lr @ return 0 for NaN 7586 .global artMterpAsmSisterEnd 7587artMterpAsmSisterEnd: 7588 7589 7590 .global artMterpAsmAltInstructionStart 7591 .text 7592 7593artMterpAsmAltInstructionStart = .L_ALT_op_nop 7594/* ------------------------------ */ 7595 .balign 128 7596.L_ALT_op_nop: /* 0x00 */ 7597/* File: arm/alt_stub.S */ 7598/* 7599 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7600 * any interesting requests and then jump to the real instruction 7601 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7602 */ 7603 .extern MterpCheckBefore 7604 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7605 adrl lr, artMterpAsmInstructionStart + (0 * 128) @ Addr of primary handler. 7606 mov r0, rSELF 7607 add r1, rFP, #OFF_FP_SHADOWFRAME 7608 mov r2, rPC 7609 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7610 7611/* ------------------------------ */ 7612 .balign 128 7613.L_ALT_op_move: /* 0x01 */ 7614/* File: arm/alt_stub.S */ 7615/* 7616 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7617 * any interesting requests and then jump to the real instruction 7618 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7619 */ 7620 .extern MterpCheckBefore 7621 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7622 adrl lr, artMterpAsmInstructionStart + (1 * 128) @ Addr of primary handler. 7623 mov r0, rSELF 7624 add r1, rFP, #OFF_FP_SHADOWFRAME 7625 mov r2, rPC 7626 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7627 7628/* ------------------------------ */ 7629 .balign 128 7630.L_ALT_op_move_from16: /* 0x02 */ 7631/* File: arm/alt_stub.S */ 7632/* 7633 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7634 * any interesting requests and then jump to the real instruction 7635 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7636 */ 7637 .extern MterpCheckBefore 7638 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7639 adrl lr, artMterpAsmInstructionStart + (2 * 128) @ Addr of primary handler. 7640 mov r0, rSELF 7641 add r1, rFP, #OFF_FP_SHADOWFRAME 7642 mov r2, rPC 7643 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7644 7645/* ------------------------------ */ 7646 .balign 128 7647.L_ALT_op_move_16: /* 0x03 */ 7648/* File: arm/alt_stub.S */ 7649/* 7650 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7651 * any interesting requests and then jump to the real instruction 7652 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7653 */ 7654 .extern MterpCheckBefore 7655 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7656 adrl lr, artMterpAsmInstructionStart + (3 * 128) @ Addr of primary handler. 7657 mov r0, rSELF 7658 add r1, rFP, #OFF_FP_SHADOWFRAME 7659 mov r2, rPC 7660 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7661 7662/* ------------------------------ */ 7663 .balign 128 7664.L_ALT_op_move_wide: /* 0x04 */ 7665/* File: arm/alt_stub.S */ 7666/* 7667 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7668 * any interesting requests and then jump to the real instruction 7669 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7670 */ 7671 .extern MterpCheckBefore 7672 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7673 adrl lr, artMterpAsmInstructionStart + (4 * 128) @ Addr of primary handler. 7674 mov r0, rSELF 7675 add r1, rFP, #OFF_FP_SHADOWFRAME 7676 mov r2, rPC 7677 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7678 7679/* ------------------------------ */ 7680 .balign 128 7681.L_ALT_op_move_wide_from16: /* 0x05 */ 7682/* File: arm/alt_stub.S */ 7683/* 7684 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7685 * any interesting requests and then jump to the real instruction 7686 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7687 */ 7688 .extern MterpCheckBefore 7689 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7690 adrl lr, artMterpAsmInstructionStart + (5 * 128) @ Addr of primary handler. 7691 mov r0, rSELF 7692 add r1, rFP, #OFF_FP_SHADOWFRAME 7693 mov r2, rPC 7694 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7695 7696/* ------------------------------ */ 7697 .balign 128 7698.L_ALT_op_move_wide_16: /* 0x06 */ 7699/* File: arm/alt_stub.S */ 7700/* 7701 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7702 * any interesting requests and then jump to the real instruction 7703 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7704 */ 7705 .extern MterpCheckBefore 7706 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7707 adrl lr, artMterpAsmInstructionStart + (6 * 128) @ Addr of primary handler. 7708 mov r0, rSELF 7709 add r1, rFP, #OFF_FP_SHADOWFRAME 7710 mov r2, rPC 7711 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7712 7713/* ------------------------------ */ 7714 .balign 128 7715.L_ALT_op_move_object: /* 0x07 */ 7716/* File: arm/alt_stub.S */ 7717/* 7718 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7719 * any interesting requests and then jump to the real instruction 7720 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7721 */ 7722 .extern MterpCheckBefore 7723 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7724 adrl lr, artMterpAsmInstructionStart + (7 * 128) @ Addr of primary handler. 7725 mov r0, rSELF 7726 add r1, rFP, #OFF_FP_SHADOWFRAME 7727 mov r2, rPC 7728 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7729 7730/* ------------------------------ */ 7731 .balign 128 7732.L_ALT_op_move_object_from16: /* 0x08 */ 7733/* File: arm/alt_stub.S */ 7734/* 7735 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7736 * any interesting requests and then jump to the real instruction 7737 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7738 */ 7739 .extern MterpCheckBefore 7740 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7741 adrl lr, artMterpAsmInstructionStart + (8 * 128) @ Addr of primary handler. 7742 mov r0, rSELF 7743 add r1, rFP, #OFF_FP_SHADOWFRAME 7744 mov r2, rPC 7745 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7746 7747/* ------------------------------ */ 7748 .balign 128 7749.L_ALT_op_move_object_16: /* 0x09 */ 7750/* File: arm/alt_stub.S */ 7751/* 7752 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7753 * any interesting requests and then jump to the real instruction 7754 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7755 */ 7756 .extern MterpCheckBefore 7757 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7758 adrl lr, artMterpAsmInstructionStart + (9 * 128) @ Addr of primary handler. 7759 mov r0, rSELF 7760 add r1, rFP, #OFF_FP_SHADOWFRAME 7761 mov r2, rPC 7762 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7763 7764/* ------------------------------ */ 7765 .balign 128 7766.L_ALT_op_move_result: /* 0x0a */ 7767/* File: arm/alt_stub.S */ 7768/* 7769 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7770 * any interesting requests and then jump to the real instruction 7771 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7772 */ 7773 .extern MterpCheckBefore 7774 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7775 adrl lr, artMterpAsmInstructionStart + (10 * 128) @ Addr of primary handler. 7776 mov r0, rSELF 7777 add r1, rFP, #OFF_FP_SHADOWFRAME 7778 mov r2, rPC 7779 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7780 7781/* ------------------------------ */ 7782 .balign 128 7783.L_ALT_op_move_result_wide: /* 0x0b */ 7784/* File: arm/alt_stub.S */ 7785/* 7786 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7787 * any interesting requests and then jump to the real instruction 7788 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7789 */ 7790 .extern MterpCheckBefore 7791 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7792 adrl lr, artMterpAsmInstructionStart + (11 * 128) @ Addr of primary handler. 7793 mov r0, rSELF 7794 add r1, rFP, #OFF_FP_SHADOWFRAME 7795 mov r2, rPC 7796 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7797 7798/* ------------------------------ */ 7799 .balign 128 7800.L_ALT_op_move_result_object: /* 0x0c */ 7801/* File: arm/alt_stub.S */ 7802/* 7803 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7804 * any interesting requests and then jump to the real instruction 7805 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7806 */ 7807 .extern MterpCheckBefore 7808 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7809 adrl lr, artMterpAsmInstructionStart + (12 * 128) @ Addr of primary handler. 7810 mov r0, rSELF 7811 add r1, rFP, #OFF_FP_SHADOWFRAME 7812 mov r2, rPC 7813 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7814 7815/* ------------------------------ */ 7816 .balign 128 7817.L_ALT_op_move_exception: /* 0x0d */ 7818/* File: arm/alt_stub.S */ 7819/* 7820 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7821 * any interesting requests and then jump to the real instruction 7822 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7823 */ 7824 .extern MterpCheckBefore 7825 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7826 adrl lr, artMterpAsmInstructionStart + (13 * 128) @ Addr of primary handler. 7827 mov r0, rSELF 7828 add r1, rFP, #OFF_FP_SHADOWFRAME 7829 mov r2, rPC 7830 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7831 7832/* ------------------------------ */ 7833 .balign 128 7834.L_ALT_op_return_void: /* 0x0e */ 7835/* File: arm/alt_stub.S */ 7836/* 7837 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7838 * any interesting requests and then jump to the real instruction 7839 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7840 */ 7841 .extern MterpCheckBefore 7842 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7843 adrl lr, artMterpAsmInstructionStart + (14 * 128) @ Addr of primary handler. 7844 mov r0, rSELF 7845 add r1, rFP, #OFF_FP_SHADOWFRAME 7846 mov r2, rPC 7847 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7848 7849/* ------------------------------ */ 7850 .balign 128 7851.L_ALT_op_return: /* 0x0f */ 7852/* File: arm/alt_stub.S */ 7853/* 7854 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7855 * any interesting requests and then jump to the real instruction 7856 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7857 */ 7858 .extern MterpCheckBefore 7859 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7860 adrl lr, artMterpAsmInstructionStart + (15 * 128) @ Addr of primary handler. 7861 mov r0, rSELF 7862 add r1, rFP, #OFF_FP_SHADOWFRAME 7863 mov r2, rPC 7864 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7865 7866/* ------------------------------ */ 7867 .balign 128 7868.L_ALT_op_return_wide: /* 0x10 */ 7869/* File: arm/alt_stub.S */ 7870/* 7871 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7872 * any interesting requests and then jump to the real instruction 7873 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7874 */ 7875 .extern MterpCheckBefore 7876 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7877 adrl lr, artMterpAsmInstructionStart + (16 * 128) @ Addr of primary handler. 7878 mov r0, rSELF 7879 add r1, rFP, #OFF_FP_SHADOWFRAME 7880 mov r2, rPC 7881 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7882 7883/* ------------------------------ */ 7884 .balign 128 7885.L_ALT_op_return_object: /* 0x11 */ 7886/* File: arm/alt_stub.S */ 7887/* 7888 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7889 * any interesting requests and then jump to the real instruction 7890 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7891 */ 7892 .extern MterpCheckBefore 7893 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7894 adrl lr, artMterpAsmInstructionStart + (17 * 128) @ Addr of primary handler. 7895 mov r0, rSELF 7896 add r1, rFP, #OFF_FP_SHADOWFRAME 7897 mov r2, rPC 7898 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7899 7900/* ------------------------------ */ 7901 .balign 128 7902.L_ALT_op_const_4: /* 0x12 */ 7903/* File: arm/alt_stub.S */ 7904/* 7905 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7906 * any interesting requests and then jump to the real instruction 7907 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7908 */ 7909 .extern MterpCheckBefore 7910 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7911 adrl lr, artMterpAsmInstructionStart + (18 * 128) @ Addr of primary handler. 7912 mov r0, rSELF 7913 add r1, rFP, #OFF_FP_SHADOWFRAME 7914 mov r2, rPC 7915 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7916 7917/* ------------------------------ */ 7918 .balign 128 7919.L_ALT_op_const_16: /* 0x13 */ 7920/* File: arm/alt_stub.S */ 7921/* 7922 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7923 * any interesting requests and then jump to the real instruction 7924 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7925 */ 7926 .extern MterpCheckBefore 7927 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7928 adrl lr, artMterpAsmInstructionStart + (19 * 128) @ Addr of primary handler. 7929 mov r0, rSELF 7930 add r1, rFP, #OFF_FP_SHADOWFRAME 7931 mov r2, rPC 7932 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7933 7934/* ------------------------------ */ 7935 .balign 128 7936.L_ALT_op_const: /* 0x14 */ 7937/* File: arm/alt_stub.S */ 7938/* 7939 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7940 * any interesting requests and then jump to the real instruction 7941 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7942 */ 7943 .extern MterpCheckBefore 7944 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7945 adrl lr, artMterpAsmInstructionStart + (20 * 128) @ Addr of primary handler. 7946 mov r0, rSELF 7947 add r1, rFP, #OFF_FP_SHADOWFRAME 7948 mov r2, rPC 7949 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7950 7951/* ------------------------------ */ 7952 .balign 128 7953.L_ALT_op_const_high16: /* 0x15 */ 7954/* File: arm/alt_stub.S */ 7955/* 7956 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7957 * any interesting requests and then jump to the real instruction 7958 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7959 */ 7960 .extern MterpCheckBefore 7961 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7962 adrl lr, artMterpAsmInstructionStart + (21 * 128) @ Addr of primary handler. 7963 mov r0, rSELF 7964 add r1, rFP, #OFF_FP_SHADOWFRAME 7965 mov r2, rPC 7966 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7967 7968/* ------------------------------ */ 7969 .balign 128 7970.L_ALT_op_const_wide_16: /* 0x16 */ 7971/* File: arm/alt_stub.S */ 7972/* 7973 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7974 * any interesting requests and then jump to the real instruction 7975 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7976 */ 7977 .extern MterpCheckBefore 7978 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7979 adrl lr, artMterpAsmInstructionStart + (22 * 128) @ Addr of primary handler. 7980 mov r0, rSELF 7981 add r1, rFP, #OFF_FP_SHADOWFRAME 7982 mov r2, rPC 7983 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7984 7985/* ------------------------------ */ 7986 .balign 128 7987.L_ALT_op_const_wide_32: /* 0x17 */ 7988/* File: arm/alt_stub.S */ 7989/* 7990 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7991 * any interesting requests and then jump to the real instruction 7992 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7993 */ 7994 .extern MterpCheckBefore 7995 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7996 adrl lr, artMterpAsmInstructionStart + (23 * 128) @ Addr of primary handler. 7997 mov r0, rSELF 7998 add r1, rFP, #OFF_FP_SHADOWFRAME 7999 mov r2, rPC 8000 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8001 8002/* ------------------------------ */ 8003 .balign 128 8004.L_ALT_op_const_wide: /* 0x18 */ 8005/* File: arm/alt_stub.S */ 8006/* 8007 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8008 * any interesting requests and then jump to the real instruction 8009 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8010 */ 8011 .extern MterpCheckBefore 8012 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8013 adrl lr, artMterpAsmInstructionStart + (24 * 128) @ Addr of primary handler. 8014 mov r0, rSELF 8015 add r1, rFP, #OFF_FP_SHADOWFRAME 8016 mov r2, rPC 8017 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8018 8019/* ------------------------------ */ 8020 .balign 128 8021.L_ALT_op_const_wide_high16: /* 0x19 */ 8022/* File: arm/alt_stub.S */ 8023/* 8024 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8025 * any interesting requests and then jump to the real instruction 8026 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8027 */ 8028 .extern MterpCheckBefore 8029 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8030 adrl lr, artMterpAsmInstructionStart + (25 * 128) @ Addr of primary handler. 8031 mov r0, rSELF 8032 add r1, rFP, #OFF_FP_SHADOWFRAME 8033 mov r2, rPC 8034 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8035 8036/* ------------------------------ */ 8037 .balign 128 8038.L_ALT_op_const_string: /* 0x1a */ 8039/* File: arm/alt_stub.S */ 8040/* 8041 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8042 * any interesting requests and then jump to the real instruction 8043 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8044 */ 8045 .extern MterpCheckBefore 8046 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8047 adrl lr, artMterpAsmInstructionStart + (26 * 128) @ Addr of primary handler. 8048 mov r0, rSELF 8049 add r1, rFP, #OFF_FP_SHADOWFRAME 8050 mov r2, rPC 8051 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8052 8053/* ------------------------------ */ 8054 .balign 128 8055.L_ALT_op_const_string_jumbo: /* 0x1b */ 8056/* File: arm/alt_stub.S */ 8057/* 8058 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8059 * any interesting requests and then jump to the real instruction 8060 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8061 */ 8062 .extern MterpCheckBefore 8063 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8064 adrl lr, artMterpAsmInstructionStart + (27 * 128) @ Addr of primary handler. 8065 mov r0, rSELF 8066 add r1, rFP, #OFF_FP_SHADOWFRAME 8067 mov r2, rPC 8068 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8069 8070/* ------------------------------ */ 8071 .balign 128 8072.L_ALT_op_const_class: /* 0x1c */ 8073/* File: arm/alt_stub.S */ 8074/* 8075 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8076 * any interesting requests and then jump to the real instruction 8077 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8078 */ 8079 .extern MterpCheckBefore 8080 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8081 adrl lr, artMterpAsmInstructionStart + (28 * 128) @ Addr of primary handler. 8082 mov r0, rSELF 8083 add r1, rFP, #OFF_FP_SHADOWFRAME 8084 mov r2, rPC 8085 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8086 8087/* ------------------------------ */ 8088 .balign 128 8089.L_ALT_op_monitor_enter: /* 0x1d */ 8090/* File: arm/alt_stub.S */ 8091/* 8092 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8093 * any interesting requests and then jump to the real instruction 8094 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8095 */ 8096 .extern MterpCheckBefore 8097 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8098 adrl lr, artMterpAsmInstructionStart + (29 * 128) @ Addr of primary handler. 8099 mov r0, rSELF 8100 add r1, rFP, #OFF_FP_SHADOWFRAME 8101 mov r2, rPC 8102 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8103 8104/* ------------------------------ */ 8105 .balign 128 8106.L_ALT_op_monitor_exit: /* 0x1e */ 8107/* File: arm/alt_stub.S */ 8108/* 8109 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8110 * any interesting requests and then jump to the real instruction 8111 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8112 */ 8113 .extern MterpCheckBefore 8114 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8115 adrl lr, artMterpAsmInstructionStart + (30 * 128) @ Addr of primary handler. 8116 mov r0, rSELF 8117 add r1, rFP, #OFF_FP_SHADOWFRAME 8118 mov r2, rPC 8119 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8120 8121/* ------------------------------ */ 8122 .balign 128 8123.L_ALT_op_check_cast: /* 0x1f */ 8124/* File: arm/alt_stub.S */ 8125/* 8126 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8127 * any interesting requests and then jump to the real instruction 8128 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8129 */ 8130 .extern MterpCheckBefore 8131 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8132 adrl lr, artMterpAsmInstructionStart + (31 * 128) @ Addr of primary handler. 8133 mov r0, rSELF 8134 add r1, rFP, #OFF_FP_SHADOWFRAME 8135 mov r2, rPC 8136 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8137 8138/* ------------------------------ */ 8139 .balign 128 8140.L_ALT_op_instance_of: /* 0x20 */ 8141/* File: arm/alt_stub.S */ 8142/* 8143 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8144 * any interesting requests and then jump to the real instruction 8145 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8146 */ 8147 .extern MterpCheckBefore 8148 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8149 adrl lr, artMterpAsmInstructionStart + (32 * 128) @ Addr of primary handler. 8150 mov r0, rSELF 8151 add r1, rFP, #OFF_FP_SHADOWFRAME 8152 mov r2, rPC 8153 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8154 8155/* ------------------------------ */ 8156 .balign 128 8157.L_ALT_op_array_length: /* 0x21 */ 8158/* File: arm/alt_stub.S */ 8159/* 8160 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8161 * any interesting requests and then jump to the real instruction 8162 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8163 */ 8164 .extern MterpCheckBefore 8165 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8166 adrl lr, artMterpAsmInstructionStart + (33 * 128) @ Addr of primary handler. 8167 mov r0, rSELF 8168 add r1, rFP, #OFF_FP_SHADOWFRAME 8169 mov r2, rPC 8170 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8171 8172/* ------------------------------ */ 8173 .balign 128 8174.L_ALT_op_new_instance: /* 0x22 */ 8175/* File: arm/alt_stub.S */ 8176/* 8177 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8178 * any interesting requests and then jump to the real instruction 8179 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8180 */ 8181 .extern MterpCheckBefore 8182 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8183 adrl lr, artMterpAsmInstructionStart + (34 * 128) @ Addr of primary handler. 8184 mov r0, rSELF 8185 add r1, rFP, #OFF_FP_SHADOWFRAME 8186 mov r2, rPC 8187 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8188 8189/* ------------------------------ */ 8190 .balign 128 8191.L_ALT_op_new_array: /* 0x23 */ 8192/* File: arm/alt_stub.S */ 8193/* 8194 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8195 * any interesting requests and then jump to the real instruction 8196 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8197 */ 8198 .extern MterpCheckBefore 8199 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8200 adrl lr, artMterpAsmInstructionStart + (35 * 128) @ Addr of primary handler. 8201 mov r0, rSELF 8202 add r1, rFP, #OFF_FP_SHADOWFRAME 8203 mov r2, rPC 8204 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8205 8206/* ------------------------------ */ 8207 .balign 128 8208.L_ALT_op_filled_new_array: /* 0x24 */ 8209/* File: arm/alt_stub.S */ 8210/* 8211 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8212 * any interesting requests and then jump to the real instruction 8213 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8214 */ 8215 .extern MterpCheckBefore 8216 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8217 adrl lr, artMterpAsmInstructionStart + (36 * 128) @ Addr of primary handler. 8218 mov r0, rSELF 8219 add r1, rFP, #OFF_FP_SHADOWFRAME 8220 mov r2, rPC 8221 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8222 8223/* ------------------------------ */ 8224 .balign 128 8225.L_ALT_op_filled_new_array_range: /* 0x25 */ 8226/* File: arm/alt_stub.S */ 8227/* 8228 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8229 * any interesting requests and then jump to the real instruction 8230 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8231 */ 8232 .extern MterpCheckBefore 8233 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8234 adrl lr, artMterpAsmInstructionStart + (37 * 128) @ Addr of primary handler. 8235 mov r0, rSELF 8236 add r1, rFP, #OFF_FP_SHADOWFRAME 8237 mov r2, rPC 8238 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8239 8240/* ------------------------------ */ 8241 .balign 128 8242.L_ALT_op_fill_array_data: /* 0x26 */ 8243/* File: arm/alt_stub.S */ 8244/* 8245 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8246 * any interesting requests and then jump to the real instruction 8247 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8248 */ 8249 .extern MterpCheckBefore 8250 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8251 adrl lr, artMterpAsmInstructionStart + (38 * 128) @ Addr of primary handler. 8252 mov r0, rSELF 8253 add r1, rFP, #OFF_FP_SHADOWFRAME 8254 mov r2, rPC 8255 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8256 8257/* ------------------------------ */ 8258 .balign 128 8259.L_ALT_op_throw: /* 0x27 */ 8260/* File: arm/alt_stub.S */ 8261/* 8262 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8263 * any interesting requests and then jump to the real instruction 8264 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8265 */ 8266 .extern MterpCheckBefore 8267 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8268 adrl lr, artMterpAsmInstructionStart + (39 * 128) @ Addr of primary handler. 8269 mov r0, rSELF 8270 add r1, rFP, #OFF_FP_SHADOWFRAME 8271 mov r2, rPC 8272 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8273 8274/* ------------------------------ */ 8275 .balign 128 8276.L_ALT_op_goto: /* 0x28 */ 8277/* File: arm/alt_stub.S */ 8278/* 8279 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8280 * any interesting requests and then jump to the real instruction 8281 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8282 */ 8283 .extern MterpCheckBefore 8284 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8285 adrl lr, artMterpAsmInstructionStart + (40 * 128) @ Addr of primary handler. 8286 mov r0, rSELF 8287 add r1, rFP, #OFF_FP_SHADOWFRAME 8288 mov r2, rPC 8289 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8290 8291/* ------------------------------ */ 8292 .balign 128 8293.L_ALT_op_goto_16: /* 0x29 */ 8294/* File: arm/alt_stub.S */ 8295/* 8296 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8297 * any interesting requests and then jump to the real instruction 8298 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8299 */ 8300 .extern MterpCheckBefore 8301 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8302 adrl lr, artMterpAsmInstructionStart + (41 * 128) @ Addr of primary handler. 8303 mov r0, rSELF 8304 add r1, rFP, #OFF_FP_SHADOWFRAME 8305 mov r2, rPC 8306 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8307 8308/* ------------------------------ */ 8309 .balign 128 8310.L_ALT_op_goto_32: /* 0x2a */ 8311/* File: arm/alt_stub.S */ 8312/* 8313 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8314 * any interesting requests and then jump to the real instruction 8315 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8316 */ 8317 .extern MterpCheckBefore 8318 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8319 adrl lr, artMterpAsmInstructionStart + (42 * 128) @ Addr of primary handler. 8320 mov r0, rSELF 8321 add r1, rFP, #OFF_FP_SHADOWFRAME 8322 mov r2, rPC 8323 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8324 8325/* ------------------------------ */ 8326 .balign 128 8327.L_ALT_op_packed_switch: /* 0x2b */ 8328/* File: arm/alt_stub.S */ 8329/* 8330 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8331 * any interesting requests and then jump to the real instruction 8332 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8333 */ 8334 .extern MterpCheckBefore 8335 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8336 adrl lr, artMterpAsmInstructionStart + (43 * 128) @ Addr of primary handler. 8337 mov r0, rSELF 8338 add r1, rFP, #OFF_FP_SHADOWFRAME 8339 mov r2, rPC 8340 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8341 8342/* ------------------------------ */ 8343 .balign 128 8344.L_ALT_op_sparse_switch: /* 0x2c */ 8345/* File: arm/alt_stub.S */ 8346/* 8347 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8348 * any interesting requests and then jump to the real instruction 8349 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8350 */ 8351 .extern MterpCheckBefore 8352 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8353 adrl lr, artMterpAsmInstructionStart + (44 * 128) @ Addr of primary handler. 8354 mov r0, rSELF 8355 add r1, rFP, #OFF_FP_SHADOWFRAME 8356 mov r2, rPC 8357 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8358 8359/* ------------------------------ */ 8360 .balign 128 8361.L_ALT_op_cmpl_float: /* 0x2d */ 8362/* File: arm/alt_stub.S */ 8363/* 8364 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8365 * any interesting requests and then jump to the real instruction 8366 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8367 */ 8368 .extern MterpCheckBefore 8369 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8370 adrl lr, artMterpAsmInstructionStart + (45 * 128) @ Addr of primary handler. 8371 mov r0, rSELF 8372 add r1, rFP, #OFF_FP_SHADOWFRAME 8373 mov r2, rPC 8374 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8375 8376/* ------------------------------ */ 8377 .balign 128 8378.L_ALT_op_cmpg_float: /* 0x2e */ 8379/* File: arm/alt_stub.S */ 8380/* 8381 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8382 * any interesting requests and then jump to the real instruction 8383 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8384 */ 8385 .extern MterpCheckBefore 8386 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8387 adrl lr, artMterpAsmInstructionStart + (46 * 128) @ Addr of primary handler. 8388 mov r0, rSELF 8389 add r1, rFP, #OFF_FP_SHADOWFRAME 8390 mov r2, rPC 8391 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8392 8393/* ------------------------------ */ 8394 .balign 128 8395.L_ALT_op_cmpl_double: /* 0x2f */ 8396/* File: arm/alt_stub.S */ 8397/* 8398 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8399 * any interesting requests and then jump to the real instruction 8400 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8401 */ 8402 .extern MterpCheckBefore 8403 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8404 adrl lr, artMterpAsmInstructionStart + (47 * 128) @ Addr of primary handler. 8405 mov r0, rSELF 8406 add r1, rFP, #OFF_FP_SHADOWFRAME 8407 mov r2, rPC 8408 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8409 8410/* ------------------------------ */ 8411 .balign 128 8412.L_ALT_op_cmpg_double: /* 0x30 */ 8413/* File: arm/alt_stub.S */ 8414/* 8415 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8416 * any interesting requests and then jump to the real instruction 8417 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8418 */ 8419 .extern MterpCheckBefore 8420 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8421 adrl lr, artMterpAsmInstructionStart + (48 * 128) @ Addr of primary handler. 8422 mov r0, rSELF 8423 add r1, rFP, #OFF_FP_SHADOWFRAME 8424 mov r2, rPC 8425 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8426 8427/* ------------------------------ */ 8428 .balign 128 8429.L_ALT_op_cmp_long: /* 0x31 */ 8430/* File: arm/alt_stub.S */ 8431/* 8432 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8433 * any interesting requests and then jump to the real instruction 8434 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8435 */ 8436 .extern MterpCheckBefore 8437 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8438 adrl lr, artMterpAsmInstructionStart + (49 * 128) @ Addr of primary handler. 8439 mov r0, rSELF 8440 add r1, rFP, #OFF_FP_SHADOWFRAME 8441 mov r2, rPC 8442 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8443 8444/* ------------------------------ */ 8445 .balign 128 8446.L_ALT_op_if_eq: /* 0x32 */ 8447/* File: arm/alt_stub.S */ 8448/* 8449 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8450 * any interesting requests and then jump to the real instruction 8451 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8452 */ 8453 .extern MterpCheckBefore 8454 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8455 adrl lr, artMterpAsmInstructionStart + (50 * 128) @ Addr of primary handler. 8456 mov r0, rSELF 8457 add r1, rFP, #OFF_FP_SHADOWFRAME 8458 mov r2, rPC 8459 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8460 8461/* ------------------------------ */ 8462 .balign 128 8463.L_ALT_op_if_ne: /* 0x33 */ 8464/* File: arm/alt_stub.S */ 8465/* 8466 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8467 * any interesting requests and then jump to the real instruction 8468 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8469 */ 8470 .extern MterpCheckBefore 8471 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8472 adrl lr, artMterpAsmInstructionStart + (51 * 128) @ Addr of primary handler. 8473 mov r0, rSELF 8474 add r1, rFP, #OFF_FP_SHADOWFRAME 8475 mov r2, rPC 8476 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8477 8478/* ------------------------------ */ 8479 .balign 128 8480.L_ALT_op_if_lt: /* 0x34 */ 8481/* File: arm/alt_stub.S */ 8482/* 8483 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8484 * any interesting requests and then jump to the real instruction 8485 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8486 */ 8487 .extern MterpCheckBefore 8488 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8489 adrl lr, artMterpAsmInstructionStart + (52 * 128) @ Addr of primary handler. 8490 mov r0, rSELF 8491 add r1, rFP, #OFF_FP_SHADOWFRAME 8492 mov r2, rPC 8493 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8494 8495/* ------------------------------ */ 8496 .balign 128 8497.L_ALT_op_if_ge: /* 0x35 */ 8498/* File: arm/alt_stub.S */ 8499/* 8500 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8501 * any interesting requests and then jump to the real instruction 8502 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8503 */ 8504 .extern MterpCheckBefore 8505 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8506 adrl lr, artMterpAsmInstructionStart + (53 * 128) @ Addr of primary handler. 8507 mov r0, rSELF 8508 add r1, rFP, #OFF_FP_SHADOWFRAME 8509 mov r2, rPC 8510 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8511 8512/* ------------------------------ */ 8513 .balign 128 8514.L_ALT_op_if_gt: /* 0x36 */ 8515/* File: arm/alt_stub.S */ 8516/* 8517 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8518 * any interesting requests and then jump to the real instruction 8519 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8520 */ 8521 .extern MterpCheckBefore 8522 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8523 adrl lr, artMterpAsmInstructionStart + (54 * 128) @ Addr of primary handler. 8524 mov r0, rSELF 8525 add r1, rFP, #OFF_FP_SHADOWFRAME 8526 mov r2, rPC 8527 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8528 8529/* ------------------------------ */ 8530 .balign 128 8531.L_ALT_op_if_le: /* 0x37 */ 8532/* File: arm/alt_stub.S */ 8533/* 8534 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8535 * any interesting requests and then jump to the real instruction 8536 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8537 */ 8538 .extern MterpCheckBefore 8539 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8540 adrl lr, artMterpAsmInstructionStart + (55 * 128) @ Addr of primary handler. 8541 mov r0, rSELF 8542 add r1, rFP, #OFF_FP_SHADOWFRAME 8543 mov r2, rPC 8544 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8545 8546/* ------------------------------ */ 8547 .balign 128 8548.L_ALT_op_if_eqz: /* 0x38 */ 8549/* File: arm/alt_stub.S */ 8550/* 8551 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8552 * any interesting requests and then jump to the real instruction 8553 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8554 */ 8555 .extern MterpCheckBefore 8556 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8557 adrl lr, artMterpAsmInstructionStart + (56 * 128) @ Addr of primary handler. 8558 mov r0, rSELF 8559 add r1, rFP, #OFF_FP_SHADOWFRAME 8560 mov r2, rPC 8561 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8562 8563/* ------------------------------ */ 8564 .balign 128 8565.L_ALT_op_if_nez: /* 0x39 */ 8566/* File: arm/alt_stub.S */ 8567/* 8568 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8569 * any interesting requests and then jump to the real instruction 8570 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8571 */ 8572 .extern MterpCheckBefore 8573 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8574 adrl lr, artMterpAsmInstructionStart + (57 * 128) @ Addr of primary handler. 8575 mov r0, rSELF 8576 add r1, rFP, #OFF_FP_SHADOWFRAME 8577 mov r2, rPC 8578 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8579 8580/* ------------------------------ */ 8581 .balign 128 8582.L_ALT_op_if_ltz: /* 0x3a */ 8583/* File: arm/alt_stub.S */ 8584/* 8585 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8586 * any interesting requests and then jump to the real instruction 8587 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8588 */ 8589 .extern MterpCheckBefore 8590 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8591 adrl lr, artMterpAsmInstructionStart + (58 * 128) @ Addr of primary handler. 8592 mov r0, rSELF 8593 add r1, rFP, #OFF_FP_SHADOWFRAME 8594 mov r2, rPC 8595 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8596 8597/* ------------------------------ */ 8598 .balign 128 8599.L_ALT_op_if_gez: /* 0x3b */ 8600/* File: arm/alt_stub.S */ 8601/* 8602 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8603 * any interesting requests and then jump to the real instruction 8604 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8605 */ 8606 .extern MterpCheckBefore 8607 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8608 adrl lr, artMterpAsmInstructionStart + (59 * 128) @ Addr of primary handler. 8609 mov r0, rSELF 8610 add r1, rFP, #OFF_FP_SHADOWFRAME 8611 mov r2, rPC 8612 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8613 8614/* ------------------------------ */ 8615 .balign 128 8616.L_ALT_op_if_gtz: /* 0x3c */ 8617/* File: arm/alt_stub.S */ 8618/* 8619 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8620 * any interesting requests and then jump to the real instruction 8621 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8622 */ 8623 .extern MterpCheckBefore 8624 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8625 adrl lr, artMterpAsmInstructionStart + (60 * 128) @ Addr of primary handler. 8626 mov r0, rSELF 8627 add r1, rFP, #OFF_FP_SHADOWFRAME 8628 mov r2, rPC 8629 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8630 8631/* ------------------------------ */ 8632 .balign 128 8633.L_ALT_op_if_lez: /* 0x3d */ 8634/* File: arm/alt_stub.S */ 8635/* 8636 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8637 * any interesting requests and then jump to the real instruction 8638 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8639 */ 8640 .extern MterpCheckBefore 8641 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8642 adrl lr, artMterpAsmInstructionStart + (61 * 128) @ Addr of primary handler. 8643 mov r0, rSELF 8644 add r1, rFP, #OFF_FP_SHADOWFRAME 8645 mov r2, rPC 8646 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8647 8648/* ------------------------------ */ 8649 .balign 128 8650.L_ALT_op_unused_3e: /* 0x3e */ 8651/* File: arm/alt_stub.S */ 8652/* 8653 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8654 * any interesting requests and then jump to the real instruction 8655 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8656 */ 8657 .extern MterpCheckBefore 8658 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8659 adrl lr, artMterpAsmInstructionStart + (62 * 128) @ Addr of primary handler. 8660 mov r0, rSELF 8661 add r1, rFP, #OFF_FP_SHADOWFRAME 8662 mov r2, rPC 8663 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8664 8665/* ------------------------------ */ 8666 .balign 128 8667.L_ALT_op_unused_3f: /* 0x3f */ 8668/* File: arm/alt_stub.S */ 8669/* 8670 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8671 * any interesting requests and then jump to the real instruction 8672 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8673 */ 8674 .extern MterpCheckBefore 8675 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8676 adrl lr, artMterpAsmInstructionStart + (63 * 128) @ Addr of primary handler. 8677 mov r0, rSELF 8678 add r1, rFP, #OFF_FP_SHADOWFRAME 8679 mov r2, rPC 8680 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8681 8682/* ------------------------------ */ 8683 .balign 128 8684.L_ALT_op_unused_40: /* 0x40 */ 8685/* File: arm/alt_stub.S */ 8686/* 8687 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8688 * any interesting requests and then jump to the real instruction 8689 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8690 */ 8691 .extern MterpCheckBefore 8692 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8693 adrl lr, artMterpAsmInstructionStart + (64 * 128) @ Addr of primary handler. 8694 mov r0, rSELF 8695 add r1, rFP, #OFF_FP_SHADOWFRAME 8696 mov r2, rPC 8697 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8698 8699/* ------------------------------ */ 8700 .balign 128 8701.L_ALT_op_unused_41: /* 0x41 */ 8702/* File: arm/alt_stub.S */ 8703/* 8704 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8705 * any interesting requests and then jump to the real instruction 8706 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8707 */ 8708 .extern MterpCheckBefore 8709 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8710 adrl lr, artMterpAsmInstructionStart + (65 * 128) @ Addr of primary handler. 8711 mov r0, rSELF 8712 add r1, rFP, #OFF_FP_SHADOWFRAME 8713 mov r2, rPC 8714 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8715 8716/* ------------------------------ */ 8717 .balign 128 8718.L_ALT_op_unused_42: /* 0x42 */ 8719/* File: arm/alt_stub.S */ 8720/* 8721 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8722 * any interesting requests and then jump to the real instruction 8723 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8724 */ 8725 .extern MterpCheckBefore 8726 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8727 adrl lr, artMterpAsmInstructionStart + (66 * 128) @ Addr of primary handler. 8728 mov r0, rSELF 8729 add r1, rFP, #OFF_FP_SHADOWFRAME 8730 mov r2, rPC 8731 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8732 8733/* ------------------------------ */ 8734 .balign 128 8735.L_ALT_op_unused_43: /* 0x43 */ 8736/* File: arm/alt_stub.S */ 8737/* 8738 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8739 * any interesting requests and then jump to the real instruction 8740 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8741 */ 8742 .extern MterpCheckBefore 8743 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8744 adrl lr, artMterpAsmInstructionStart + (67 * 128) @ Addr of primary handler. 8745 mov r0, rSELF 8746 add r1, rFP, #OFF_FP_SHADOWFRAME 8747 mov r2, rPC 8748 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8749 8750/* ------------------------------ */ 8751 .balign 128 8752.L_ALT_op_aget: /* 0x44 */ 8753/* File: arm/alt_stub.S */ 8754/* 8755 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8756 * any interesting requests and then jump to the real instruction 8757 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8758 */ 8759 .extern MterpCheckBefore 8760 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8761 adrl lr, artMterpAsmInstructionStart + (68 * 128) @ Addr of primary handler. 8762 mov r0, rSELF 8763 add r1, rFP, #OFF_FP_SHADOWFRAME 8764 mov r2, rPC 8765 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8766 8767/* ------------------------------ */ 8768 .balign 128 8769.L_ALT_op_aget_wide: /* 0x45 */ 8770/* File: arm/alt_stub.S */ 8771/* 8772 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8773 * any interesting requests and then jump to the real instruction 8774 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8775 */ 8776 .extern MterpCheckBefore 8777 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8778 adrl lr, artMterpAsmInstructionStart + (69 * 128) @ Addr of primary handler. 8779 mov r0, rSELF 8780 add r1, rFP, #OFF_FP_SHADOWFRAME 8781 mov r2, rPC 8782 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8783 8784/* ------------------------------ */ 8785 .balign 128 8786.L_ALT_op_aget_object: /* 0x46 */ 8787/* File: arm/alt_stub.S */ 8788/* 8789 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8790 * any interesting requests and then jump to the real instruction 8791 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8792 */ 8793 .extern MterpCheckBefore 8794 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8795 adrl lr, artMterpAsmInstructionStart + (70 * 128) @ Addr of primary handler. 8796 mov r0, rSELF 8797 add r1, rFP, #OFF_FP_SHADOWFRAME 8798 mov r2, rPC 8799 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8800 8801/* ------------------------------ */ 8802 .balign 128 8803.L_ALT_op_aget_boolean: /* 0x47 */ 8804/* File: arm/alt_stub.S */ 8805/* 8806 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8807 * any interesting requests and then jump to the real instruction 8808 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8809 */ 8810 .extern MterpCheckBefore 8811 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8812 adrl lr, artMterpAsmInstructionStart + (71 * 128) @ Addr of primary handler. 8813 mov r0, rSELF 8814 add r1, rFP, #OFF_FP_SHADOWFRAME 8815 mov r2, rPC 8816 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8817 8818/* ------------------------------ */ 8819 .balign 128 8820.L_ALT_op_aget_byte: /* 0x48 */ 8821/* File: arm/alt_stub.S */ 8822/* 8823 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8824 * any interesting requests and then jump to the real instruction 8825 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8826 */ 8827 .extern MterpCheckBefore 8828 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8829 adrl lr, artMterpAsmInstructionStart + (72 * 128) @ Addr of primary handler. 8830 mov r0, rSELF 8831 add r1, rFP, #OFF_FP_SHADOWFRAME 8832 mov r2, rPC 8833 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8834 8835/* ------------------------------ */ 8836 .balign 128 8837.L_ALT_op_aget_char: /* 0x49 */ 8838/* File: arm/alt_stub.S */ 8839/* 8840 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8841 * any interesting requests and then jump to the real instruction 8842 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8843 */ 8844 .extern MterpCheckBefore 8845 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8846 adrl lr, artMterpAsmInstructionStart + (73 * 128) @ Addr of primary handler. 8847 mov r0, rSELF 8848 add r1, rFP, #OFF_FP_SHADOWFRAME 8849 mov r2, rPC 8850 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8851 8852/* ------------------------------ */ 8853 .balign 128 8854.L_ALT_op_aget_short: /* 0x4a */ 8855/* File: arm/alt_stub.S */ 8856/* 8857 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8858 * any interesting requests and then jump to the real instruction 8859 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8860 */ 8861 .extern MterpCheckBefore 8862 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8863 adrl lr, artMterpAsmInstructionStart + (74 * 128) @ Addr of primary handler. 8864 mov r0, rSELF 8865 add r1, rFP, #OFF_FP_SHADOWFRAME 8866 mov r2, rPC 8867 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8868 8869/* ------------------------------ */ 8870 .balign 128 8871.L_ALT_op_aput: /* 0x4b */ 8872/* File: arm/alt_stub.S */ 8873/* 8874 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8875 * any interesting requests and then jump to the real instruction 8876 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8877 */ 8878 .extern MterpCheckBefore 8879 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8880 adrl lr, artMterpAsmInstructionStart + (75 * 128) @ Addr of primary handler. 8881 mov r0, rSELF 8882 add r1, rFP, #OFF_FP_SHADOWFRAME 8883 mov r2, rPC 8884 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8885 8886/* ------------------------------ */ 8887 .balign 128 8888.L_ALT_op_aput_wide: /* 0x4c */ 8889/* File: arm/alt_stub.S */ 8890/* 8891 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8892 * any interesting requests and then jump to the real instruction 8893 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8894 */ 8895 .extern MterpCheckBefore 8896 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8897 adrl lr, artMterpAsmInstructionStart + (76 * 128) @ Addr of primary handler. 8898 mov r0, rSELF 8899 add r1, rFP, #OFF_FP_SHADOWFRAME 8900 mov r2, rPC 8901 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8902 8903/* ------------------------------ */ 8904 .balign 128 8905.L_ALT_op_aput_object: /* 0x4d */ 8906/* File: arm/alt_stub.S */ 8907/* 8908 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8909 * any interesting requests and then jump to the real instruction 8910 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8911 */ 8912 .extern MterpCheckBefore 8913 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8914 adrl lr, artMterpAsmInstructionStart + (77 * 128) @ Addr of primary handler. 8915 mov r0, rSELF 8916 add r1, rFP, #OFF_FP_SHADOWFRAME 8917 mov r2, rPC 8918 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8919 8920/* ------------------------------ */ 8921 .balign 128 8922.L_ALT_op_aput_boolean: /* 0x4e */ 8923/* File: arm/alt_stub.S */ 8924/* 8925 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8926 * any interesting requests and then jump to the real instruction 8927 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8928 */ 8929 .extern MterpCheckBefore 8930 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8931 adrl lr, artMterpAsmInstructionStart + (78 * 128) @ Addr of primary handler. 8932 mov r0, rSELF 8933 add r1, rFP, #OFF_FP_SHADOWFRAME 8934 mov r2, rPC 8935 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8936 8937/* ------------------------------ */ 8938 .balign 128 8939.L_ALT_op_aput_byte: /* 0x4f */ 8940/* File: arm/alt_stub.S */ 8941/* 8942 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8943 * any interesting requests and then jump to the real instruction 8944 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8945 */ 8946 .extern MterpCheckBefore 8947 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8948 adrl lr, artMterpAsmInstructionStart + (79 * 128) @ Addr of primary handler. 8949 mov r0, rSELF 8950 add r1, rFP, #OFF_FP_SHADOWFRAME 8951 mov r2, rPC 8952 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8953 8954/* ------------------------------ */ 8955 .balign 128 8956.L_ALT_op_aput_char: /* 0x50 */ 8957/* File: arm/alt_stub.S */ 8958/* 8959 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8960 * any interesting requests and then jump to the real instruction 8961 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8962 */ 8963 .extern MterpCheckBefore 8964 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8965 adrl lr, artMterpAsmInstructionStart + (80 * 128) @ Addr of primary handler. 8966 mov r0, rSELF 8967 add r1, rFP, #OFF_FP_SHADOWFRAME 8968 mov r2, rPC 8969 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8970 8971/* ------------------------------ */ 8972 .balign 128 8973.L_ALT_op_aput_short: /* 0x51 */ 8974/* File: arm/alt_stub.S */ 8975/* 8976 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8977 * any interesting requests and then jump to the real instruction 8978 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8979 */ 8980 .extern MterpCheckBefore 8981 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8982 adrl lr, artMterpAsmInstructionStart + (81 * 128) @ Addr of primary handler. 8983 mov r0, rSELF 8984 add r1, rFP, #OFF_FP_SHADOWFRAME 8985 mov r2, rPC 8986 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8987 8988/* ------------------------------ */ 8989 .balign 128 8990.L_ALT_op_iget: /* 0x52 */ 8991/* File: arm/alt_stub.S */ 8992/* 8993 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8994 * any interesting requests and then jump to the real instruction 8995 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8996 */ 8997 .extern MterpCheckBefore 8998 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8999 adrl lr, artMterpAsmInstructionStart + (82 * 128) @ Addr of primary handler. 9000 mov r0, rSELF 9001 add r1, rFP, #OFF_FP_SHADOWFRAME 9002 mov r2, rPC 9003 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9004 9005/* ------------------------------ */ 9006 .balign 128 9007.L_ALT_op_iget_wide: /* 0x53 */ 9008/* File: arm/alt_stub.S */ 9009/* 9010 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9011 * any interesting requests and then jump to the real instruction 9012 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9013 */ 9014 .extern MterpCheckBefore 9015 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9016 adrl lr, artMterpAsmInstructionStart + (83 * 128) @ Addr of primary handler. 9017 mov r0, rSELF 9018 add r1, rFP, #OFF_FP_SHADOWFRAME 9019 mov r2, rPC 9020 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9021 9022/* ------------------------------ */ 9023 .balign 128 9024.L_ALT_op_iget_object: /* 0x54 */ 9025/* File: arm/alt_stub.S */ 9026/* 9027 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9028 * any interesting requests and then jump to the real instruction 9029 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9030 */ 9031 .extern MterpCheckBefore 9032 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9033 adrl lr, artMterpAsmInstructionStart + (84 * 128) @ Addr of primary handler. 9034 mov r0, rSELF 9035 add r1, rFP, #OFF_FP_SHADOWFRAME 9036 mov r2, rPC 9037 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9038 9039/* ------------------------------ */ 9040 .balign 128 9041.L_ALT_op_iget_boolean: /* 0x55 */ 9042/* File: arm/alt_stub.S */ 9043/* 9044 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9045 * any interesting requests and then jump to the real instruction 9046 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9047 */ 9048 .extern MterpCheckBefore 9049 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9050 adrl lr, artMterpAsmInstructionStart + (85 * 128) @ Addr of primary handler. 9051 mov r0, rSELF 9052 add r1, rFP, #OFF_FP_SHADOWFRAME 9053 mov r2, rPC 9054 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9055 9056/* ------------------------------ */ 9057 .balign 128 9058.L_ALT_op_iget_byte: /* 0x56 */ 9059/* File: arm/alt_stub.S */ 9060/* 9061 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9062 * any interesting requests and then jump to the real instruction 9063 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9064 */ 9065 .extern MterpCheckBefore 9066 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9067 adrl lr, artMterpAsmInstructionStart + (86 * 128) @ Addr of primary handler. 9068 mov r0, rSELF 9069 add r1, rFP, #OFF_FP_SHADOWFRAME 9070 mov r2, rPC 9071 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9072 9073/* ------------------------------ */ 9074 .balign 128 9075.L_ALT_op_iget_char: /* 0x57 */ 9076/* File: arm/alt_stub.S */ 9077/* 9078 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9079 * any interesting requests and then jump to the real instruction 9080 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9081 */ 9082 .extern MterpCheckBefore 9083 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9084 adrl lr, artMterpAsmInstructionStart + (87 * 128) @ Addr of primary handler. 9085 mov r0, rSELF 9086 add r1, rFP, #OFF_FP_SHADOWFRAME 9087 mov r2, rPC 9088 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9089 9090/* ------------------------------ */ 9091 .balign 128 9092.L_ALT_op_iget_short: /* 0x58 */ 9093/* File: arm/alt_stub.S */ 9094/* 9095 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9096 * any interesting requests and then jump to the real instruction 9097 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9098 */ 9099 .extern MterpCheckBefore 9100 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9101 adrl lr, artMterpAsmInstructionStart + (88 * 128) @ Addr of primary handler. 9102 mov r0, rSELF 9103 add r1, rFP, #OFF_FP_SHADOWFRAME 9104 mov r2, rPC 9105 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9106 9107/* ------------------------------ */ 9108 .balign 128 9109.L_ALT_op_iput: /* 0x59 */ 9110/* File: arm/alt_stub.S */ 9111/* 9112 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9113 * any interesting requests and then jump to the real instruction 9114 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9115 */ 9116 .extern MterpCheckBefore 9117 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9118 adrl lr, artMterpAsmInstructionStart + (89 * 128) @ Addr of primary handler. 9119 mov r0, rSELF 9120 add r1, rFP, #OFF_FP_SHADOWFRAME 9121 mov r2, rPC 9122 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9123 9124/* ------------------------------ */ 9125 .balign 128 9126.L_ALT_op_iput_wide: /* 0x5a */ 9127/* File: arm/alt_stub.S */ 9128/* 9129 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9130 * any interesting requests and then jump to the real instruction 9131 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9132 */ 9133 .extern MterpCheckBefore 9134 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9135 adrl lr, artMterpAsmInstructionStart + (90 * 128) @ Addr of primary handler. 9136 mov r0, rSELF 9137 add r1, rFP, #OFF_FP_SHADOWFRAME 9138 mov r2, rPC 9139 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9140 9141/* ------------------------------ */ 9142 .balign 128 9143.L_ALT_op_iput_object: /* 0x5b */ 9144/* File: arm/alt_stub.S */ 9145/* 9146 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9147 * any interesting requests and then jump to the real instruction 9148 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9149 */ 9150 .extern MterpCheckBefore 9151 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9152 adrl lr, artMterpAsmInstructionStart + (91 * 128) @ Addr of primary handler. 9153 mov r0, rSELF 9154 add r1, rFP, #OFF_FP_SHADOWFRAME 9155 mov r2, rPC 9156 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9157 9158/* ------------------------------ */ 9159 .balign 128 9160.L_ALT_op_iput_boolean: /* 0x5c */ 9161/* File: arm/alt_stub.S */ 9162/* 9163 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9164 * any interesting requests and then jump to the real instruction 9165 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9166 */ 9167 .extern MterpCheckBefore 9168 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9169 adrl lr, artMterpAsmInstructionStart + (92 * 128) @ Addr of primary handler. 9170 mov r0, rSELF 9171 add r1, rFP, #OFF_FP_SHADOWFRAME 9172 mov r2, rPC 9173 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9174 9175/* ------------------------------ */ 9176 .balign 128 9177.L_ALT_op_iput_byte: /* 0x5d */ 9178/* File: arm/alt_stub.S */ 9179/* 9180 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9181 * any interesting requests and then jump to the real instruction 9182 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9183 */ 9184 .extern MterpCheckBefore 9185 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9186 adrl lr, artMterpAsmInstructionStart + (93 * 128) @ Addr of primary handler. 9187 mov r0, rSELF 9188 add r1, rFP, #OFF_FP_SHADOWFRAME 9189 mov r2, rPC 9190 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9191 9192/* ------------------------------ */ 9193 .balign 128 9194.L_ALT_op_iput_char: /* 0x5e */ 9195/* File: arm/alt_stub.S */ 9196/* 9197 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9198 * any interesting requests and then jump to the real instruction 9199 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9200 */ 9201 .extern MterpCheckBefore 9202 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9203 adrl lr, artMterpAsmInstructionStart + (94 * 128) @ Addr of primary handler. 9204 mov r0, rSELF 9205 add r1, rFP, #OFF_FP_SHADOWFRAME 9206 mov r2, rPC 9207 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9208 9209/* ------------------------------ */ 9210 .balign 128 9211.L_ALT_op_iput_short: /* 0x5f */ 9212/* File: arm/alt_stub.S */ 9213/* 9214 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9215 * any interesting requests and then jump to the real instruction 9216 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9217 */ 9218 .extern MterpCheckBefore 9219 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9220 adrl lr, artMterpAsmInstructionStart + (95 * 128) @ Addr of primary handler. 9221 mov r0, rSELF 9222 add r1, rFP, #OFF_FP_SHADOWFRAME 9223 mov r2, rPC 9224 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9225 9226/* ------------------------------ */ 9227 .balign 128 9228.L_ALT_op_sget: /* 0x60 */ 9229/* File: arm/alt_stub.S */ 9230/* 9231 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9232 * any interesting requests and then jump to the real instruction 9233 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9234 */ 9235 .extern MterpCheckBefore 9236 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9237 adrl lr, artMterpAsmInstructionStart + (96 * 128) @ Addr of primary handler. 9238 mov r0, rSELF 9239 add r1, rFP, #OFF_FP_SHADOWFRAME 9240 mov r2, rPC 9241 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9242 9243/* ------------------------------ */ 9244 .balign 128 9245.L_ALT_op_sget_wide: /* 0x61 */ 9246/* File: arm/alt_stub.S */ 9247/* 9248 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9249 * any interesting requests and then jump to the real instruction 9250 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9251 */ 9252 .extern MterpCheckBefore 9253 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9254 adrl lr, artMterpAsmInstructionStart + (97 * 128) @ Addr of primary handler. 9255 mov r0, rSELF 9256 add r1, rFP, #OFF_FP_SHADOWFRAME 9257 mov r2, rPC 9258 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9259 9260/* ------------------------------ */ 9261 .balign 128 9262.L_ALT_op_sget_object: /* 0x62 */ 9263/* File: arm/alt_stub.S */ 9264/* 9265 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9266 * any interesting requests and then jump to the real instruction 9267 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9268 */ 9269 .extern MterpCheckBefore 9270 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9271 adrl lr, artMterpAsmInstructionStart + (98 * 128) @ Addr of primary handler. 9272 mov r0, rSELF 9273 add r1, rFP, #OFF_FP_SHADOWFRAME 9274 mov r2, rPC 9275 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9276 9277/* ------------------------------ */ 9278 .balign 128 9279.L_ALT_op_sget_boolean: /* 0x63 */ 9280/* File: arm/alt_stub.S */ 9281/* 9282 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9283 * any interesting requests and then jump to the real instruction 9284 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9285 */ 9286 .extern MterpCheckBefore 9287 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9288 adrl lr, artMterpAsmInstructionStart + (99 * 128) @ Addr of primary handler. 9289 mov r0, rSELF 9290 add r1, rFP, #OFF_FP_SHADOWFRAME 9291 mov r2, rPC 9292 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9293 9294/* ------------------------------ */ 9295 .balign 128 9296.L_ALT_op_sget_byte: /* 0x64 */ 9297/* File: arm/alt_stub.S */ 9298/* 9299 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9300 * any interesting requests and then jump to the real instruction 9301 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9302 */ 9303 .extern MterpCheckBefore 9304 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9305 adrl lr, artMterpAsmInstructionStart + (100 * 128) @ Addr of primary handler. 9306 mov r0, rSELF 9307 add r1, rFP, #OFF_FP_SHADOWFRAME 9308 mov r2, rPC 9309 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9310 9311/* ------------------------------ */ 9312 .balign 128 9313.L_ALT_op_sget_char: /* 0x65 */ 9314/* File: arm/alt_stub.S */ 9315/* 9316 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9317 * any interesting requests and then jump to the real instruction 9318 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9319 */ 9320 .extern MterpCheckBefore 9321 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9322 adrl lr, artMterpAsmInstructionStart + (101 * 128) @ Addr of primary handler. 9323 mov r0, rSELF 9324 add r1, rFP, #OFF_FP_SHADOWFRAME 9325 mov r2, rPC 9326 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9327 9328/* ------------------------------ */ 9329 .balign 128 9330.L_ALT_op_sget_short: /* 0x66 */ 9331/* File: arm/alt_stub.S */ 9332/* 9333 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9334 * any interesting requests and then jump to the real instruction 9335 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9336 */ 9337 .extern MterpCheckBefore 9338 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9339 adrl lr, artMterpAsmInstructionStart + (102 * 128) @ Addr of primary handler. 9340 mov r0, rSELF 9341 add r1, rFP, #OFF_FP_SHADOWFRAME 9342 mov r2, rPC 9343 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9344 9345/* ------------------------------ */ 9346 .balign 128 9347.L_ALT_op_sput: /* 0x67 */ 9348/* File: arm/alt_stub.S */ 9349/* 9350 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9351 * any interesting requests and then jump to the real instruction 9352 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9353 */ 9354 .extern MterpCheckBefore 9355 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9356 adrl lr, artMterpAsmInstructionStart + (103 * 128) @ Addr of primary handler. 9357 mov r0, rSELF 9358 add r1, rFP, #OFF_FP_SHADOWFRAME 9359 mov r2, rPC 9360 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9361 9362/* ------------------------------ */ 9363 .balign 128 9364.L_ALT_op_sput_wide: /* 0x68 */ 9365/* File: arm/alt_stub.S */ 9366/* 9367 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9368 * any interesting requests and then jump to the real instruction 9369 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9370 */ 9371 .extern MterpCheckBefore 9372 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9373 adrl lr, artMterpAsmInstructionStart + (104 * 128) @ Addr of primary handler. 9374 mov r0, rSELF 9375 add r1, rFP, #OFF_FP_SHADOWFRAME 9376 mov r2, rPC 9377 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9378 9379/* ------------------------------ */ 9380 .balign 128 9381.L_ALT_op_sput_object: /* 0x69 */ 9382/* File: arm/alt_stub.S */ 9383/* 9384 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9385 * any interesting requests and then jump to the real instruction 9386 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9387 */ 9388 .extern MterpCheckBefore 9389 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9390 adrl lr, artMterpAsmInstructionStart + (105 * 128) @ Addr of primary handler. 9391 mov r0, rSELF 9392 add r1, rFP, #OFF_FP_SHADOWFRAME 9393 mov r2, rPC 9394 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9395 9396/* ------------------------------ */ 9397 .balign 128 9398.L_ALT_op_sput_boolean: /* 0x6a */ 9399/* File: arm/alt_stub.S */ 9400/* 9401 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9402 * any interesting requests and then jump to the real instruction 9403 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9404 */ 9405 .extern MterpCheckBefore 9406 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9407 adrl lr, artMterpAsmInstructionStart + (106 * 128) @ Addr of primary handler. 9408 mov r0, rSELF 9409 add r1, rFP, #OFF_FP_SHADOWFRAME 9410 mov r2, rPC 9411 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9412 9413/* ------------------------------ */ 9414 .balign 128 9415.L_ALT_op_sput_byte: /* 0x6b */ 9416/* File: arm/alt_stub.S */ 9417/* 9418 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9419 * any interesting requests and then jump to the real instruction 9420 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9421 */ 9422 .extern MterpCheckBefore 9423 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9424 adrl lr, artMterpAsmInstructionStart + (107 * 128) @ Addr of primary handler. 9425 mov r0, rSELF 9426 add r1, rFP, #OFF_FP_SHADOWFRAME 9427 mov r2, rPC 9428 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9429 9430/* ------------------------------ */ 9431 .balign 128 9432.L_ALT_op_sput_char: /* 0x6c */ 9433/* File: arm/alt_stub.S */ 9434/* 9435 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9436 * any interesting requests and then jump to the real instruction 9437 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9438 */ 9439 .extern MterpCheckBefore 9440 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9441 adrl lr, artMterpAsmInstructionStart + (108 * 128) @ Addr of primary handler. 9442 mov r0, rSELF 9443 add r1, rFP, #OFF_FP_SHADOWFRAME 9444 mov r2, rPC 9445 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9446 9447/* ------------------------------ */ 9448 .balign 128 9449.L_ALT_op_sput_short: /* 0x6d */ 9450/* File: arm/alt_stub.S */ 9451/* 9452 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9453 * any interesting requests and then jump to the real instruction 9454 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9455 */ 9456 .extern MterpCheckBefore 9457 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9458 adrl lr, artMterpAsmInstructionStart + (109 * 128) @ Addr of primary handler. 9459 mov r0, rSELF 9460 add r1, rFP, #OFF_FP_SHADOWFRAME 9461 mov r2, rPC 9462 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9463 9464/* ------------------------------ */ 9465 .balign 128 9466.L_ALT_op_invoke_virtual: /* 0x6e */ 9467/* File: arm/alt_stub.S */ 9468/* 9469 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9470 * any interesting requests and then jump to the real instruction 9471 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9472 */ 9473 .extern MterpCheckBefore 9474 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9475 adrl lr, artMterpAsmInstructionStart + (110 * 128) @ Addr of primary handler. 9476 mov r0, rSELF 9477 add r1, rFP, #OFF_FP_SHADOWFRAME 9478 mov r2, rPC 9479 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9480 9481/* ------------------------------ */ 9482 .balign 128 9483.L_ALT_op_invoke_super: /* 0x6f */ 9484/* File: arm/alt_stub.S */ 9485/* 9486 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9487 * any interesting requests and then jump to the real instruction 9488 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9489 */ 9490 .extern MterpCheckBefore 9491 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9492 adrl lr, artMterpAsmInstructionStart + (111 * 128) @ Addr of primary handler. 9493 mov r0, rSELF 9494 add r1, rFP, #OFF_FP_SHADOWFRAME 9495 mov r2, rPC 9496 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9497 9498/* ------------------------------ */ 9499 .balign 128 9500.L_ALT_op_invoke_direct: /* 0x70 */ 9501/* File: arm/alt_stub.S */ 9502/* 9503 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9504 * any interesting requests and then jump to the real instruction 9505 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9506 */ 9507 .extern MterpCheckBefore 9508 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9509 adrl lr, artMterpAsmInstructionStart + (112 * 128) @ Addr of primary handler. 9510 mov r0, rSELF 9511 add r1, rFP, #OFF_FP_SHADOWFRAME 9512 mov r2, rPC 9513 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9514 9515/* ------------------------------ */ 9516 .balign 128 9517.L_ALT_op_invoke_static: /* 0x71 */ 9518/* File: arm/alt_stub.S */ 9519/* 9520 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9521 * any interesting requests and then jump to the real instruction 9522 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9523 */ 9524 .extern MterpCheckBefore 9525 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9526 adrl lr, artMterpAsmInstructionStart + (113 * 128) @ Addr of primary handler. 9527 mov r0, rSELF 9528 add r1, rFP, #OFF_FP_SHADOWFRAME 9529 mov r2, rPC 9530 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9531 9532/* ------------------------------ */ 9533 .balign 128 9534.L_ALT_op_invoke_interface: /* 0x72 */ 9535/* File: arm/alt_stub.S */ 9536/* 9537 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9538 * any interesting requests and then jump to the real instruction 9539 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9540 */ 9541 .extern MterpCheckBefore 9542 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9543 adrl lr, artMterpAsmInstructionStart + (114 * 128) @ Addr of primary handler. 9544 mov r0, rSELF 9545 add r1, rFP, #OFF_FP_SHADOWFRAME 9546 mov r2, rPC 9547 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9548 9549/* ------------------------------ */ 9550 .balign 128 9551.L_ALT_op_return_void_no_barrier: /* 0x73 */ 9552/* File: arm/alt_stub.S */ 9553/* 9554 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9555 * any interesting requests and then jump to the real instruction 9556 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9557 */ 9558 .extern MterpCheckBefore 9559 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9560 adrl lr, artMterpAsmInstructionStart + (115 * 128) @ Addr of primary handler. 9561 mov r0, rSELF 9562 add r1, rFP, #OFF_FP_SHADOWFRAME 9563 mov r2, rPC 9564 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9565 9566/* ------------------------------ */ 9567 .balign 128 9568.L_ALT_op_invoke_virtual_range: /* 0x74 */ 9569/* File: arm/alt_stub.S */ 9570/* 9571 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9572 * any interesting requests and then jump to the real instruction 9573 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9574 */ 9575 .extern MterpCheckBefore 9576 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9577 adrl lr, artMterpAsmInstructionStart + (116 * 128) @ Addr of primary handler. 9578 mov r0, rSELF 9579 add r1, rFP, #OFF_FP_SHADOWFRAME 9580 mov r2, rPC 9581 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9582 9583/* ------------------------------ */ 9584 .balign 128 9585.L_ALT_op_invoke_super_range: /* 0x75 */ 9586/* File: arm/alt_stub.S */ 9587/* 9588 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9589 * any interesting requests and then jump to the real instruction 9590 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9591 */ 9592 .extern MterpCheckBefore 9593 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9594 adrl lr, artMterpAsmInstructionStart + (117 * 128) @ Addr of primary handler. 9595 mov r0, rSELF 9596 add r1, rFP, #OFF_FP_SHADOWFRAME 9597 mov r2, rPC 9598 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9599 9600/* ------------------------------ */ 9601 .balign 128 9602.L_ALT_op_invoke_direct_range: /* 0x76 */ 9603/* File: arm/alt_stub.S */ 9604/* 9605 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9606 * any interesting requests and then jump to the real instruction 9607 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9608 */ 9609 .extern MterpCheckBefore 9610 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9611 adrl lr, artMterpAsmInstructionStart + (118 * 128) @ Addr of primary handler. 9612 mov r0, rSELF 9613 add r1, rFP, #OFF_FP_SHADOWFRAME 9614 mov r2, rPC 9615 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9616 9617/* ------------------------------ */ 9618 .balign 128 9619.L_ALT_op_invoke_static_range: /* 0x77 */ 9620/* File: arm/alt_stub.S */ 9621/* 9622 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9623 * any interesting requests and then jump to the real instruction 9624 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9625 */ 9626 .extern MterpCheckBefore 9627 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9628 adrl lr, artMterpAsmInstructionStart + (119 * 128) @ Addr of primary handler. 9629 mov r0, rSELF 9630 add r1, rFP, #OFF_FP_SHADOWFRAME 9631 mov r2, rPC 9632 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9633 9634/* ------------------------------ */ 9635 .balign 128 9636.L_ALT_op_invoke_interface_range: /* 0x78 */ 9637/* File: arm/alt_stub.S */ 9638/* 9639 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9640 * any interesting requests and then jump to the real instruction 9641 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9642 */ 9643 .extern MterpCheckBefore 9644 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9645 adrl lr, artMterpAsmInstructionStart + (120 * 128) @ Addr of primary handler. 9646 mov r0, rSELF 9647 add r1, rFP, #OFF_FP_SHADOWFRAME 9648 mov r2, rPC 9649 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9650 9651/* ------------------------------ */ 9652 .balign 128 9653.L_ALT_op_unused_79: /* 0x79 */ 9654/* File: arm/alt_stub.S */ 9655/* 9656 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9657 * any interesting requests and then jump to the real instruction 9658 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9659 */ 9660 .extern MterpCheckBefore 9661 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9662 adrl lr, artMterpAsmInstructionStart + (121 * 128) @ Addr of primary handler. 9663 mov r0, rSELF 9664 add r1, rFP, #OFF_FP_SHADOWFRAME 9665 mov r2, rPC 9666 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9667 9668/* ------------------------------ */ 9669 .balign 128 9670.L_ALT_op_unused_7a: /* 0x7a */ 9671/* File: arm/alt_stub.S */ 9672/* 9673 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9674 * any interesting requests and then jump to the real instruction 9675 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9676 */ 9677 .extern MterpCheckBefore 9678 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9679 adrl lr, artMterpAsmInstructionStart + (122 * 128) @ Addr of primary handler. 9680 mov r0, rSELF 9681 add r1, rFP, #OFF_FP_SHADOWFRAME 9682 mov r2, rPC 9683 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9684 9685/* ------------------------------ */ 9686 .balign 128 9687.L_ALT_op_neg_int: /* 0x7b */ 9688/* File: arm/alt_stub.S */ 9689/* 9690 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9691 * any interesting requests and then jump to the real instruction 9692 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9693 */ 9694 .extern MterpCheckBefore 9695 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9696 adrl lr, artMterpAsmInstructionStart + (123 * 128) @ Addr of primary handler. 9697 mov r0, rSELF 9698 add r1, rFP, #OFF_FP_SHADOWFRAME 9699 mov r2, rPC 9700 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9701 9702/* ------------------------------ */ 9703 .balign 128 9704.L_ALT_op_not_int: /* 0x7c */ 9705/* File: arm/alt_stub.S */ 9706/* 9707 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9708 * any interesting requests and then jump to the real instruction 9709 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9710 */ 9711 .extern MterpCheckBefore 9712 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9713 adrl lr, artMterpAsmInstructionStart + (124 * 128) @ Addr of primary handler. 9714 mov r0, rSELF 9715 add r1, rFP, #OFF_FP_SHADOWFRAME 9716 mov r2, rPC 9717 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9718 9719/* ------------------------------ */ 9720 .balign 128 9721.L_ALT_op_neg_long: /* 0x7d */ 9722/* File: arm/alt_stub.S */ 9723/* 9724 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9725 * any interesting requests and then jump to the real instruction 9726 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9727 */ 9728 .extern MterpCheckBefore 9729 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9730 adrl lr, artMterpAsmInstructionStart + (125 * 128) @ Addr of primary handler. 9731 mov r0, rSELF 9732 add r1, rFP, #OFF_FP_SHADOWFRAME 9733 mov r2, rPC 9734 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9735 9736/* ------------------------------ */ 9737 .balign 128 9738.L_ALT_op_not_long: /* 0x7e */ 9739/* File: arm/alt_stub.S */ 9740/* 9741 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9742 * any interesting requests and then jump to the real instruction 9743 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9744 */ 9745 .extern MterpCheckBefore 9746 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9747 adrl lr, artMterpAsmInstructionStart + (126 * 128) @ Addr of primary handler. 9748 mov r0, rSELF 9749 add r1, rFP, #OFF_FP_SHADOWFRAME 9750 mov r2, rPC 9751 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9752 9753/* ------------------------------ */ 9754 .balign 128 9755.L_ALT_op_neg_float: /* 0x7f */ 9756/* File: arm/alt_stub.S */ 9757/* 9758 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9759 * any interesting requests and then jump to the real instruction 9760 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9761 */ 9762 .extern MterpCheckBefore 9763 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9764 adrl lr, artMterpAsmInstructionStart + (127 * 128) @ Addr of primary handler. 9765 mov r0, rSELF 9766 add r1, rFP, #OFF_FP_SHADOWFRAME 9767 mov r2, rPC 9768 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9769 9770/* ------------------------------ */ 9771 .balign 128 9772.L_ALT_op_neg_double: /* 0x80 */ 9773/* File: arm/alt_stub.S */ 9774/* 9775 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9776 * any interesting requests and then jump to the real instruction 9777 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9778 */ 9779 .extern MterpCheckBefore 9780 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9781 adrl lr, artMterpAsmInstructionStart + (128 * 128) @ Addr of primary handler. 9782 mov r0, rSELF 9783 add r1, rFP, #OFF_FP_SHADOWFRAME 9784 mov r2, rPC 9785 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9786 9787/* ------------------------------ */ 9788 .balign 128 9789.L_ALT_op_int_to_long: /* 0x81 */ 9790/* File: arm/alt_stub.S */ 9791/* 9792 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9793 * any interesting requests and then jump to the real instruction 9794 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9795 */ 9796 .extern MterpCheckBefore 9797 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9798 adrl lr, artMterpAsmInstructionStart + (129 * 128) @ Addr of primary handler. 9799 mov r0, rSELF 9800 add r1, rFP, #OFF_FP_SHADOWFRAME 9801 mov r2, rPC 9802 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9803 9804/* ------------------------------ */ 9805 .balign 128 9806.L_ALT_op_int_to_float: /* 0x82 */ 9807/* File: arm/alt_stub.S */ 9808/* 9809 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9810 * any interesting requests and then jump to the real instruction 9811 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9812 */ 9813 .extern MterpCheckBefore 9814 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9815 adrl lr, artMterpAsmInstructionStart + (130 * 128) @ Addr of primary handler. 9816 mov r0, rSELF 9817 add r1, rFP, #OFF_FP_SHADOWFRAME 9818 mov r2, rPC 9819 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9820 9821/* ------------------------------ */ 9822 .balign 128 9823.L_ALT_op_int_to_double: /* 0x83 */ 9824/* File: arm/alt_stub.S */ 9825/* 9826 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9827 * any interesting requests and then jump to the real instruction 9828 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9829 */ 9830 .extern MterpCheckBefore 9831 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9832 adrl lr, artMterpAsmInstructionStart + (131 * 128) @ Addr of primary handler. 9833 mov r0, rSELF 9834 add r1, rFP, #OFF_FP_SHADOWFRAME 9835 mov r2, rPC 9836 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9837 9838/* ------------------------------ */ 9839 .balign 128 9840.L_ALT_op_long_to_int: /* 0x84 */ 9841/* File: arm/alt_stub.S */ 9842/* 9843 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9844 * any interesting requests and then jump to the real instruction 9845 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9846 */ 9847 .extern MterpCheckBefore 9848 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9849 adrl lr, artMterpAsmInstructionStart + (132 * 128) @ Addr of primary handler. 9850 mov r0, rSELF 9851 add r1, rFP, #OFF_FP_SHADOWFRAME 9852 mov r2, rPC 9853 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9854 9855/* ------------------------------ */ 9856 .balign 128 9857.L_ALT_op_long_to_float: /* 0x85 */ 9858/* File: arm/alt_stub.S */ 9859/* 9860 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9861 * any interesting requests and then jump to the real instruction 9862 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9863 */ 9864 .extern MterpCheckBefore 9865 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9866 adrl lr, artMterpAsmInstructionStart + (133 * 128) @ Addr of primary handler. 9867 mov r0, rSELF 9868 add r1, rFP, #OFF_FP_SHADOWFRAME 9869 mov r2, rPC 9870 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9871 9872/* ------------------------------ */ 9873 .balign 128 9874.L_ALT_op_long_to_double: /* 0x86 */ 9875/* File: arm/alt_stub.S */ 9876/* 9877 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9878 * any interesting requests and then jump to the real instruction 9879 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9880 */ 9881 .extern MterpCheckBefore 9882 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9883 adrl lr, artMterpAsmInstructionStart + (134 * 128) @ Addr of primary handler. 9884 mov r0, rSELF 9885 add r1, rFP, #OFF_FP_SHADOWFRAME 9886 mov r2, rPC 9887 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9888 9889/* ------------------------------ */ 9890 .balign 128 9891.L_ALT_op_float_to_int: /* 0x87 */ 9892/* File: arm/alt_stub.S */ 9893/* 9894 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9895 * any interesting requests and then jump to the real instruction 9896 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9897 */ 9898 .extern MterpCheckBefore 9899 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9900 adrl lr, artMterpAsmInstructionStart + (135 * 128) @ Addr of primary handler. 9901 mov r0, rSELF 9902 add r1, rFP, #OFF_FP_SHADOWFRAME 9903 mov r2, rPC 9904 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9905 9906/* ------------------------------ */ 9907 .balign 128 9908.L_ALT_op_float_to_long: /* 0x88 */ 9909/* File: arm/alt_stub.S */ 9910/* 9911 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9912 * any interesting requests and then jump to the real instruction 9913 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9914 */ 9915 .extern MterpCheckBefore 9916 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9917 adrl lr, artMterpAsmInstructionStart + (136 * 128) @ Addr of primary handler. 9918 mov r0, rSELF 9919 add r1, rFP, #OFF_FP_SHADOWFRAME 9920 mov r2, rPC 9921 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9922 9923/* ------------------------------ */ 9924 .balign 128 9925.L_ALT_op_float_to_double: /* 0x89 */ 9926/* File: arm/alt_stub.S */ 9927/* 9928 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9929 * any interesting requests and then jump to the real instruction 9930 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9931 */ 9932 .extern MterpCheckBefore 9933 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9934 adrl lr, artMterpAsmInstructionStart + (137 * 128) @ Addr of primary handler. 9935 mov r0, rSELF 9936 add r1, rFP, #OFF_FP_SHADOWFRAME 9937 mov r2, rPC 9938 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9939 9940/* ------------------------------ */ 9941 .balign 128 9942.L_ALT_op_double_to_int: /* 0x8a */ 9943/* File: arm/alt_stub.S */ 9944/* 9945 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9946 * any interesting requests and then jump to the real instruction 9947 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9948 */ 9949 .extern MterpCheckBefore 9950 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9951 adrl lr, artMterpAsmInstructionStart + (138 * 128) @ Addr of primary handler. 9952 mov r0, rSELF 9953 add r1, rFP, #OFF_FP_SHADOWFRAME 9954 mov r2, rPC 9955 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9956 9957/* ------------------------------ */ 9958 .balign 128 9959.L_ALT_op_double_to_long: /* 0x8b */ 9960/* File: arm/alt_stub.S */ 9961/* 9962 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9963 * any interesting requests and then jump to the real instruction 9964 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9965 */ 9966 .extern MterpCheckBefore 9967 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9968 adrl lr, artMterpAsmInstructionStart + (139 * 128) @ Addr of primary handler. 9969 mov r0, rSELF 9970 add r1, rFP, #OFF_FP_SHADOWFRAME 9971 mov r2, rPC 9972 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9973 9974/* ------------------------------ */ 9975 .balign 128 9976.L_ALT_op_double_to_float: /* 0x8c */ 9977/* File: arm/alt_stub.S */ 9978/* 9979 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9980 * any interesting requests and then jump to the real instruction 9981 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9982 */ 9983 .extern MterpCheckBefore 9984 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9985 adrl lr, artMterpAsmInstructionStart + (140 * 128) @ Addr of primary handler. 9986 mov r0, rSELF 9987 add r1, rFP, #OFF_FP_SHADOWFRAME 9988 mov r2, rPC 9989 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9990 9991/* ------------------------------ */ 9992 .balign 128 9993.L_ALT_op_int_to_byte: /* 0x8d */ 9994/* File: arm/alt_stub.S */ 9995/* 9996 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9997 * any interesting requests and then jump to the real instruction 9998 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9999 */ 10000 .extern MterpCheckBefore 10001 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10002 adrl lr, artMterpAsmInstructionStart + (141 * 128) @ Addr of primary handler. 10003 mov r0, rSELF 10004 add r1, rFP, #OFF_FP_SHADOWFRAME 10005 mov r2, rPC 10006 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10007 10008/* ------------------------------ */ 10009 .balign 128 10010.L_ALT_op_int_to_char: /* 0x8e */ 10011/* File: arm/alt_stub.S */ 10012/* 10013 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10014 * any interesting requests and then jump to the real instruction 10015 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10016 */ 10017 .extern MterpCheckBefore 10018 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10019 adrl lr, artMterpAsmInstructionStart + (142 * 128) @ Addr of primary handler. 10020 mov r0, rSELF 10021 add r1, rFP, #OFF_FP_SHADOWFRAME 10022 mov r2, rPC 10023 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10024 10025/* ------------------------------ */ 10026 .balign 128 10027.L_ALT_op_int_to_short: /* 0x8f */ 10028/* File: arm/alt_stub.S */ 10029/* 10030 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10031 * any interesting requests and then jump to the real instruction 10032 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10033 */ 10034 .extern MterpCheckBefore 10035 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10036 adrl lr, artMterpAsmInstructionStart + (143 * 128) @ Addr of primary handler. 10037 mov r0, rSELF 10038 add r1, rFP, #OFF_FP_SHADOWFRAME 10039 mov r2, rPC 10040 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10041 10042/* ------------------------------ */ 10043 .balign 128 10044.L_ALT_op_add_int: /* 0x90 */ 10045/* File: arm/alt_stub.S */ 10046/* 10047 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10048 * any interesting requests and then jump to the real instruction 10049 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10050 */ 10051 .extern MterpCheckBefore 10052 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10053 adrl lr, artMterpAsmInstructionStart + (144 * 128) @ Addr of primary handler. 10054 mov r0, rSELF 10055 add r1, rFP, #OFF_FP_SHADOWFRAME 10056 mov r2, rPC 10057 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10058 10059/* ------------------------------ */ 10060 .balign 128 10061.L_ALT_op_sub_int: /* 0x91 */ 10062/* File: arm/alt_stub.S */ 10063/* 10064 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10065 * any interesting requests and then jump to the real instruction 10066 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10067 */ 10068 .extern MterpCheckBefore 10069 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10070 adrl lr, artMterpAsmInstructionStart + (145 * 128) @ Addr of primary handler. 10071 mov r0, rSELF 10072 add r1, rFP, #OFF_FP_SHADOWFRAME 10073 mov r2, rPC 10074 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10075 10076/* ------------------------------ */ 10077 .balign 128 10078.L_ALT_op_mul_int: /* 0x92 */ 10079/* File: arm/alt_stub.S */ 10080/* 10081 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10082 * any interesting requests and then jump to the real instruction 10083 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10084 */ 10085 .extern MterpCheckBefore 10086 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10087 adrl lr, artMterpAsmInstructionStart + (146 * 128) @ Addr of primary handler. 10088 mov r0, rSELF 10089 add r1, rFP, #OFF_FP_SHADOWFRAME 10090 mov r2, rPC 10091 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10092 10093/* ------------------------------ */ 10094 .balign 128 10095.L_ALT_op_div_int: /* 0x93 */ 10096/* File: arm/alt_stub.S */ 10097/* 10098 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10099 * any interesting requests and then jump to the real instruction 10100 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10101 */ 10102 .extern MterpCheckBefore 10103 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10104 adrl lr, artMterpAsmInstructionStart + (147 * 128) @ Addr of primary handler. 10105 mov r0, rSELF 10106 add r1, rFP, #OFF_FP_SHADOWFRAME 10107 mov r2, rPC 10108 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10109 10110/* ------------------------------ */ 10111 .balign 128 10112.L_ALT_op_rem_int: /* 0x94 */ 10113/* File: arm/alt_stub.S */ 10114/* 10115 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10116 * any interesting requests and then jump to the real instruction 10117 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10118 */ 10119 .extern MterpCheckBefore 10120 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10121 adrl lr, artMterpAsmInstructionStart + (148 * 128) @ Addr of primary handler. 10122 mov r0, rSELF 10123 add r1, rFP, #OFF_FP_SHADOWFRAME 10124 mov r2, rPC 10125 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10126 10127/* ------------------------------ */ 10128 .balign 128 10129.L_ALT_op_and_int: /* 0x95 */ 10130/* File: arm/alt_stub.S */ 10131/* 10132 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10133 * any interesting requests and then jump to the real instruction 10134 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10135 */ 10136 .extern MterpCheckBefore 10137 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10138 adrl lr, artMterpAsmInstructionStart + (149 * 128) @ Addr of primary handler. 10139 mov r0, rSELF 10140 add r1, rFP, #OFF_FP_SHADOWFRAME 10141 mov r2, rPC 10142 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10143 10144/* ------------------------------ */ 10145 .balign 128 10146.L_ALT_op_or_int: /* 0x96 */ 10147/* File: arm/alt_stub.S */ 10148/* 10149 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10150 * any interesting requests and then jump to the real instruction 10151 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10152 */ 10153 .extern MterpCheckBefore 10154 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10155 adrl lr, artMterpAsmInstructionStart + (150 * 128) @ Addr of primary handler. 10156 mov r0, rSELF 10157 add r1, rFP, #OFF_FP_SHADOWFRAME 10158 mov r2, rPC 10159 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10160 10161/* ------------------------------ */ 10162 .balign 128 10163.L_ALT_op_xor_int: /* 0x97 */ 10164/* File: arm/alt_stub.S */ 10165/* 10166 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10167 * any interesting requests and then jump to the real instruction 10168 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10169 */ 10170 .extern MterpCheckBefore 10171 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10172 adrl lr, artMterpAsmInstructionStart + (151 * 128) @ Addr of primary handler. 10173 mov r0, rSELF 10174 add r1, rFP, #OFF_FP_SHADOWFRAME 10175 mov r2, rPC 10176 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10177 10178/* ------------------------------ */ 10179 .balign 128 10180.L_ALT_op_shl_int: /* 0x98 */ 10181/* File: arm/alt_stub.S */ 10182/* 10183 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10184 * any interesting requests and then jump to the real instruction 10185 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10186 */ 10187 .extern MterpCheckBefore 10188 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10189 adrl lr, artMterpAsmInstructionStart + (152 * 128) @ Addr of primary handler. 10190 mov r0, rSELF 10191 add r1, rFP, #OFF_FP_SHADOWFRAME 10192 mov r2, rPC 10193 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10194 10195/* ------------------------------ */ 10196 .balign 128 10197.L_ALT_op_shr_int: /* 0x99 */ 10198/* File: arm/alt_stub.S */ 10199/* 10200 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10201 * any interesting requests and then jump to the real instruction 10202 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10203 */ 10204 .extern MterpCheckBefore 10205 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10206 adrl lr, artMterpAsmInstructionStart + (153 * 128) @ Addr of primary handler. 10207 mov r0, rSELF 10208 add r1, rFP, #OFF_FP_SHADOWFRAME 10209 mov r2, rPC 10210 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10211 10212/* ------------------------------ */ 10213 .balign 128 10214.L_ALT_op_ushr_int: /* 0x9a */ 10215/* File: arm/alt_stub.S */ 10216/* 10217 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10218 * any interesting requests and then jump to the real instruction 10219 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10220 */ 10221 .extern MterpCheckBefore 10222 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10223 adrl lr, artMterpAsmInstructionStart + (154 * 128) @ Addr of primary handler. 10224 mov r0, rSELF 10225 add r1, rFP, #OFF_FP_SHADOWFRAME 10226 mov r2, rPC 10227 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10228 10229/* ------------------------------ */ 10230 .balign 128 10231.L_ALT_op_add_long: /* 0x9b */ 10232/* File: arm/alt_stub.S */ 10233/* 10234 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10235 * any interesting requests and then jump to the real instruction 10236 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10237 */ 10238 .extern MterpCheckBefore 10239 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10240 adrl lr, artMterpAsmInstructionStart + (155 * 128) @ Addr of primary handler. 10241 mov r0, rSELF 10242 add r1, rFP, #OFF_FP_SHADOWFRAME 10243 mov r2, rPC 10244 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10245 10246/* ------------------------------ */ 10247 .balign 128 10248.L_ALT_op_sub_long: /* 0x9c */ 10249/* File: arm/alt_stub.S */ 10250/* 10251 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10252 * any interesting requests and then jump to the real instruction 10253 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10254 */ 10255 .extern MterpCheckBefore 10256 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10257 adrl lr, artMterpAsmInstructionStart + (156 * 128) @ Addr of primary handler. 10258 mov r0, rSELF 10259 add r1, rFP, #OFF_FP_SHADOWFRAME 10260 mov r2, rPC 10261 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10262 10263/* ------------------------------ */ 10264 .balign 128 10265.L_ALT_op_mul_long: /* 0x9d */ 10266/* File: arm/alt_stub.S */ 10267/* 10268 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10269 * any interesting requests and then jump to the real instruction 10270 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10271 */ 10272 .extern MterpCheckBefore 10273 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10274 adrl lr, artMterpAsmInstructionStart + (157 * 128) @ Addr of primary handler. 10275 mov r0, rSELF 10276 add r1, rFP, #OFF_FP_SHADOWFRAME 10277 mov r2, rPC 10278 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10279 10280/* ------------------------------ */ 10281 .balign 128 10282.L_ALT_op_div_long: /* 0x9e */ 10283/* File: arm/alt_stub.S */ 10284/* 10285 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10286 * any interesting requests and then jump to the real instruction 10287 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10288 */ 10289 .extern MterpCheckBefore 10290 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10291 adrl lr, artMterpAsmInstructionStart + (158 * 128) @ Addr of primary handler. 10292 mov r0, rSELF 10293 add r1, rFP, #OFF_FP_SHADOWFRAME 10294 mov r2, rPC 10295 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10296 10297/* ------------------------------ */ 10298 .balign 128 10299.L_ALT_op_rem_long: /* 0x9f */ 10300/* File: arm/alt_stub.S */ 10301/* 10302 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10303 * any interesting requests and then jump to the real instruction 10304 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10305 */ 10306 .extern MterpCheckBefore 10307 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10308 adrl lr, artMterpAsmInstructionStart + (159 * 128) @ Addr of primary handler. 10309 mov r0, rSELF 10310 add r1, rFP, #OFF_FP_SHADOWFRAME 10311 mov r2, rPC 10312 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10313 10314/* ------------------------------ */ 10315 .balign 128 10316.L_ALT_op_and_long: /* 0xa0 */ 10317/* File: arm/alt_stub.S */ 10318/* 10319 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10320 * any interesting requests and then jump to the real instruction 10321 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10322 */ 10323 .extern MterpCheckBefore 10324 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10325 adrl lr, artMterpAsmInstructionStart + (160 * 128) @ Addr of primary handler. 10326 mov r0, rSELF 10327 add r1, rFP, #OFF_FP_SHADOWFRAME 10328 mov r2, rPC 10329 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10330 10331/* ------------------------------ */ 10332 .balign 128 10333.L_ALT_op_or_long: /* 0xa1 */ 10334/* File: arm/alt_stub.S */ 10335/* 10336 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10337 * any interesting requests and then jump to the real instruction 10338 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10339 */ 10340 .extern MterpCheckBefore 10341 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10342 adrl lr, artMterpAsmInstructionStart + (161 * 128) @ Addr of primary handler. 10343 mov r0, rSELF 10344 add r1, rFP, #OFF_FP_SHADOWFRAME 10345 mov r2, rPC 10346 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10347 10348/* ------------------------------ */ 10349 .balign 128 10350.L_ALT_op_xor_long: /* 0xa2 */ 10351/* File: arm/alt_stub.S */ 10352/* 10353 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10354 * any interesting requests and then jump to the real instruction 10355 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10356 */ 10357 .extern MterpCheckBefore 10358 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10359 adrl lr, artMterpAsmInstructionStart + (162 * 128) @ Addr of primary handler. 10360 mov r0, rSELF 10361 add r1, rFP, #OFF_FP_SHADOWFRAME 10362 mov r2, rPC 10363 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10364 10365/* ------------------------------ */ 10366 .balign 128 10367.L_ALT_op_shl_long: /* 0xa3 */ 10368/* File: arm/alt_stub.S */ 10369/* 10370 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10371 * any interesting requests and then jump to the real instruction 10372 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10373 */ 10374 .extern MterpCheckBefore 10375 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10376 adrl lr, artMterpAsmInstructionStart + (163 * 128) @ Addr of primary handler. 10377 mov r0, rSELF 10378 add r1, rFP, #OFF_FP_SHADOWFRAME 10379 mov r2, rPC 10380 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10381 10382/* ------------------------------ */ 10383 .balign 128 10384.L_ALT_op_shr_long: /* 0xa4 */ 10385/* File: arm/alt_stub.S */ 10386/* 10387 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10388 * any interesting requests and then jump to the real instruction 10389 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10390 */ 10391 .extern MterpCheckBefore 10392 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10393 adrl lr, artMterpAsmInstructionStart + (164 * 128) @ Addr of primary handler. 10394 mov r0, rSELF 10395 add r1, rFP, #OFF_FP_SHADOWFRAME 10396 mov r2, rPC 10397 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10398 10399/* ------------------------------ */ 10400 .balign 128 10401.L_ALT_op_ushr_long: /* 0xa5 */ 10402/* File: arm/alt_stub.S */ 10403/* 10404 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10405 * any interesting requests and then jump to the real instruction 10406 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10407 */ 10408 .extern MterpCheckBefore 10409 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10410 adrl lr, artMterpAsmInstructionStart + (165 * 128) @ Addr of primary handler. 10411 mov r0, rSELF 10412 add r1, rFP, #OFF_FP_SHADOWFRAME 10413 mov r2, rPC 10414 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10415 10416/* ------------------------------ */ 10417 .balign 128 10418.L_ALT_op_add_float: /* 0xa6 */ 10419/* File: arm/alt_stub.S */ 10420/* 10421 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10422 * any interesting requests and then jump to the real instruction 10423 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10424 */ 10425 .extern MterpCheckBefore 10426 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10427 adrl lr, artMterpAsmInstructionStart + (166 * 128) @ Addr of primary handler. 10428 mov r0, rSELF 10429 add r1, rFP, #OFF_FP_SHADOWFRAME 10430 mov r2, rPC 10431 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10432 10433/* ------------------------------ */ 10434 .balign 128 10435.L_ALT_op_sub_float: /* 0xa7 */ 10436/* File: arm/alt_stub.S */ 10437/* 10438 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10439 * any interesting requests and then jump to the real instruction 10440 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10441 */ 10442 .extern MterpCheckBefore 10443 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10444 adrl lr, artMterpAsmInstructionStart + (167 * 128) @ Addr of primary handler. 10445 mov r0, rSELF 10446 add r1, rFP, #OFF_FP_SHADOWFRAME 10447 mov r2, rPC 10448 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10449 10450/* ------------------------------ */ 10451 .balign 128 10452.L_ALT_op_mul_float: /* 0xa8 */ 10453/* File: arm/alt_stub.S */ 10454/* 10455 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10456 * any interesting requests and then jump to the real instruction 10457 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10458 */ 10459 .extern MterpCheckBefore 10460 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10461 adrl lr, artMterpAsmInstructionStart + (168 * 128) @ Addr of primary handler. 10462 mov r0, rSELF 10463 add r1, rFP, #OFF_FP_SHADOWFRAME 10464 mov r2, rPC 10465 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10466 10467/* ------------------------------ */ 10468 .balign 128 10469.L_ALT_op_div_float: /* 0xa9 */ 10470/* File: arm/alt_stub.S */ 10471/* 10472 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10473 * any interesting requests and then jump to the real instruction 10474 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10475 */ 10476 .extern MterpCheckBefore 10477 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10478 adrl lr, artMterpAsmInstructionStart + (169 * 128) @ Addr of primary handler. 10479 mov r0, rSELF 10480 add r1, rFP, #OFF_FP_SHADOWFRAME 10481 mov r2, rPC 10482 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10483 10484/* ------------------------------ */ 10485 .balign 128 10486.L_ALT_op_rem_float: /* 0xaa */ 10487/* File: arm/alt_stub.S */ 10488/* 10489 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10490 * any interesting requests and then jump to the real instruction 10491 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10492 */ 10493 .extern MterpCheckBefore 10494 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10495 adrl lr, artMterpAsmInstructionStart + (170 * 128) @ Addr of primary handler. 10496 mov r0, rSELF 10497 add r1, rFP, #OFF_FP_SHADOWFRAME 10498 mov r2, rPC 10499 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10500 10501/* ------------------------------ */ 10502 .balign 128 10503.L_ALT_op_add_double: /* 0xab */ 10504/* File: arm/alt_stub.S */ 10505/* 10506 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10507 * any interesting requests and then jump to the real instruction 10508 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10509 */ 10510 .extern MterpCheckBefore 10511 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10512 adrl lr, artMterpAsmInstructionStart + (171 * 128) @ Addr of primary handler. 10513 mov r0, rSELF 10514 add r1, rFP, #OFF_FP_SHADOWFRAME 10515 mov r2, rPC 10516 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10517 10518/* ------------------------------ */ 10519 .balign 128 10520.L_ALT_op_sub_double: /* 0xac */ 10521/* File: arm/alt_stub.S */ 10522/* 10523 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10524 * any interesting requests and then jump to the real instruction 10525 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10526 */ 10527 .extern MterpCheckBefore 10528 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10529 adrl lr, artMterpAsmInstructionStart + (172 * 128) @ Addr of primary handler. 10530 mov r0, rSELF 10531 add r1, rFP, #OFF_FP_SHADOWFRAME 10532 mov r2, rPC 10533 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10534 10535/* ------------------------------ */ 10536 .balign 128 10537.L_ALT_op_mul_double: /* 0xad */ 10538/* File: arm/alt_stub.S */ 10539/* 10540 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10541 * any interesting requests and then jump to the real instruction 10542 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10543 */ 10544 .extern MterpCheckBefore 10545 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10546 adrl lr, artMterpAsmInstructionStart + (173 * 128) @ Addr of primary handler. 10547 mov r0, rSELF 10548 add r1, rFP, #OFF_FP_SHADOWFRAME 10549 mov r2, rPC 10550 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10551 10552/* ------------------------------ */ 10553 .balign 128 10554.L_ALT_op_div_double: /* 0xae */ 10555/* File: arm/alt_stub.S */ 10556/* 10557 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10558 * any interesting requests and then jump to the real instruction 10559 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10560 */ 10561 .extern MterpCheckBefore 10562 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10563 adrl lr, artMterpAsmInstructionStart + (174 * 128) @ Addr of primary handler. 10564 mov r0, rSELF 10565 add r1, rFP, #OFF_FP_SHADOWFRAME 10566 mov r2, rPC 10567 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10568 10569/* ------------------------------ */ 10570 .balign 128 10571.L_ALT_op_rem_double: /* 0xaf */ 10572/* File: arm/alt_stub.S */ 10573/* 10574 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10575 * any interesting requests and then jump to the real instruction 10576 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10577 */ 10578 .extern MterpCheckBefore 10579 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10580 adrl lr, artMterpAsmInstructionStart + (175 * 128) @ Addr of primary handler. 10581 mov r0, rSELF 10582 add r1, rFP, #OFF_FP_SHADOWFRAME 10583 mov r2, rPC 10584 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10585 10586/* ------------------------------ */ 10587 .balign 128 10588.L_ALT_op_add_int_2addr: /* 0xb0 */ 10589/* File: arm/alt_stub.S */ 10590/* 10591 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10592 * any interesting requests and then jump to the real instruction 10593 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10594 */ 10595 .extern MterpCheckBefore 10596 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10597 adrl lr, artMterpAsmInstructionStart + (176 * 128) @ Addr of primary handler. 10598 mov r0, rSELF 10599 add r1, rFP, #OFF_FP_SHADOWFRAME 10600 mov r2, rPC 10601 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10602 10603/* ------------------------------ */ 10604 .balign 128 10605.L_ALT_op_sub_int_2addr: /* 0xb1 */ 10606/* File: arm/alt_stub.S */ 10607/* 10608 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10609 * any interesting requests and then jump to the real instruction 10610 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10611 */ 10612 .extern MterpCheckBefore 10613 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10614 adrl lr, artMterpAsmInstructionStart + (177 * 128) @ Addr of primary handler. 10615 mov r0, rSELF 10616 add r1, rFP, #OFF_FP_SHADOWFRAME 10617 mov r2, rPC 10618 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10619 10620/* ------------------------------ */ 10621 .balign 128 10622.L_ALT_op_mul_int_2addr: /* 0xb2 */ 10623/* File: arm/alt_stub.S */ 10624/* 10625 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10626 * any interesting requests and then jump to the real instruction 10627 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10628 */ 10629 .extern MterpCheckBefore 10630 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10631 adrl lr, artMterpAsmInstructionStart + (178 * 128) @ Addr of primary handler. 10632 mov r0, rSELF 10633 add r1, rFP, #OFF_FP_SHADOWFRAME 10634 mov r2, rPC 10635 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10636 10637/* ------------------------------ */ 10638 .balign 128 10639.L_ALT_op_div_int_2addr: /* 0xb3 */ 10640/* File: arm/alt_stub.S */ 10641/* 10642 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10643 * any interesting requests and then jump to the real instruction 10644 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10645 */ 10646 .extern MterpCheckBefore 10647 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10648 adrl lr, artMterpAsmInstructionStart + (179 * 128) @ Addr of primary handler. 10649 mov r0, rSELF 10650 add r1, rFP, #OFF_FP_SHADOWFRAME 10651 mov r2, rPC 10652 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10653 10654/* ------------------------------ */ 10655 .balign 128 10656.L_ALT_op_rem_int_2addr: /* 0xb4 */ 10657/* File: arm/alt_stub.S */ 10658/* 10659 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10660 * any interesting requests and then jump to the real instruction 10661 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10662 */ 10663 .extern MterpCheckBefore 10664 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10665 adrl lr, artMterpAsmInstructionStart + (180 * 128) @ Addr of primary handler. 10666 mov r0, rSELF 10667 add r1, rFP, #OFF_FP_SHADOWFRAME 10668 mov r2, rPC 10669 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10670 10671/* ------------------------------ */ 10672 .balign 128 10673.L_ALT_op_and_int_2addr: /* 0xb5 */ 10674/* File: arm/alt_stub.S */ 10675/* 10676 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10677 * any interesting requests and then jump to the real instruction 10678 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10679 */ 10680 .extern MterpCheckBefore 10681 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10682 adrl lr, artMterpAsmInstructionStart + (181 * 128) @ Addr of primary handler. 10683 mov r0, rSELF 10684 add r1, rFP, #OFF_FP_SHADOWFRAME 10685 mov r2, rPC 10686 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10687 10688/* ------------------------------ */ 10689 .balign 128 10690.L_ALT_op_or_int_2addr: /* 0xb6 */ 10691/* File: arm/alt_stub.S */ 10692/* 10693 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10694 * any interesting requests and then jump to the real instruction 10695 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10696 */ 10697 .extern MterpCheckBefore 10698 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10699 adrl lr, artMterpAsmInstructionStart + (182 * 128) @ Addr of primary handler. 10700 mov r0, rSELF 10701 add r1, rFP, #OFF_FP_SHADOWFRAME 10702 mov r2, rPC 10703 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10704 10705/* ------------------------------ */ 10706 .balign 128 10707.L_ALT_op_xor_int_2addr: /* 0xb7 */ 10708/* File: arm/alt_stub.S */ 10709/* 10710 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10711 * any interesting requests and then jump to the real instruction 10712 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10713 */ 10714 .extern MterpCheckBefore 10715 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10716 adrl lr, artMterpAsmInstructionStart + (183 * 128) @ Addr of primary handler. 10717 mov r0, rSELF 10718 add r1, rFP, #OFF_FP_SHADOWFRAME 10719 mov r2, rPC 10720 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10721 10722/* ------------------------------ */ 10723 .balign 128 10724.L_ALT_op_shl_int_2addr: /* 0xb8 */ 10725/* File: arm/alt_stub.S */ 10726/* 10727 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10728 * any interesting requests and then jump to the real instruction 10729 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10730 */ 10731 .extern MterpCheckBefore 10732 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10733 adrl lr, artMterpAsmInstructionStart + (184 * 128) @ Addr of primary handler. 10734 mov r0, rSELF 10735 add r1, rFP, #OFF_FP_SHADOWFRAME 10736 mov r2, rPC 10737 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10738 10739/* ------------------------------ */ 10740 .balign 128 10741.L_ALT_op_shr_int_2addr: /* 0xb9 */ 10742/* File: arm/alt_stub.S */ 10743/* 10744 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10745 * any interesting requests and then jump to the real instruction 10746 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10747 */ 10748 .extern MterpCheckBefore 10749 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10750 adrl lr, artMterpAsmInstructionStart + (185 * 128) @ Addr of primary handler. 10751 mov r0, rSELF 10752 add r1, rFP, #OFF_FP_SHADOWFRAME 10753 mov r2, rPC 10754 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10755 10756/* ------------------------------ */ 10757 .balign 128 10758.L_ALT_op_ushr_int_2addr: /* 0xba */ 10759/* File: arm/alt_stub.S */ 10760/* 10761 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10762 * any interesting requests and then jump to the real instruction 10763 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10764 */ 10765 .extern MterpCheckBefore 10766 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10767 adrl lr, artMterpAsmInstructionStart + (186 * 128) @ Addr of primary handler. 10768 mov r0, rSELF 10769 add r1, rFP, #OFF_FP_SHADOWFRAME 10770 mov r2, rPC 10771 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10772 10773/* ------------------------------ */ 10774 .balign 128 10775.L_ALT_op_add_long_2addr: /* 0xbb */ 10776/* File: arm/alt_stub.S */ 10777/* 10778 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10779 * any interesting requests and then jump to the real instruction 10780 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10781 */ 10782 .extern MterpCheckBefore 10783 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10784 adrl lr, artMterpAsmInstructionStart + (187 * 128) @ Addr of primary handler. 10785 mov r0, rSELF 10786 add r1, rFP, #OFF_FP_SHADOWFRAME 10787 mov r2, rPC 10788 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10789 10790/* ------------------------------ */ 10791 .balign 128 10792.L_ALT_op_sub_long_2addr: /* 0xbc */ 10793/* File: arm/alt_stub.S */ 10794/* 10795 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10796 * any interesting requests and then jump to the real instruction 10797 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10798 */ 10799 .extern MterpCheckBefore 10800 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10801 adrl lr, artMterpAsmInstructionStart + (188 * 128) @ Addr of primary handler. 10802 mov r0, rSELF 10803 add r1, rFP, #OFF_FP_SHADOWFRAME 10804 mov r2, rPC 10805 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10806 10807/* ------------------------------ */ 10808 .balign 128 10809.L_ALT_op_mul_long_2addr: /* 0xbd */ 10810/* File: arm/alt_stub.S */ 10811/* 10812 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10813 * any interesting requests and then jump to the real instruction 10814 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10815 */ 10816 .extern MterpCheckBefore 10817 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10818 adrl lr, artMterpAsmInstructionStart + (189 * 128) @ Addr of primary handler. 10819 mov r0, rSELF 10820 add r1, rFP, #OFF_FP_SHADOWFRAME 10821 mov r2, rPC 10822 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10823 10824/* ------------------------------ */ 10825 .balign 128 10826.L_ALT_op_div_long_2addr: /* 0xbe */ 10827/* File: arm/alt_stub.S */ 10828/* 10829 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10830 * any interesting requests and then jump to the real instruction 10831 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10832 */ 10833 .extern MterpCheckBefore 10834 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10835 adrl lr, artMterpAsmInstructionStart + (190 * 128) @ Addr of primary handler. 10836 mov r0, rSELF 10837 add r1, rFP, #OFF_FP_SHADOWFRAME 10838 mov r2, rPC 10839 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10840 10841/* ------------------------------ */ 10842 .balign 128 10843.L_ALT_op_rem_long_2addr: /* 0xbf */ 10844/* File: arm/alt_stub.S */ 10845/* 10846 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10847 * any interesting requests and then jump to the real instruction 10848 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10849 */ 10850 .extern MterpCheckBefore 10851 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10852 adrl lr, artMterpAsmInstructionStart + (191 * 128) @ Addr of primary handler. 10853 mov r0, rSELF 10854 add r1, rFP, #OFF_FP_SHADOWFRAME 10855 mov r2, rPC 10856 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10857 10858/* ------------------------------ */ 10859 .balign 128 10860.L_ALT_op_and_long_2addr: /* 0xc0 */ 10861/* File: arm/alt_stub.S */ 10862/* 10863 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10864 * any interesting requests and then jump to the real instruction 10865 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10866 */ 10867 .extern MterpCheckBefore 10868 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10869 adrl lr, artMterpAsmInstructionStart + (192 * 128) @ Addr of primary handler. 10870 mov r0, rSELF 10871 add r1, rFP, #OFF_FP_SHADOWFRAME 10872 mov r2, rPC 10873 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10874 10875/* ------------------------------ */ 10876 .balign 128 10877.L_ALT_op_or_long_2addr: /* 0xc1 */ 10878/* File: arm/alt_stub.S */ 10879/* 10880 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10881 * any interesting requests and then jump to the real instruction 10882 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10883 */ 10884 .extern MterpCheckBefore 10885 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10886 adrl lr, artMterpAsmInstructionStart + (193 * 128) @ Addr of primary handler. 10887 mov r0, rSELF 10888 add r1, rFP, #OFF_FP_SHADOWFRAME 10889 mov r2, rPC 10890 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10891 10892/* ------------------------------ */ 10893 .balign 128 10894.L_ALT_op_xor_long_2addr: /* 0xc2 */ 10895/* File: arm/alt_stub.S */ 10896/* 10897 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10898 * any interesting requests and then jump to the real instruction 10899 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10900 */ 10901 .extern MterpCheckBefore 10902 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10903 adrl lr, artMterpAsmInstructionStart + (194 * 128) @ Addr of primary handler. 10904 mov r0, rSELF 10905 add r1, rFP, #OFF_FP_SHADOWFRAME 10906 mov r2, rPC 10907 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10908 10909/* ------------------------------ */ 10910 .balign 128 10911.L_ALT_op_shl_long_2addr: /* 0xc3 */ 10912/* File: arm/alt_stub.S */ 10913/* 10914 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10915 * any interesting requests and then jump to the real instruction 10916 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10917 */ 10918 .extern MterpCheckBefore 10919 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10920 adrl lr, artMterpAsmInstructionStart + (195 * 128) @ Addr of primary handler. 10921 mov r0, rSELF 10922 add r1, rFP, #OFF_FP_SHADOWFRAME 10923 mov r2, rPC 10924 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10925 10926/* ------------------------------ */ 10927 .balign 128 10928.L_ALT_op_shr_long_2addr: /* 0xc4 */ 10929/* File: arm/alt_stub.S */ 10930/* 10931 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10932 * any interesting requests and then jump to the real instruction 10933 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10934 */ 10935 .extern MterpCheckBefore 10936 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10937 adrl lr, artMterpAsmInstructionStart + (196 * 128) @ Addr of primary handler. 10938 mov r0, rSELF 10939 add r1, rFP, #OFF_FP_SHADOWFRAME 10940 mov r2, rPC 10941 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10942 10943/* ------------------------------ */ 10944 .balign 128 10945.L_ALT_op_ushr_long_2addr: /* 0xc5 */ 10946/* File: arm/alt_stub.S */ 10947/* 10948 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10949 * any interesting requests and then jump to the real instruction 10950 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10951 */ 10952 .extern MterpCheckBefore 10953 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10954 adrl lr, artMterpAsmInstructionStart + (197 * 128) @ Addr of primary handler. 10955 mov r0, rSELF 10956 add r1, rFP, #OFF_FP_SHADOWFRAME 10957 mov r2, rPC 10958 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10959 10960/* ------------------------------ */ 10961 .balign 128 10962.L_ALT_op_add_float_2addr: /* 0xc6 */ 10963/* File: arm/alt_stub.S */ 10964/* 10965 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10966 * any interesting requests and then jump to the real instruction 10967 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10968 */ 10969 .extern MterpCheckBefore 10970 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10971 adrl lr, artMterpAsmInstructionStart + (198 * 128) @ Addr of primary handler. 10972 mov r0, rSELF 10973 add r1, rFP, #OFF_FP_SHADOWFRAME 10974 mov r2, rPC 10975 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10976 10977/* ------------------------------ */ 10978 .balign 128 10979.L_ALT_op_sub_float_2addr: /* 0xc7 */ 10980/* File: arm/alt_stub.S */ 10981/* 10982 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10983 * any interesting requests and then jump to the real instruction 10984 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10985 */ 10986 .extern MterpCheckBefore 10987 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10988 adrl lr, artMterpAsmInstructionStart + (199 * 128) @ Addr of primary handler. 10989 mov r0, rSELF 10990 add r1, rFP, #OFF_FP_SHADOWFRAME 10991 mov r2, rPC 10992 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10993 10994/* ------------------------------ */ 10995 .balign 128 10996.L_ALT_op_mul_float_2addr: /* 0xc8 */ 10997/* File: arm/alt_stub.S */ 10998/* 10999 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11000 * any interesting requests and then jump to the real instruction 11001 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11002 */ 11003 .extern MterpCheckBefore 11004 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11005 adrl lr, artMterpAsmInstructionStart + (200 * 128) @ Addr of primary handler. 11006 mov r0, rSELF 11007 add r1, rFP, #OFF_FP_SHADOWFRAME 11008 mov r2, rPC 11009 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11010 11011/* ------------------------------ */ 11012 .balign 128 11013.L_ALT_op_div_float_2addr: /* 0xc9 */ 11014/* File: arm/alt_stub.S */ 11015/* 11016 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11017 * any interesting requests and then jump to the real instruction 11018 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11019 */ 11020 .extern MterpCheckBefore 11021 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11022 adrl lr, artMterpAsmInstructionStart + (201 * 128) @ Addr of primary handler. 11023 mov r0, rSELF 11024 add r1, rFP, #OFF_FP_SHADOWFRAME 11025 mov r2, rPC 11026 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11027 11028/* ------------------------------ */ 11029 .balign 128 11030.L_ALT_op_rem_float_2addr: /* 0xca */ 11031/* File: arm/alt_stub.S */ 11032/* 11033 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11034 * any interesting requests and then jump to the real instruction 11035 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11036 */ 11037 .extern MterpCheckBefore 11038 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11039 adrl lr, artMterpAsmInstructionStart + (202 * 128) @ Addr of primary handler. 11040 mov r0, rSELF 11041 add r1, rFP, #OFF_FP_SHADOWFRAME 11042 mov r2, rPC 11043 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11044 11045/* ------------------------------ */ 11046 .balign 128 11047.L_ALT_op_add_double_2addr: /* 0xcb */ 11048/* File: arm/alt_stub.S */ 11049/* 11050 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11051 * any interesting requests and then jump to the real instruction 11052 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11053 */ 11054 .extern MterpCheckBefore 11055 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11056 adrl lr, artMterpAsmInstructionStart + (203 * 128) @ Addr of primary handler. 11057 mov r0, rSELF 11058 add r1, rFP, #OFF_FP_SHADOWFRAME 11059 mov r2, rPC 11060 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11061 11062/* ------------------------------ */ 11063 .balign 128 11064.L_ALT_op_sub_double_2addr: /* 0xcc */ 11065/* File: arm/alt_stub.S */ 11066/* 11067 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11068 * any interesting requests and then jump to the real instruction 11069 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11070 */ 11071 .extern MterpCheckBefore 11072 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11073 adrl lr, artMterpAsmInstructionStart + (204 * 128) @ Addr of primary handler. 11074 mov r0, rSELF 11075 add r1, rFP, #OFF_FP_SHADOWFRAME 11076 mov r2, rPC 11077 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11078 11079/* ------------------------------ */ 11080 .balign 128 11081.L_ALT_op_mul_double_2addr: /* 0xcd */ 11082/* File: arm/alt_stub.S */ 11083/* 11084 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11085 * any interesting requests and then jump to the real instruction 11086 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11087 */ 11088 .extern MterpCheckBefore 11089 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11090 adrl lr, artMterpAsmInstructionStart + (205 * 128) @ Addr of primary handler. 11091 mov r0, rSELF 11092 add r1, rFP, #OFF_FP_SHADOWFRAME 11093 mov r2, rPC 11094 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11095 11096/* ------------------------------ */ 11097 .balign 128 11098.L_ALT_op_div_double_2addr: /* 0xce */ 11099/* File: arm/alt_stub.S */ 11100/* 11101 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11102 * any interesting requests and then jump to the real instruction 11103 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11104 */ 11105 .extern MterpCheckBefore 11106 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11107 adrl lr, artMterpAsmInstructionStart + (206 * 128) @ Addr of primary handler. 11108 mov r0, rSELF 11109 add r1, rFP, #OFF_FP_SHADOWFRAME 11110 mov r2, rPC 11111 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11112 11113/* ------------------------------ */ 11114 .balign 128 11115.L_ALT_op_rem_double_2addr: /* 0xcf */ 11116/* File: arm/alt_stub.S */ 11117/* 11118 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11119 * any interesting requests and then jump to the real instruction 11120 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11121 */ 11122 .extern MterpCheckBefore 11123 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11124 adrl lr, artMterpAsmInstructionStart + (207 * 128) @ Addr of primary handler. 11125 mov r0, rSELF 11126 add r1, rFP, #OFF_FP_SHADOWFRAME 11127 mov r2, rPC 11128 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11129 11130/* ------------------------------ */ 11131 .balign 128 11132.L_ALT_op_add_int_lit16: /* 0xd0 */ 11133/* File: arm/alt_stub.S */ 11134/* 11135 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11136 * any interesting requests and then jump to the real instruction 11137 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11138 */ 11139 .extern MterpCheckBefore 11140 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11141 adrl lr, artMterpAsmInstructionStart + (208 * 128) @ Addr of primary handler. 11142 mov r0, rSELF 11143 add r1, rFP, #OFF_FP_SHADOWFRAME 11144 mov r2, rPC 11145 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11146 11147/* ------------------------------ */ 11148 .balign 128 11149.L_ALT_op_rsub_int: /* 0xd1 */ 11150/* File: arm/alt_stub.S */ 11151/* 11152 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11153 * any interesting requests and then jump to the real instruction 11154 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11155 */ 11156 .extern MterpCheckBefore 11157 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11158 adrl lr, artMterpAsmInstructionStart + (209 * 128) @ Addr of primary handler. 11159 mov r0, rSELF 11160 add r1, rFP, #OFF_FP_SHADOWFRAME 11161 mov r2, rPC 11162 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11163 11164/* ------------------------------ */ 11165 .balign 128 11166.L_ALT_op_mul_int_lit16: /* 0xd2 */ 11167/* File: arm/alt_stub.S */ 11168/* 11169 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11170 * any interesting requests and then jump to the real instruction 11171 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11172 */ 11173 .extern MterpCheckBefore 11174 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11175 adrl lr, artMterpAsmInstructionStart + (210 * 128) @ Addr of primary handler. 11176 mov r0, rSELF 11177 add r1, rFP, #OFF_FP_SHADOWFRAME 11178 mov r2, rPC 11179 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11180 11181/* ------------------------------ */ 11182 .balign 128 11183.L_ALT_op_div_int_lit16: /* 0xd3 */ 11184/* File: arm/alt_stub.S */ 11185/* 11186 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11187 * any interesting requests and then jump to the real instruction 11188 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11189 */ 11190 .extern MterpCheckBefore 11191 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11192 adrl lr, artMterpAsmInstructionStart + (211 * 128) @ Addr of primary handler. 11193 mov r0, rSELF 11194 add r1, rFP, #OFF_FP_SHADOWFRAME 11195 mov r2, rPC 11196 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11197 11198/* ------------------------------ */ 11199 .balign 128 11200.L_ALT_op_rem_int_lit16: /* 0xd4 */ 11201/* File: arm/alt_stub.S */ 11202/* 11203 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11204 * any interesting requests and then jump to the real instruction 11205 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11206 */ 11207 .extern MterpCheckBefore 11208 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11209 adrl lr, artMterpAsmInstructionStart + (212 * 128) @ Addr of primary handler. 11210 mov r0, rSELF 11211 add r1, rFP, #OFF_FP_SHADOWFRAME 11212 mov r2, rPC 11213 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11214 11215/* ------------------------------ */ 11216 .balign 128 11217.L_ALT_op_and_int_lit16: /* 0xd5 */ 11218/* File: arm/alt_stub.S */ 11219/* 11220 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11221 * any interesting requests and then jump to the real instruction 11222 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11223 */ 11224 .extern MterpCheckBefore 11225 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11226 adrl lr, artMterpAsmInstructionStart + (213 * 128) @ Addr of primary handler. 11227 mov r0, rSELF 11228 add r1, rFP, #OFF_FP_SHADOWFRAME 11229 mov r2, rPC 11230 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11231 11232/* ------------------------------ */ 11233 .balign 128 11234.L_ALT_op_or_int_lit16: /* 0xd6 */ 11235/* File: arm/alt_stub.S */ 11236/* 11237 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11238 * any interesting requests and then jump to the real instruction 11239 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11240 */ 11241 .extern MterpCheckBefore 11242 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11243 adrl lr, artMterpAsmInstructionStart + (214 * 128) @ Addr of primary handler. 11244 mov r0, rSELF 11245 add r1, rFP, #OFF_FP_SHADOWFRAME 11246 mov r2, rPC 11247 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11248 11249/* ------------------------------ */ 11250 .balign 128 11251.L_ALT_op_xor_int_lit16: /* 0xd7 */ 11252/* File: arm/alt_stub.S */ 11253/* 11254 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11255 * any interesting requests and then jump to the real instruction 11256 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11257 */ 11258 .extern MterpCheckBefore 11259 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11260 adrl lr, artMterpAsmInstructionStart + (215 * 128) @ Addr of primary handler. 11261 mov r0, rSELF 11262 add r1, rFP, #OFF_FP_SHADOWFRAME 11263 mov r2, rPC 11264 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11265 11266/* ------------------------------ */ 11267 .balign 128 11268.L_ALT_op_add_int_lit8: /* 0xd8 */ 11269/* File: arm/alt_stub.S */ 11270/* 11271 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11272 * any interesting requests and then jump to the real instruction 11273 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11274 */ 11275 .extern MterpCheckBefore 11276 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11277 adrl lr, artMterpAsmInstructionStart + (216 * 128) @ Addr of primary handler. 11278 mov r0, rSELF 11279 add r1, rFP, #OFF_FP_SHADOWFRAME 11280 mov r2, rPC 11281 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11282 11283/* ------------------------------ */ 11284 .balign 128 11285.L_ALT_op_rsub_int_lit8: /* 0xd9 */ 11286/* File: arm/alt_stub.S */ 11287/* 11288 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11289 * any interesting requests and then jump to the real instruction 11290 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11291 */ 11292 .extern MterpCheckBefore 11293 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11294 adrl lr, artMterpAsmInstructionStart + (217 * 128) @ Addr of primary handler. 11295 mov r0, rSELF 11296 add r1, rFP, #OFF_FP_SHADOWFRAME 11297 mov r2, rPC 11298 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11299 11300/* ------------------------------ */ 11301 .balign 128 11302.L_ALT_op_mul_int_lit8: /* 0xda */ 11303/* File: arm/alt_stub.S */ 11304/* 11305 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11306 * any interesting requests and then jump to the real instruction 11307 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11308 */ 11309 .extern MterpCheckBefore 11310 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11311 adrl lr, artMterpAsmInstructionStart + (218 * 128) @ Addr of primary handler. 11312 mov r0, rSELF 11313 add r1, rFP, #OFF_FP_SHADOWFRAME 11314 mov r2, rPC 11315 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11316 11317/* ------------------------------ */ 11318 .balign 128 11319.L_ALT_op_div_int_lit8: /* 0xdb */ 11320/* File: arm/alt_stub.S */ 11321/* 11322 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11323 * any interesting requests and then jump to the real instruction 11324 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11325 */ 11326 .extern MterpCheckBefore 11327 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11328 adrl lr, artMterpAsmInstructionStart + (219 * 128) @ Addr of primary handler. 11329 mov r0, rSELF 11330 add r1, rFP, #OFF_FP_SHADOWFRAME 11331 mov r2, rPC 11332 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11333 11334/* ------------------------------ */ 11335 .balign 128 11336.L_ALT_op_rem_int_lit8: /* 0xdc */ 11337/* File: arm/alt_stub.S */ 11338/* 11339 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11340 * any interesting requests and then jump to the real instruction 11341 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11342 */ 11343 .extern MterpCheckBefore 11344 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11345 adrl lr, artMterpAsmInstructionStart + (220 * 128) @ Addr of primary handler. 11346 mov r0, rSELF 11347 add r1, rFP, #OFF_FP_SHADOWFRAME 11348 mov r2, rPC 11349 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11350 11351/* ------------------------------ */ 11352 .balign 128 11353.L_ALT_op_and_int_lit8: /* 0xdd */ 11354/* File: arm/alt_stub.S */ 11355/* 11356 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11357 * any interesting requests and then jump to the real instruction 11358 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11359 */ 11360 .extern MterpCheckBefore 11361 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11362 adrl lr, artMterpAsmInstructionStart + (221 * 128) @ Addr of primary handler. 11363 mov r0, rSELF 11364 add r1, rFP, #OFF_FP_SHADOWFRAME 11365 mov r2, rPC 11366 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11367 11368/* ------------------------------ */ 11369 .balign 128 11370.L_ALT_op_or_int_lit8: /* 0xde */ 11371/* File: arm/alt_stub.S */ 11372/* 11373 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11374 * any interesting requests and then jump to the real instruction 11375 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11376 */ 11377 .extern MterpCheckBefore 11378 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11379 adrl lr, artMterpAsmInstructionStart + (222 * 128) @ Addr of primary handler. 11380 mov r0, rSELF 11381 add r1, rFP, #OFF_FP_SHADOWFRAME 11382 mov r2, rPC 11383 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11384 11385/* ------------------------------ */ 11386 .balign 128 11387.L_ALT_op_xor_int_lit8: /* 0xdf */ 11388/* File: arm/alt_stub.S */ 11389/* 11390 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11391 * any interesting requests and then jump to the real instruction 11392 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11393 */ 11394 .extern MterpCheckBefore 11395 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11396 adrl lr, artMterpAsmInstructionStart + (223 * 128) @ Addr of primary handler. 11397 mov r0, rSELF 11398 add r1, rFP, #OFF_FP_SHADOWFRAME 11399 mov r2, rPC 11400 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11401 11402/* ------------------------------ */ 11403 .balign 128 11404.L_ALT_op_shl_int_lit8: /* 0xe0 */ 11405/* File: arm/alt_stub.S */ 11406/* 11407 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11408 * any interesting requests and then jump to the real instruction 11409 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11410 */ 11411 .extern MterpCheckBefore 11412 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11413 adrl lr, artMterpAsmInstructionStart + (224 * 128) @ Addr of primary handler. 11414 mov r0, rSELF 11415 add r1, rFP, #OFF_FP_SHADOWFRAME 11416 mov r2, rPC 11417 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11418 11419/* ------------------------------ */ 11420 .balign 128 11421.L_ALT_op_shr_int_lit8: /* 0xe1 */ 11422/* File: arm/alt_stub.S */ 11423/* 11424 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11425 * any interesting requests and then jump to the real instruction 11426 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11427 */ 11428 .extern MterpCheckBefore 11429 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11430 adrl lr, artMterpAsmInstructionStart + (225 * 128) @ Addr of primary handler. 11431 mov r0, rSELF 11432 add r1, rFP, #OFF_FP_SHADOWFRAME 11433 mov r2, rPC 11434 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11435 11436/* ------------------------------ */ 11437 .balign 128 11438.L_ALT_op_ushr_int_lit8: /* 0xe2 */ 11439/* File: arm/alt_stub.S */ 11440/* 11441 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11442 * any interesting requests and then jump to the real instruction 11443 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11444 */ 11445 .extern MterpCheckBefore 11446 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11447 adrl lr, artMterpAsmInstructionStart + (226 * 128) @ Addr of primary handler. 11448 mov r0, rSELF 11449 add r1, rFP, #OFF_FP_SHADOWFRAME 11450 mov r2, rPC 11451 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11452 11453/* ------------------------------ */ 11454 .balign 128 11455.L_ALT_op_iget_quick: /* 0xe3 */ 11456/* File: arm/alt_stub.S */ 11457/* 11458 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11459 * any interesting requests and then jump to the real instruction 11460 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11461 */ 11462 .extern MterpCheckBefore 11463 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11464 adrl lr, artMterpAsmInstructionStart + (227 * 128) @ Addr of primary handler. 11465 mov r0, rSELF 11466 add r1, rFP, #OFF_FP_SHADOWFRAME 11467 mov r2, rPC 11468 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11469 11470/* ------------------------------ */ 11471 .balign 128 11472.L_ALT_op_iget_wide_quick: /* 0xe4 */ 11473/* File: arm/alt_stub.S */ 11474/* 11475 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11476 * any interesting requests and then jump to the real instruction 11477 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11478 */ 11479 .extern MterpCheckBefore 11480 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11481 adrl lr, artMterpAsmInstructionStart + (228 * 128) @ Addr of primary handler. 11482 mov r0, rSELF 11483 add r1, rFP, #OFF_FP_SHADOWFRAME 11484 mov r2, rPC 11485 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11486 11487/* ------------------------------ */ 11488 .balign 128 11489.L_ALT_op_iget_object_quick: /* 0xe5 */ 11490/* File: arm/alt_stub.S */ 11491/* 11492 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11493 * any interesting requests and then jump to the real instruction 11494 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11495 */ 11496 .extern MterpCheckBefore 11497 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11498 adrl lr, artMterpAsmInstructionStart + (229 * 128) @ Addr of primary handler. 11499 mov r0, rSELF 11500 add r1, rFP, #OFF_FP_SHADOWFRAME 11501 mov r2, rPC 11502 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11503 11504/* ------------------------------ */ 11505 .balign 128 11506.L_ALT_op_iput_quick: /* 0xe6 */ 11507/* File: arm/alt_stub.S */ 11508/* 11509 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11510 * any interesting requests and then jump to the real instruction 11511 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11512 */ 11513 .extern MterpCheckBefore 11514 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11515 adrl lr, artMterpAsmInstructionStart + (230 * 128) @ Addr of primary handler. 11516 mov r0, rSELF 11517 add r1, rFP, #OFF_FP_SHADOWFRAME 11518 mov r2, rPC 11519 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11520 11521/* ------------------------------ */ 11522 .balign 128 11523.L_ALT_op_iput_wide_quick: /* 0xe7 */ 11524/* File: arm/alt_stub.S */ 11525/* 11526 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11527 * any interesting requests and then jump to the real instruction 11528 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11529 */ 11530 .extern MterpCheckBefore 11531 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11532 adrl lr, artMterpAsmInstructionStart + (231 * 128) @ Addr of primary handler. 11533 mov r0, rSELF 11534 add r1, rFP, #OFF_FP_SHADOWFRAME 11535 mov r2, rPC 11536 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11537 11538/* ------------------------------ */ 11539 .balign 128 11540.L_ALT_op_iput_object_quick: /* 0xe8 */ 11541/* File: arm/alt_stub.S */ 11542/* 11543 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11544 * any interesting requests and then jump to the real instruction 11545 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11546 */ 11547 .extern MterpCheckBefore 11548 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11549 adrl lr, artMterpAsmInstructionStart + (232 * 128) @ Addr of primary handler. 11550 mov r0, rSELF 11551 add r1, rFP, #OFF_FP_SHADOWFRAME 11552 mov r2, rPC 11553 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11554 11555/* ------------------------------ */ 11556 .balign 128 11557.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ 11558/* File: arm/alt_stub.S */ 11559/* 11560 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11561 * any interesting requests and then jump to the real instruction 11562 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11563 */ 11564 .extern MterpCheckBefore 11565 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11566 adrl lr, artMterpAsmInstructionStart + (233 * 128) @ Addr of primary handler. 11567 mov r0, rSELF 11568 add r1, rFP, #OFF_FP_SHADOWFRAME 11569 mov r2, rPC 11570 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11571 11572/* ------------------------------ */ 11573 .balign 128 11574.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ 11575/* File: arm/alt_stub.S */ 11576/* 11577 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11578 * any interesting requests and then jump to the real instruction 11579 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11580 */ 11581 .extern MterpCheckBefore 11582 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11583 adrl lr, artMterpAsmInstructionStart + (234 * 128) @ Addr of primary handler. 11584 mov r0, rSELF 11585 add r1, rFP, #OFF_FP_SHADOWFRAME 11586 mov r2, rPC 11587 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11588 11589/* ------------------------------ */ 11590 .balign 128 11591.L_ALT_op_iput_boolean_quick: /* 0xeb */ 11592/* File: arm/alt_stub.S */ 11593/* 11594 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11595 * any interesting requests and then jump to the real instruction 11596 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11597 */ 11598 .extern MterpCheckBefore 11599 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11600 adrl lr, artMterpAsmInstructionStart + (235 * 128) @ Addr of primary handler. 11601 mov r0, rSELF 11602 add r1, rFP, #OFF_FP_SHADOWFRAME 11603 mov r2, rPC 11604 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11605 11606/* ------------------------------ */ 11607 .balign 128 11608.L_ALT_op_iput_byte_quick: /* 0xec */ 11609/* File: arm/alt_stub.S */ 11610/* 11611 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11612 * any interesting requests and then jump to the real instruction 11613 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11614 */ 11615 .extern MterpCheckBefore 11616 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11617 adrl lr, artMterpAsmInstructionStart + (236 * 128) @ Addr of primary handler. 11618 mov r0, rSELF 11619 add r1, rFP, #OFF_FP_SHADOWFRAME 11620 mov r2, rPC 11621 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11622 11623/* ------------------------------ */ 11624 .balign 128 11625.L_ALT_op_iput_char_quick: /* 0xed */ 11626/* File: arm/alt_stub.S */ 11627/* 11628 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11629 * any interesting requests and then jump to the real instruction 11630 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11631 */ 11632 .extern MterpCheckBefore 11633 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11634 adrl lr, artMterpAsmInstructionStart + (237 * 128) @ Addr of primary handler. 11635 mov r0, rSELF 11636 add r1, rFP, #OFF_FP_SHADOWFRAME 11637 mov r2, rPC 11638 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11639 11640/* ------------------------------ */ 11641 .balign 128 11642.L_ALT_op_iput_short_quick: /* 0xee */ 11643/* File: arm/alt_stub.S */ 11644/* 11645 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11646 * any interesting requests and then jump to the real instruction 11647 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11648 */ 11649 .extern MterpCheckBefore 11650 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11651 adrl lr, artMterpAsmInstructionStart + (238 * 128) @ Addr of primary handler. 11652 mov r0, rSELF 11653 add r1, rFP, #OFF_FP_SHADOWFRAME 11654 mov r2, rPC 11655 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11656 11657/* ------------------------------ */ 11658 .balign 128 11659.L_ALT_op_iget_boolean_quick: /* 0xef */ 11660/* File: arm/alt_stub.S */ 11661/* 11662 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11663 * any interesting requests and then jump to the real instruction 11664 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11665 */ 11666 .extern MterpCheckBefore 11667 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11668 adrl lr, artMterpAsmInstructionStart + (239 * 128) @ Addr of primary handler. 11669 mov r0, rSELF 11670 add r1, rFP, #OFF_FP_SHADOWFRAME 11671 mov r2, rPC 11672 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11673 11674/* ------------------------------ */ 11675 .balign 128 11676.L_ALT_op_iget_byte_quick: /* 0xf0 */ 11677/* File: arm/alt_stub.S */ 11678/* 11679 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11680 * any interesting requests and then jump to the real instruction 11681 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11682 */ 11683 .extern MterpCheckBefore 11684 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11685 adrl lr, artMterpAsmInstructionStart + (240 * 128) @ Addr of primary handler. 11686 mov r0, rSELF 11687 add r1, rFP, #OFF_FP_SHADOWFRAME 11688 mov r2, rPC 11689 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11690 11691/* ------------------------------ */ 11692 .balign 128 11693.L_ALT_op_iget_char_quick: /* 0xf1 */ 11694/* File: arm/alt_stub.S */ 11695/* 11696 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11697 * any interesting requests and then jump to the real instruction 11698 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11699 */ 11700 .extern MterpCheckBefore 11701 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11702 adrl lr, artMterpAsmInstructionStart + (241 * 128) @ Addr of primary handler. 11703 mov r0, rSELF 11704 add r1, rFP, #OFF_FP_SHADOWFRAME 11705 mov r2, rPC 11706 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11707 11708/* ------------------------------ */ 11709 .balign 128 11710.L_ALT_op_iget_short_quick: /* 0xf2 */ 11711/* File: arm/alt_stub.S */ 11712/* 11713 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11714 * any interesting requests and then jump to the real instruction 11715 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11716 */ 11717 .extern MterpCheckBefore 11718 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11719 adrl lr, artMterpAsmInstructionStart + (242 * 128) @ Addr of primary handler. 11720 mov r0, rSELF 11721 add r1, rFP, #OFF_FP_SHADOWFRAME 11722 mov r2, rPC 11723 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11724 11725/* ------------------------------ */ 11726 .balign 128 11727.L_ALT_op_unused_f3: /* 0xf3 */ 11728/* File: arm/alt_stub.S */ 11729/* 11730 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11731 * any interesting requests and then jump to the real instruction 11732 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11733 */ 11734 .extern MterpCheckBefore 11735 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11736 adrl lr, artMterpAsmInstructionStart + (243 * 128) @ Addr of primary handler. 11737 mov r0, rSELF 11738 add r1, rFP, #OFF_FP_SHADOWFRAME 11739 mov r2, rPC 11740 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11741 11742/* ------------------------------ */ 11743 .balign 128 11744.L_ALT_op_unused_f4: /* 0xf4 */ 11745/* File: arm/alt_stub.S */ 11746/* 11747 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11748 * any interesting requests and then jump to the real instruction 11749 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11750 */ 11751 .extern MterpCheckBefore 11752 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11753 adrl lr, artMterpAsmInstructionStart + (244 * 128) @ Addr of primary handler. 11754 mov r0, rSELF 11755 add r1, rFP, #OFF_FP_SHADOWFRAME 11756 mov r2, rPC 11757 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11758 11759/* ------------------------------ */ 11760 .balign 128 11761.L_ALT_op_unused_f5: /* 0xf5 */ 11762/* File: arm/alt_stub.S */ 11763/* 11764 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11765 * any interesting requests and then jump to the real instruction 11766 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11767 */ 11768 .extern MterpCheckBefore 11769 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11770 adrl lr, artMterpAsmInstructionStart + (245 * 128) @ Addr of primary handler. 11771 mov r0, rSELF 11772 add r1, rFP, #OFF_FP_SHADOWFRAME 11773 mov r2, rPC 11774 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11775 11776/* ------------------------------ */ 11777 .balign 128 11778.L_ALT_op_unused_f6: /* 0xf6 */ 11779/* File: arm/alt_stub.S */ 11780/* 11781 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11782 * any interesting requests and then jump to the real instruction 11783 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11784 */ 11785 .extern MterpCheckBefore 11786 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11787 adrl lr, artMterpAsmInstructionStart + (246 * 128) @ Addr of primary handler. 11788 mov r0, rSELF 11789 add r1, rFP, #OFF_FP_SHADOWFRAME 11790 mov r2, rPC 11791 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11792 11793/* ------------------------------ */ 11794 .balign 128 11795.L_ALT_op_unused_f7: /* 0xf7 */ 11796/* File: arm/alt_stub.S */ 11797/* 11798 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11799 * any interesting requests and then jump to the real instruction 11800 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11801 */ 11802 .extern MterpCheckBefore 11803 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11804 adrl lr, artMterpAsmInstructionStart + (247 * 128) @ Addr of primary handler. 11805 mov r0, rSELF 11806 add r1, rFP, #OFF_FP_SHADOWFRAME 11807 mov r2, rPC 11808 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11809 11810/* ------------------------------ */ 11811 .balign 128 11812.L_ALT_op_unused_f8: /* 0xf8 */ 11813/* File: arm/alt_stub.S */ 11814/* 11815 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11816 * any interesting requests and then jump to the real instruction 11817 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11818 */ 11819 .extern MterpCheckBefore 11820 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11821 adrl lr, artMterpAsmInstructionStart + (248 * 128) @ Addr of primary handler. 11822 mov r0, rSELF 11823 add r1, rFP, #OFF_FP_SHADOWFRAME 11824 mov r2, rPC 11825 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11826 11827/* ------------------------------ */ 11828 .balign 128 11829.L_ALT_op_unused_f9: /* 0xf9 */ 11830/* File: arm/alt_stub.S */ 11831/* 11832 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11833 * any interesting requests and then jump to the real instruction 11834 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11835 */ 11836 .extern MterpCheckBefore 11837 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11838 adrl lr, artMterpAsmInstructionStart + (249 * 128) @ Addr of primary handler. 11839 mov r0, rSELF 11840 add r1, rFP, #OFF_FP_SHADOWFRAME 11841 mov r2, rPC 11842 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11843 11844/* ------------------------------ */ 11845 .balign 128 11846.L_ALT_op_invoke_polymorphic: /* 0xfa */ 11847/* File: arm/alt_stub.S */ 11848/* 11849 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11850 * any interesting requests and then jump to the real instruction 11851 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11852 */ 11853 .extern MterpCheckBefore 11854 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11855 adrl lr, artMterpAsmInstructionStart + (250 * 128) @ Addr of primary handler. 11856 mov r0, rSELF 11857 add r1, rFP, #OFF_FP_SHADOWFRAME 11858 mov r2, rPC 11859 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11860 11861/* ------------------------------ */ 11862 .balign 128 11863.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ 11864/* File: arm/alt_stub.S */ 11865/* 11866 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11867 * any interesting requests and then jump to the real instruction 11868 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11869 */ 11870 .extern MterpCheckBefore 11871 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11872 adrl lr, artMterpAsmInstructionStart + (251 * 128) @ Addr of primary handler. 11873 mov r0, rSELF 11874 add r1, rFP, #OFF_FP_SHADOWFRAME 11875 mov r2, rPC 11876 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11877 11878/* ------------------------------ */ 11879 .balign 128 11880.L_ALT_op_invoke_custom: /* 0xfc */ 11881/* File: arm/alt_stub.S */ 11882/* 11883 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11884 * any interesting requests and then jump to the real instruction 11885 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11886 */ 11887 .extern MterpCheckBefore 11888 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11889 adrl lr, artMterpAsmInstructionStart + (252 * 128) @ Addr of primary handler. 11890 mov r0, rSELF 11891 add r1, rFP, #OFF_FP_SHADOWFRAME 11892 mov r2, rPC 11893 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11894 11895/* ------------------------------ */ 11896 .balign 128 11897.L_ALT_op_invoke_custom_range: /* 0xfd */ 11898/* File: arm/alt_stub.S */ 11899/* 11900 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11901 * any interesting requests and then jump to the real instruction 11902 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11903 */ 11904 .extern MterpCheckBefore 11905 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11906 adrl lr, artMterpAsmInstructionStart + (253 * 128) @ Addr of primary handler. 11907 mov r0, rSELF 11908 add r1, rFP, #OFF_FP_SHADOWFRAME 11909 mov r2, rPC 11910 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11911 11912/* ------------------------------ */ 11913 .balign 128 11914.L_ALT_op_const_method_handle: /* 0xfe */ 11915/* File: arm/alt_stub.S */ 11916/* 11917 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11918 * any interesting requests and then jump to the real instruction 11919 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11920 */ 11921 .extern MterpCheckBefore 11922 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11923 adrl lr, artMterpAsmInstructionStart + (254 * 128) @ Addr of primary handler. 11924 mov r0, rSELF 11925 add r1, rFP, #OFF_FP_SHADOWFRAME 11926 mov r2, rPC 11927 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11928 11929/* ------------------------------ */ 11930 .balign 128 11931.L_ALT_op_const_method_type: /* 0xff */ 11932/* File: arm/alt_stub.S */ 11933/* 11934 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11935 * any interesting requests and then jump to the real instruction 11936 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11937 */ 11938 .extern MterpCheckBefore 11939 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11940 adrl lr, artMterpAsmInstructionStart + (255 * 128) @ Addr of primary handler. 11941 mov r0, rSELF 11942 add r1, rFP, #OFF_FP_SHADOWFRAME 11943 mov r2, rPC 11944 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11945 11946 .balign 128 11947 .global artMterpAsmAltInstructionEnd 11948artMterpAsmAltInstructionEnd: 11949/* File: arm/footer.S */ 11950/* 11951 * =========================================================================== 11952 * Common subroutines and data 11953 * =========================================================================== 11954 */ 11955 11956 .text 11957 .align 2 11958 11959/* 11960 * We've detected a condition that will result in an exception, but the exception 11961 * has not yet been thrown. Just bail out to the reference interpreter to deal with it. 11962 * TUNING: for consistency, we may want to just go ahead and handle these here. 11963 */ 11964common_errDivideByZero: 11965 EXPORT_PC 11966#if MTERP_LOGGING 11967 mov r0, rSELF 11968 add r1, rFP, #OFF_FP_SHADOWFRAME 11969 bl MterpLogDivideByZeroException 11970#endif 11971 b MterpCommonFallback 11972 11973common_errArrayIndex: 11974 EXPORT_PC 11975#if MTERP_LOGGING 11976 mov r0, rSELF 11977 add r1, rFP, #OFF_FP_SHADOWFRAME 11978 bl MterpLogArrayIndexException 11979#endif 11980 b MterpCommonFallback 11981 11982common_errNegativeArraySize: 11983 EXPORT_PC 11984#if MTERP_LOGGING 11985 mov r0, rSELF 11986 add r1, rFP, #OFF_FP_SHADOWFRAME 11987 bl MterpLogNegativeArraySizeException 11988#endif 11989 b MterpCommonFallback 11990 11991common_errNoSuchMethod: 11992 EXPORT_PC 11993#if MTERP_LOGGING 11994 mov r0, rSELF 11995 add r1, rFP, #OFF_FP_SHADOWFRAME 11996 bl MterpLogNoSuchMethodException 11997#endif 11998 b MterpCommonFallback 11999 12000common_errNullObject: 12001 EXPORT_PC 12002#if MTERP_LOGGING 12003 mov r0, rSELF 12004 add r1, rFP, #OFF_FP_SHADOWFRAME 12005 bl MterpLogNullObjectException 12006#endif 12007 b MterpCommonFallback 12008 12009common_exceptionThrown: 12010 EXPORT_PC 12011#if MTERP_LOGGING 12012 mov r0, rSELF 12013 add r1, rFP, #OFF_FP_SHADOWFRAME 12014 bl MterpLogExceptionThrownException 12015#endif 12016 b MterpCommonFallback 12017 12018MterpSuspendFallback: 12019 EXPORT_PC 12020#if MTERP_LOGGING 12021 mov r0, rSELF 12022 add r1, rFP, #OFF_FP_SHADOWFRAME 12023 ldr r2, [rSELF, #THREAD_FLAGS_OFFSET] 12024 bl MterpLogSuspendFallback 12025#endif 12026 b MterpCommonFallback 12027 12028/* 12029 * If we're here, something is out of the ordinary. If there is a pending 12030 * exception, handle it. Otherwise, roll back and retry with the reference 12031 * interpreter. 12032 */ 12033MterpPossibleException: 12034 ldr r0, [rSELF, #THREAD_EXCEPTION_OFFSET] 12035 cmp r0, #0 @ Exception pending? 12036 beq MterpFallback @ If not, fall back to reference interpreter. 12037 /* intentional fallthrough - handle pending exception. */ 12038/* 12039 * On return from a runtime helper routine, we've found a pending exception. 12040 * Can we handle it here - or need to bail out to caller? 12041 * 12042 */ 12043MterpException: 12044 mov r0, rSELF 12045 add r1, rFP, #OFF_FP_SHADOWFRAME 12046 bl MterpHandleException @ (self, shadow_frame) 12047 cmp r0, #0 12048 beq MterpExceptionReturn @ no local catch, back to caller. 12049 ldr r0, [rFP, #OFF_FP_DEX_INSTRUCTIONS] 12050 ldr r1, [rFP, #OFF_FP_DEX_PC] 12051 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] 12052 add rPC, r0, r1, lsl #1 @ generate new dex_pc_ptr 12053 /* Do we need to switch interpreters? */ 12054 bl MterpShouldSwitchInterpreters 12055 cmp r0, #0 12056 bne MterpFallback 12057 /* resume execution at catch block */ 12058 EXPORT_PC 12059 FETCH_INST 12060 GET_INST_OPCODE ip 12061 GOTO_OPCODE ip 12062 /* NOTE: no fallthrough */ 12063 12064/* 12065 * Common handling for branches with support for Jit profiling. 12066 * On entry: 12067 * rINST <= signed offset 12068 * rPROFILE <= signed hotness countdown (expanded to 32 bits) 12069 * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) 12070 * 12071 * We have quite a few different cases for branch profiling, OSR detection and 12072 * suspend check support here. 12073 * 12074 * Taken backward branches: 12075 * If profiling active, do hotness countdown and report if we hit zero. 12076 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 12077 * Is there a pending suspend request? If so, suspend. 12078 * 12079 * Taken forward branches and not-taken backward branches: 12080 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 12081 * 12082 * Our most common case is expected to be a taken backward branch with active jit profiling, 12083 * but no full OSR check and no pending suspend request. 12084 * Next most common case is not-taken branch with no full OSR check. 12085 * 12086 */ 12087MterpCommonTakenBranchNoFlags: 12088 cmp rINST, #0 12089MterpCommonTakenBranch: 12090 bgt .L_forward_branch @ don't add forward branches to hotness 12091/* 12092 * We need to subtract 1 from positive values and we should not see 0 here, 12093 * so we may use the result of the comparison with -1. 12094 */ 12095#if JIT_CHECK_OSR != -1 12096# error "JIT_CHECK_OSR must be -1." 12097#endif 12098 cmp rPROFILE, #JIT_CHECK_OSR 12099 beq .L_osr_check 12100 subgts rPROFILE, #1 12101 beq .L_add_batch @ counted down to zero - report 12102.L_resume_backward_branch: 12103 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 12104 REFRESH_IBASE 12105 add r2, rINST, rINST @ r2<- byte offset 12106 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST 12107 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 12108 bne .L_suspend_request_pending 12109 GET_INST_OPCODE ip @ extract opcode from rINST 12110 GOTO_OPCODE ip @ jump to next instruction 12111 12112.L_suspend_request_pending: 12113 EXPORT_PC 12114 mov r0, rSELF 12115 bl MterpSuspendCheck @ (self) 12116 cmp r0, #0 12117 bne MterpFallback 12118 REFRESH_IBASE @ might have changed during suspend 12119 GET_INST_OPCODE ip @ extract opcode from rINST 12120 GOTO_OPCODE ip @ jump to next instruction 12121 12122.L_no_count_backwards: 12123 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 12124 bne .L_resume_backward_branch 12125.L_osr_check: 12126 mov r0, rSELF 12127 add r1, rFP, #OFF_FP_SHADOWFRAME 12128 mov r2, rINST 12129 EXPORT_PC 12130 bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) 12131 cmp r0, #0 12132 bne MterpOnStackReplacement 12133 b .L_resume_backward_branch 12134 12135.L_forward_branch: 12136 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 12137 beq .L_check_osr_forward 12138.L_resume_forward_branch: 12139 add r2, rINST, rINST @ r2<- byte offset 12140 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST 12141 GET_INST_OPCODE ip @ extract opcode from rINST 12142 GOTO_OPCODE ip @ jump to next instruction 12143 12144.L_check_osr_forward: 12145 mov r0, rSELF 12146 add r1, rFP, #OFF_FP_SHADOWFRAME 12147 mov r2, rINST 12148 EXPORT_PC 12149 bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) 12150 cmp r0, #0 12151 bne MterpOnStackReplacement 12152 b .L_resume_forward_branch 12153 12154.L_add_batch: 12155 add r1, rFP, #OFF_FP_SHADOWFRAME 12156 strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] 12157 ldr r0, [rFP, #OFF_FP_METHOD] 12158 mov r2, rSELF 12159 bl MterpAddHotnessBatch @ (method, shadow_frame, self) 12160 mov rPROFILE, r0 @ restore new hotness countdown to rPROFILE 12161 b .L_no_count_backwards 12162 12163/* 12164 * Entered from the conditional branch handlers when OSR check request active on 12165 * not-taken path. All Dalvik not-taken conditional branch offsets are 2. 12166 */ 12167.L_check_not_taken_osr: 12168 mov r0, rSELF 12169 add r1, rFP, #OFF_FP_SHADOWFRAME 12170 mov r2, #2 12171 EXPORT_PC 12172 bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) 12173 cmp r0, #0 12174 bne MterpOnStackReplacement 12175 FETCH_ADVANCE_INST 2 12176 GET_INST_OPCODE ip @ extract opcode from rINST 12177 GOTO_OPCODE ip @ jump to next instruction 12178 12179/* 12180 * On-stack replacement has happened, and now we've returned from the compiled method. 12181 */ 12182MterpOnStackReplacement: 12183#if MTERP_LOGGING 12184 mov r0, rSELF 12185 add r1, rFP, #OFF_FP_SHADOWFRAME 12186 mov r2, rINST 12187 bl MterpLogOSR 12188#endif 12189 mov r0, #1 @ Signal normal return 12190 b MterpDone 12191 12192/* 12193 * Bail out to reference interpreter. 12194 */ 12195MterpFallback: 12196 EXPORT_PC 12197#if MTERP_LOGGING 12198 mov r0, rSELF 12199 add r1, rFP, #OFF_FP_SHADOWFRAME 12200 bl MterpLogFallback 12201#endif 12202MterpCommonFallback: 12203 mov r0, #0 @ signal retry with reference interpreter. 12204 b MterpDone 12205 12206/* 12207 * We pushed some registers on the stack in ExecuteMterpImpl, then saved 12208 * SP and LR. Here we restore SP, restore the registers, and then restore 12209 * LR to PC. 12210 * 12211 * On entry: 12212 * uint32_t* rFP (should still be live, pointer to base of vregs) 12213 */ 12214MterpExceptionReturn: 12215 mov r0, #1 @ signal return to caller. 12216 b MterpDone 12217MterpReturn: 12218 ldr r2, [rFP, #OFF_FP_RESULT_REGISTER] 12219 str r0, [r2] 12220 str r1, [r2, #4] 12221 mov r0, #1 @ signal return to caller. 12222MterpDone: 12223/* 12224 * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're 12225 * checking for OSR. If greater than zero, we might have unreported hotness to register 12226 * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE 12227 * should only reach zero immediately after a hotness decrement, and is then reset to either 12228 * a negative special state or the new non-zero countdown value. 12229 */ 12230 cmp rPROFILE, #0 12231 bgt MterpProfileActive @ if > 0, we may have some counts to report. 12232 ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return 12233 12234MterpProfileActive: 12235 mov rINST, r0 @ stash return value 12236 /* Report cached hotness counts */ 12237 ldr r0, [rFP, #OFF_FP_METHOD] 12238 add r1, rFP, #OFF_FP_SHADOWFRAME 12239 mov r2, rSELF 12240 strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] 12241 bl MterpAddHotnessBatch @ (method, shadow_frame, self) 12242 mov r0, rINST @ restore return value 12243 ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return 12244 12245 END ExecuteMterpImpl 12246 12247 12248