1VIXL Supported Instruction List 2=============================== 3 4This is a list of the AArch64 instructions supported by the VIXL assembler, 5disassembler and simulator. The simulator may not support all floating point 6operations to the precision required by AArch64 - please check the simulator 7source code for details. 8 9AArch64 integer instructions 10---------------------------- 11 12### ADC ### 13 14Add with carry bit. 15 16 void adc(const Register& rd, const Register& rn, const Operand& operand) 17 18 19### ADCS ### 20 21Add with carry bit and update status flags. 22 23 void adcs(const Register& rd, const Register& rn, const Operand& operand) 24 25 26### ADD ### 27 28Add. 29 30 void add(const Register& rd, const Register& rn, const Operand& operand) 31 32 33### ADDS ### 34 35Add and update status flags. 36 37 void adds(const Register& rd, const Register& rn, const Operand& operand) 38 39 40### ADR ### 41 42Calculate the address of a PC offset. 43 44 void adr(const Register& xd, int64_t imm21) 45 46 47### ADR ### 48 49Calculate the address of a label. 50 51 void adr(const Register& xd, Label* label) 52 53 54### ADRP ### 55 56Calculate the page address of a PC offset. 57 58 void adrp(const Register& xd, int64_t imm21) 59 60 61### ADRP ### 62 63Calculate the page address of a label. 64 65 void adrp(const Register& xd, Label* label) 66 67 68### AND ### 69 70Bitwise and (A & B). 71 72 void and_(const Register& rd, const Register& rn, const Operand& operand) 73 74 75### ANDS ### 76 77Bitwise and (A & B) and update status flags. 78 79 void ands(const Register& rd, const Register& rn, const Operand& operand) 80 81 82### ASR ### 83 84Arithmetic shift right. 85 86 void asr(const Register& rd, const Register& rn, unsigned shift) 87 88 89### ASRV ### 90 91Arithmetic shift right by variable. 92 93 void asrv(const Register& rd, const Register& rn, const Register& rm) 94 95 96### B ### 97 98Conditional branch to PC offset. 99 100 void b(int64_t imm19, Condition cond) 101 102 103### B ### 104 105Conditional branch to label. 106 107 void b(Label* label, Condition cond) 108 109 110### B ### 111 112Unconditional branch to PC offset. 113 114 void b(int64_t imm26) 115 116 117### B ### 118 119Unconditional branch to label. 120 121 void b(Label* label) 122 123 124### BFI ### 125 126Bitfield insert. 127 128 void bfi(const Register& rd, 129 const Register& rn, 130 unsigned lsb, 131 unsigned width) 132 133 134### BFM ### 135 136Bitfield move. 137 138 void bfm(const Register& rd, 139 const Register& rn, 140 unsigned immr, 141 unsigned imms) 142 143 144### BFXIL ### 145 146Bitfield extract and insert low. 147 148 void bfxil(const Register& rd, 149 const Register& rn, 150 unsigned lsb, 151 unsigned width) 152 153 154### BIC ### 155 156Bit clear (A & ~B). 157 158 void bic(const Register& rd, const Register& rn, const Operand& operand) 159 160 161### BICS ### 162 163Bit clear (A & ~B) and update status flags. 164 165 void bics(const Register& rd, const Register& rn, const Operand& operand) 166 167 168### BL ### 169 170Branch with link to PC offset. 171 172 void bl(int64_t imm26) 173 174 175### BL ### 176 177Branch with link to label. 178 179 void bl(Label* label) 180 181 182### BLR ### 183 184Branch with link to register. 185 186 void blr(const Register& xn) 187 188 189### BR ### 190 191Branch to register. 192 193 void br(const Register& xn) 194 195 196### BRK ### 197 198Monitor debug-mode breakpoint. 199 200 void brk(int code) 201 202 203### CBNZ ### 204 205Compare and branch to PC offset if not zero. 206 207 void cbnz(const Register& rt, int64_t imm19) 208 209 210### CBNZ ### 211 212Compare and branch to label if not zero. 213 214 void cbnz(const Register& rt, Label* label) 215 216 217### CBZ ### 218 219Compare and branch to PC offset if zero. 220 221 void cbz(const Register& rt, int64_t imm19) 222 223 224### CBZ ### 225 226Compare and branch to label if zero. 227 228 void cbz(const Register& rt, Label* label) 229 230 231### CCMN ### 232 233Conditional compare negative. 234 235 void ccmn(const Register& rn, 236 const Operand& operand, 237 StatusFlags nzcv, 238 Condition cond) 239 240 241### CCMP ### 242 243Conditional compare. 244 245 void ccmp(const Register& rn, 246 const Operand& operand, 247 StatusFlags nzcv, 248 Condition cond) 249 250 251### CINC ### 252 253Conditional increment: rd = cond ? rn + 1 : rn. 254 255 void cinc(const Register& rd, const Register& rn, Condition cond) 256 257 258### CINV ### 259 260Conditional invert: rd = cond ? ~rn : rn. 261 262 void cinv(const Register& rd, const Register& rn, Condition cond) 263 264 265### CLREX ### 266 267Clear exclusive monitor. 268 269 void clrex(int imm4 = 0xf) 270 271 272### CLS ### 273 274Count leading sign bits. 275 276 void cls(const Register& rd, const Register& rn) 277 278 279### CLZ ### 280 281Count leading zeroes. 282 283 void clz(const Register& rd, const Register& rn) 284 285 286### CMN ### 287 288Compare negative. 289 290 void cmn(const Register& rn, const Operand& operand) 291 292 293### CMP ### 294 295Compare. 296 297 void cmp(const Register& rn, const Operand& operand) 298 299 300### CNEG ### 301 302Conditional negate: rd = cond ? -rn : rn. 303 304 void cneg(const Register& rd, const Register& rn, Condition cond) 305 306 307### CRC32B ### 308 309CRC-32 checksum from byte. 310 311 void crc32b(const Register& wd, const Register& wn, const Register& wm) 312 313 314### CRC32CB ### 315 316CRC-32 C checksum from byte. 317 318 void crc32cb(const Register& wd, const Register& wn, const Register& wm) 319 320 321### CRC32CH ### 322 323CRC-32 C checksum from half-word. 324 325 void crc32ch(const Register& wd, const Register& wn, const Register& wm) 326 327 328### CRC32CW ### 329 330CRC-32 C checksum from word. 331 332 void crc32cw(const Register& wd, const Register& wn, const Register& wm) 333 334 335### CRC32CX ### 336 337CRC-32C checksum from double word. 338 339 void crc32cx(const Register& wd, const Register& wn, const Register& xm) 340 341 342### CRC32H ### 343 344CRC-32 checksum from half-word. 345 346 void crc32h(const Register& wd, const Register& wn, const Register& wm) 347 348 349### CRC32W ### 350 351CRC-32 checksum from word. 352 353 void crc32w(const Register& wd, const Register& wn, const Register& wm) 354 355 356### CRC32X ### 357 358CRC-32 checksum from double word. 359 360 void crc32x(const Register& wd, const Register& wn, const Register& xm) 361 362 363### CSEL ### 364 365Conditional select: rd = cond ? rn : rm. 366 367 void csel(const Register& rd, 368 const Register& rn, 369 const Register& rm, 370 Condition cond) 371 372 373### CSET ### 374 375Conditional set: rd = cond ? 1 : 0. 376 377 void cset(const Register& rd, Condition cond) 378 379 380### CSETM ### 381 382Conditional set mask: rd = cond ? -1 : 0. 383 384 void csetm(const Register& rd, Condition cond) 385 386 387### CSINC ### 388 389Conditional select increment: rd = cond ? rn : rm + 1. 390 391 void csinc(const Register& rd, 392 const Register& rn, 393 const Register& rm, 394 Condition cond) 395 396 397### CSINV ### 398 399Conditional select inversion: rd = cond ? rn : ~rm. 400 401 void csinv(const Register& rd, 402 const Register& rn, 403 const Register& rm, 404 Condition cond) 405 406 407### CSNEG ### 408 409Conditional select negation: rd = cond ? rn : -rm. 410 411 void csneg(const Register& rd, 412 const Register& rn, 413 const Register& rm, 414 Condition cond) 415 416 417### DC ### 418 419 420 421 void dc(T data) 422 423 424### DC ### 425 426System data cache operation. 427 428 void dc(DataCacheOp op, const Register& rt) 429 430 431### DMB ### 432 433Data memory barrier. 434 435 void dmb(BarrierDomain domain, BarrierType type) 436 437 438### DSB ### 439 440Data synchronization barrier. 441 442 void dsb(BarrierDomain domain, BarrierType type) 443 444 445### EON ### 446 447Bitwise enor/xnor (A ^ ~B). 448 449 void eon(const Register& rd, const Register& rn, const Operand& operand) 450 451 452### EOR ### 453 454Bitwise eor/xor (A ^ B). 455 456 void eor(const Register& rd, const Register& rn, const Operand& operand) 457 458 459### EXTR ### 460 461Extract. 462 463 void extr(const Register& rd, 464 const Register& rn, 465 const Register& rm, 466 unsigned lsb) 467 468 469### HINT ### 470 471System hint. 472 473 void hint(SystemHint code) 474 475 476### HLT ### 477 478Halting debug-mode breakpoint. 479 480 void hlt(int code) 481 482 483### IC ### 484 485System instruction cache operation. 486 487 void ic(InstructionCacheOp op, const Register& rt) 488 489 490### ISB ### 491 492Instruction synchronization barrier. 493 494 void isb() 495 496 497### LDAR ### 498 499Load-acquire register. 500 501 void ldar(const Register& rt, const MemOperand& src) 502 503 504### LDARB ### 505 506Load-acquire byte. 507 508 void ldarb(const Register& rt, const MemOperand& src) 509 510 511### LDARH ### 512 513Load-acquire half-word. 514 515 void ldarh(const Register& rt, const MemOperand& src) 516 517 518### LDAXP ### 519 520Load-acquire exclusive register pair. 521 522 void ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) 523 524 525### LDAXR ### 526 527Load-acquire exclusive register. 528 529 void ldaxr(const Register& rt, const MemOperand& src) 530 531 532### LDAXRB ### 533 534Load-acquire exclusive byte. 535 536 void ldaxrb(const Register& rt, const MemOperand& src) 537 538 539### LDAXRH ### 540 541Load-acquire exclusive half-word. 542 543 void ldaxrh(const Register& rt, const MemOperand& src) 544 545 546### LDNP ### 547 548Load integer or FP register pair, non-temporal. 549 550 void ldnp(const CPURegister& rt, 551 const CPURegister& rt2, 552 const MemOperand& src) 553 554 555### LDP ### 556 557Load integer or FP register pair. 558 559 void ldp(const CPURegister& rt, 560 const CPURegister& rt2, 561 const MemOperand& src) 562 563 564### LDPSW ### 565 566Load word pair with sign extension. 567 568 void ldpsw(const Register& xt, const Register& xt2, const MemOperand& src) 569 570 571### LDR ### 572 573Load integer or FP register from literal pool. 574 575 void ldr(const CPURegister& rt, RawLiteral* literal) 576 577 578### LDR ### 579 580Load integer or FP register from pc + imm19 << 2. 581 582 void ldr(const CPURegister& rt, int64_t imm19) 583 584 585### LDR ### 586 587Load integer or FP register. 588 589 void ldr(const CPURegister& rt, 590 const MemOperand& src, 591 LoadStoreScalingOption option = PreferScaledOffset) 592 593 594### LDRB ### 595 596Load byte. 597 598 void ldrb(const Register& rt, 599 const MemOperand& src, 600 LoadStoreScalingOption option = PreferScaledOffset) 601 602 603### LDRH ### 604 605Load half-word. 606 607 void ldrh(const Register& rt, 608 const MemOperand& src, 609 LoadStoreScalingOption option = PreferScaledOffset) 610 611 612### LDRSB ### 613 614Load byte with sign extension. 615 616 void ldrsb(const Register& rt, 617 const MemOperand& src, 618 LoadStoreScalingOption option = PreferScaledOffset) 619 620 621### LDRSH ### 622 623Load half-word with sign extension. 624 625 void ldrsh(const Register& rt, 626 const MemOperand& src, 627 LoadStoreScalingOption option = PreferScaledOffset) 628 629 630### LDRSW ### 631 632Load word with sign extension from literal pool. 633 634 void ldrsw(const Register& xt, RawLiteral* literal) 635 636 637### LDRSW ### 638 639Load word with sign extension from pc + imm19 << 2. 640 641 void ldrsw(const Register& xt, int64_t imm19) 642 643 644### LDRSW ### 645 646Load word with sign extension. 647 648 void ldrsw(const Register& xt, 649 const MemOperand& src, 650 LoadStoreScalingOption option = PreferScaledOffset) 651 652 653### LDUR ### 654 655Load integer or FP register (with unscaled offset). 656 657 void ldur(const CPURegister& rt, 658 const MemOperand& src, 659 LoadStoreScalingOption option = PreferUnscaledOffset) 660 661 662### LDURB ### 663 664Load byte (with unscaled offset). 665 666 void ldurb(const Register& rt, 667 const MemOperand& src, 668 LoadStoreScalingOption option = PreferUnscaledOffset) 669 670 671### LDURH ### 672 673Load half-word (with unscaled offset). 674 675 void ldurh(const Register& rt, 676 const MemOperand& src, 677 LoadStoreScalingOption option = PreferUnscaledOffset) 678 679 680### LDURSB ### 681 682Load byte with sign extension (and unscaled offset). 683 684 void ldursb(const Register& rt, 685 const MemOperand& src, 686 LoadStoreScalingOption option = PreferUnscaledOffset) 687 688 689### LDURSH ### 690 691Load half-word with sign extension (and unscaled offset). 692 693 void ldursh(const Register& rt, 694 const MemOperand& src, 695 LoadStoreScalingOption option = PreferUnscaledOffset) 696 697 698### LDURSW ### 699 700Load word with sign extension. 701 702 void ldursw(const Register& xt, 703 const MemOperand& src, 704 LoadStoreScalingOption option = PreferUnscaledOffset) 705 706 707### LDXP ### 708 709Load exclusive register pair. 710 711 void ldxp(const Register& rt, const Register& rt2, const MemOperand& src) 712 713 714### LDXR ### 715 716Load exclusive register. 717 718 void ldxr(const Register& rt, const MemOperand& src) 719 720 721### LDXRB ### 722 723Load exclusive byte. 724 725 void ldxrb(const Register& rt, const MemOperand& src) 726 727 728### LDXRH ### 729 730Load exclusive half-word. 731 732 void ldxrh(const Register& rt, const MemOperand& src) 733 734 735### LSL ### 736 737Logical shift left. 738 739 void lsl(const Register& rd, const Register& rn, unsigned shift) 740 741 742### LSLV ### 743 744Logical shift left by variable. 745 746 void lslv(const Register& rd, const Register& rn, const Register& rm) 747 748 749### LSR ### 750 751Logical shift right. 752 753 void lsr(const Register& rd, const Register& rn, unsigned shift) 754 755 756### LSRV ### 757 758Logical shift right by variable. 759 760 void lsrv(const Register& rd, const Register& rn, const Register& rm) 761 762 763### MADD ### 764 765Multiply and accumulate. 766 767 void madd(const Register& rd, 768 const Register& rn, 769 const Register& rm, 770 const Register& ra) 771 772 773### MNEG ### 774 775Negated multiply. 776 777 void mneg(const Register& rd, const Register& rn, const Register& rm) 778 779 780### MOV ### 781 782Move register to register. 783 784 void mov(const Register& rd, const Register& rn) 785 786 787### MOVK ### 788 789Move immediate and keep. 790 791 void movk(const Register& rd, uint64_t imm, int shift = -1) 792 793 794### MOVN ### 795 796Move inverted immediate. 797 798 void movn(const Register& rd, uint64_t imm, int shift = -1) 799 800 801### MOVZ ### 802 803Move immediate. 804 805 void movz(const Register& rd, uint64_t imm, int shift = -1) 806 807 808### MRS ### 809 810Move to register from system register. 811 812 void mrs(const Register& xt, SystemRegister sysreg) 813 814 815### MSR ### 816 817Move from register to system register. 818 819 void msr(SystemRegister sysreg, const Register& xt) 820 821 822### MSUB ### 823 824Multiply and subtract. 825 826 void msub(const Register& rd, 827 const Register& rn, 828 const Register& rm, 829 const Register& ra) 830 831 832### MUL ### 833 834Multiply. 835 836 void mul(const Register& rd, const Register& rn, const Register& rm) 837 838 839### MVN ### 840 841Move inverted operand to register. 842 843 void mvn(const Register& rd, const Operand& operand) 844 845 846### NEG ### 847 848Negate. 849 850 void neg(const Register& rd, const Operand& operand) 851 852 853### NEGS ### 854 855Negate and update status flags. 856 857 void negs(const Register& rd, const Operand& operand) 858 859 860### NGC ### 861 862Negate with carry bit. 863 864 void ngc(const Register& rd, const Operand& operand) 865 866 867### NGCS ### 868 869Negate with carry bit and update status flags. 870 871 void ngcs(const Register& rd, const Operand& operand) 872 873 874### NOP ### 875 876No-op. 877 878 void nop() 879 880 881### ORN ### 882 883Bitwise nor (A | ~B). 884 885 void orn(const Register& rd, const Register& rn, const Operand& operand) 886 887 888### ORR ### 889 890Bitwise or (A | B). 891 892 void orr(const Register& rd, const Register& rn, const Operand& operand) 893 894 895### PRFM ### 896 897Prefetch from pc + imm19 << 2. 898 899 void prfm(PrefetchOperation op, int64_t imm19) 900 901 902### PRFM ### 903 904Prefetch memory in the literal pool. 905 906 void prfm(PrefetchOperation op, RawLiteral* literal) 907 908 909### PRFM ### 910 911Prefetch memory. 912 913 void prfm(PrefetchOperation op, 914 const MemOperand& addr, 915 LoadStoreScalingOption option = PreferScaledOffset) 916 917 918### PRFUM ### 919 920Prefetch memory (with unscaled offset). 921 922 void prfum(PrefetchOperation op, 923 const MemOperand& addr, 924 LoadStoreScalingOption option = PreferUnscaledOffset) 925 926 927### RBIT ### 928 929Bit reverse. 930 931 void rbit(const Register& rd, const Register& rn) 932 933 934### RET ### 935 936Branch to register with return hint. 937 938 void ret(const Register& xn = lr) 939 940 941### REV ### 942 943Reverse bytes. 944 945 void rev(const Register& rd, const Register& rn) 946 947 948### REV16 ### 949 950Reverse bytes in 16-bit half words. 951 952 void rev16(const Register& rd, const Register& rn) 953 954 955### REV32 ### 956 957Reverse bytes in 32-bit words. 958 959 void rev32(const Register& xd, const Register& xn) 960 961 962### ROR ### 963 964Rotate right. 965 966 void ror(const Register& rd, const Register& rs, unsigned shift) 967 968 969### RORV ### 970 971Rotate right by variable. 972 973 void rorv(const Register& rd, const Register& rn, const Register& rm) 974 975 976### SBC ### 977 978Subtract with carry bit. 979 980 void sbc(const Register& rd, const Register& rn, const Operand& operand) 981 982 983### SBCS ### 984 985Subtract with carry bit and update status flags. 986 987 void sbcs(const Register& rd, const Register& rn, const Operand& operand) 988 989 990### SBFIZ ### 991 992Signed bitfield insert with zero at right. 993 994 void sbfiz(const Register& rd, 995 const Register& rn, 996 unsigned lsb, 997 unsigned width) 998 999 1000### SBFM ### 1001 1002Signed bitfield move. 1003 1004 void sbfm(const Register& rd, 1005 const Register& rn, 1006 unsigned immr, 1007 unsigned imms) 1008 1009 1010### SBFX ### 1011 1012Signed bitfield extract. 1013 1014 void sbfx(const Register& rd, 1015 const Register& rn, 1016 unsigned lsb, 1017 unsigned width) 1018 1019 1020### SDIV ### 1021 1022Signed integer divide. 1023 1024 void sdiv(const Register& rd, const Register& rn, const Register& rm) 1025 1026 1027### SMADDL ### 1028 1029Signed long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 1030 1031 void smaddl(const Register& xd, 1032 const Register& wn, 1033 const Register& wm, 1034 const Register& xa) 1035 1036 1037### SMSUBL ### 1038 1039Signed long multiply and subtract: 64 - (32 x 32) -> 64-bit. 1040 1041 void smsubl(const Register& xd, 1042 const Register& wn, 1043 const Register& wm, 1044 const Register& xa) 1045 1046 1047### SMULH ### 1048 1049Signed multiply high: 64 x 64 -> 64-bit <127:64>. 1050 1051 void smulh(const Register& xd, const Register& xn, const Register& xm) 1052 1053 1054### SMULL ### 1055 1056Signed long multiply: 32 x 32 -> 64-bit. 1057 1058 void smull(const Register& xd, const Register& wn, const Register& wm) 1059 1060 1061### STLR ### 1062 1063Store-release register. 1064 1065 void stlr(const Register& rt, const MemOperand& dst) 1066 1067 1068### STLRB ### 1069 1070Store-release byte. 1071 1072 void stlrb(const Register& rt, const MemOperand& dst) 1073 1074 1075### STLRH ### 1076 1077Store-release half-word. 1078 1079 void stlrh(const Register& rt, const MemOperand& dst) 1080 1081 1082### STLXP ### 1083 1084Store-release exclusive register pair. 1085 1086 void stlxp(const Register& rs, 1087 const Register& rt, 1088 const Register& rt2, 1089 const MemOperand& dst) 1090 1091 1092### STLXR ### 1093 1094Store-release exclusive register. 1095 1096 void stlxr(const Register& rs, const Register& rt, const MemOperand& dst) 1097 1098 1099### STLXRB ### 1100 1101Store-release exclusive byte. 1102 1103 void stlxrb(const Register& rs, const Register& rt, const MemOperand& dst) 1104 1105 1106### STLXRH ### 1107 1108Store-release exclusive half-word. 1109 1110 void stlxrh(const Register& rs, const Register& rt, const MemOperand& dst) 1111 1112 1113### STNP ### 1114 1115Store integer or FP register pair, non-temporal. 1116 1117 void stnp(const CPURegister& rt, 1118 const CPURegister& rt2, 1119 const MemOperand& dst) 1120 1121 1122### STP ### 1123 1124Store integer or FP register pair. 1125 1126 void stp(const CPURegister& rt, 1127 const CPURegister& rt2, 1128 const MemOperand& dst) 1129 1130 1131### STR ### 1132 1133Store integer or FP register. 1134 1135 void str(const CPURegister& rt, 1136 const MemOperand& dst, 1137 LoadStoreScalingOption option = PreferScaledOffset) 1138 1139 1140### STRB ### 1141 1142Store byte. 1143 1144 void strb(const Register& rt, 1145 const MemOperand& dst, 1146 LoadStoreScalingOption option = PreferScaledOffset) 1147 1148 1149### STRH ### 1150 1151Store half-word. 1152 1153 void strh(const Register& rt, 1154 const MemOperand& dst, 1155 LoadStoreScalingOption option = PreferScaledOffset) 1156 1157 1158### STUR ### 1159 1160Store integer or FP register (with unscaled offset). 1161 1162 void stur(const CPURegister& rt, 1163 const MemOperand& src, 1164 LoadStoreScalingOption option = PreferUnscaledOffset) 1165 1166 1167### STURB ### 1168 1169Store byte (with unscaled offset). 1170 1171 void sturb(const Register& rt, 1172 const MemOperand& dst, 1173 LoadStoreScalingOption option = PreferUnscaledOffset) 1174 1175 1176### STURH ### 1177 1178Store half-word (with unscaled offset). 1179 1180 void sturh(const Register& rt, 1181 const MemOperand& dst, 1182 LoadStoreScalingOption option = PreferUnscaledOffset) 1183 1184 1185### STXP ### 1186 1187Store exclusive register pair. 1188 1189 void stxp(const Register& rs, 1190 const Register& rt, 1191 const Register& rt2, 1192 const MemOperand& dst) 1193 1194 1195### STXR ### 1196 1197Store exclusive register. 1198 1199 void stxr(const Register& rs, const Register& rt, const MemOperand& dst) 1200 1201 1202### STXRB ### 1203 1204Store exclusive byte. 1205 1206 void stxrb(const Register& rs, const Register& rt, const MemOperand& dst) 1207 1208 1209### STXRH ### 1210 1211Store exclusive half-word. 1212 1213 void stxrh(const Register& rs, const Register& rt, const MemOperand& dst) 1214 1215 1216### SUB ### 1217 1218Subtract. 1219 1220 void sub(const Register& rd, const Register& rn, const Operand& operand) 1221 1222 1223### SUBS ### 1224 1225Subtract and update status flags. 1226 1227 void subs(const Register& rd, const Register& rn, const Operand& operand) 1228 1229 1230### SVC ### 1231 1232Generate exception targeting EL1. 1233 1234 void svc(int code) 1235 1236 1237### SXTB ### 1238 1239Signed extend byte. 1240 1241 void sxtb(const Register& rd, const Register& rn) 1242 1243 1244### SXTH ### 1245 1246Signed extend halfword. 1247 1248 void sxth(const Register& rd, const Register& rn) 1249 1250 1251### SXTW ### 1252 1253Signed extend word. 1254 1255 void sxtw(const Register& rd, const Register& rn) 1256 1257 1258### SYS ### 1259 1260System instruction with pre-encoded op (op1:crn:crm:op2). 1261 1262 void sys(int op, const Register& xt = xzr) 1263 1264 1265### SYS ### 1266 1267System instruction. 1268 1269 void sys(int op1, int crn, int crm, int op2, const Register& xt = xzr) 1270 1271 1272### TBNZ ### 1273 1274Test bit and branch to PC offset if not zero. 1275 1276 void tbnz(const Register& rt, unsigned bit_pos, int64_t imm14) 1277 1278 1279### TBNZ ### 1280 1281Test bit and branch to label if not zero. 1282 1283 void tbnz(const Register& rt, unsigned bit_pos, Label* label) 1284 1285 1286### TBZ ### 1287 1288Test bit and branch to PC offset if zero. 1289 1290 void tbz(const Register& rt, unsigned bit_pos, int64_t imm14) 1291 1292 1293### TBZ ### 1294 1295Test bit and branch to label if zero. 1296 1297 void tbz(const Register& rt, unsigned bit_pos, Label* label) 1298 1299 1300### TST ### 1301 1302Bit test and set flags. 1303 1304 void tst(const Register& rn, const Operand& operand) 1305 1306 1307### UBFIZ ### 1308 1309Unsigned bitfield insert with zero at right. 1310 1311 void ubfiz(const Register& rd, 1312 const Register& rn, 1313 unsigned lsb, 1314 unsigned width) 1315 1316 1317### UBFM ### 1318 1319Unsigned bitfield move. 1320 1321 void ubfm(const Register& rd, 1322 const Register& rn, 1323 unsigned immr, 1324 unsigned imms) 1325 1326 1327### UBFX ### 1328 1329Unsigned bitfield extract. 1330 1331 void ubfx(const Register& rd, 1332 const Register& rn, 1333 unsigned lsb, 1334 unsigned width) 1335 1336 1337### UDIV ### 1338 1339Unsigned integer divide. 1340 1341 void udiv(const Register& rd, const Register& rn, const Register& rm) 1342 1343 1344### UMADDL ### 1345 1346Unsigned long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 1347 1348 void umaddl(const Register& xd, 1349 const Register& wn, 1350 const Register& wm, 1351 const Register& xa) 1352 1353 1354### UMSUBL ### 1355 1356Unsigned long multiply and subtract: 64 - (32 x 32) -> 64-bit. 1357 1358 void umsubl(const Register& xd, 1359 const Register& wn, 1360 const Register& wm, 1361 const Register& xa) 1362 1363 1364### UMULH ### 1365 1366Unsigned multiply high: 64 x 64 -> 64-bit <127:64>. 1367 1368 void umulh(const Register& xd, const Register& xn, const Register& xm) 1369 1370 1371### UMULL ### 1372 1373Unsigned long multiply: 32 x 32 -> 64-bit. 1374 1375 void umull(const Register& xd, const Register& wn, const Register& wm) 1376 1377 1378### UXTB ### 1379 1380Unsigned extend byte. 1381 1382 void uxtb(const Register& rd, const Register& rn) 1383 1384 1385### UXTH ### 1386 1387Unsigned extend halfword. 1388 1389 void uxth(const Register& rd, const Register& rn) 1390 1391 1392### UXTW ### 1393 1394Unsigned extend word. 1395 1396 void uxtw(const Register& rd, const Register& rn) 1397 1398 1399 1400AArch64 floating point and NEON instructions 1401-------------------------------------------- 1402 1403### ABS ### 1404 1405Absolute value. 1406 1407 void abs(const VRegister& vd, const VRegister& vn) 1408 1409 1410### ADD ### 1411 1412Add. 1413 1414 void add(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1415 1416 1417### ADDHN ### 1418 1419Add narrow returning high half. 1420 1421 void addhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1422 1423 1424### ADDHN2 ### 1425 1426Add narrow returning high half (second part). 1427 1428 void addhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1429 1430 1431### ADDP ### 1432 1433Add pair of elements scalar. 1434 1435 void addp(const VRegister& vd, const VRegister& vn) 1436 1437 1438### ADDP ### 1439 1440Add pairwise. 1441 1442 void addp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1443 1444 1445### ADDV ### 1446 1447Add across vector. 1448 1449 void addv(const VRegister& vd, const VRegister& vn) 1450 1451 1452### AND ### 1453 1454Bitwise and. 1455 1456 void and_(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1457 1458 1459### BIC ### 1460 1461Bit clear immediate. 1462 1463 void bic(const VRegister& vd, const int imm8, const int left_shift = 0) 1464 1465 1466### BIC ### 1467 1468Bit clear. 1469 1470 void bic(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1471 1472 1473### BIF ### 1474 1475Bitwise insert if false. 1476 1477 void bif(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1478 1479 1480### BIT ### 1481 1482Bitwise insert if true. 1483 1484 void bit(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1485 1486 1487### BSL ### 1488 1489Bitwise select. 1490 1491 void bsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1492 1493 1494### CLS ### 1495 1496Count leading sign bits. 1497 1498 void cls(const VRegister& vd, const VRegister& vn) 1499 1500 1501### CLZ ### 1502 1503Count leading zero bits (vector). 1504 1505 void clz(const VRegister& vd, const VRegister& vn) 1506 1507 1508### CMEQ ### 1509 1510Compare bitwise to zero. 1511 1512 void cmeq(const VRegister& vd, const VRegister& vn, int value) 1513 1514 1515### CMEQ ### 1516 1517Compare equal. 1518 1519 void cmeq(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1520 1521 1522### CMGE ### 1523 1524Compare signed greater than or equal to zero. 1525 1526 void cmge(const VRegister& vd, const VRegister& vn, int value) 1527 1528 1529### CMGE ### 1530 1531Compare signed greater than or equal. 1532 1533 void cmge(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1534 1535 1536### CMGT ### 1537 1538Compare signed greater than zero. 1539 1540 void cmgt(const VRegister& vd, const VRegister& vn, int value) 1541 1542 1543### CMGT ### 1544 1545Compare signed greater than. 1546 1547 void cmgt(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1548 1549 1550### CMHI ### 1551 1552Compare unsigned higher. 1553 1554 void cmhi(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1555 1556 1557### CMHS ### 1558 1559Compare unsigned higher or same. 1560 1561 void cmhs(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1562 1563 1564### CMLE ### 1565 1566Compare signed less than or equal to zero. 1567 1568 void cmle(const VRegister& vd, const VRegister& vn, int value) 1569 1570 1571### CMLT ### 1572 1573Compare signed less than zero. 1574 1575 void cmlt(const VRegister& vd, const VRegister& vn, int value) 1576 1577 1578### CMTST ### 1579 1580Compare bitwise test bits nonzero. 1581 1582 void cmtst(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1583 1584 1585### CNT ### 1586 1587Population count per byte. 1588 1589 void cnt(const VRegister& vd, const VRegister& vn) 1590 1591 1592### DUP ### 1593 1594Duplicate general-purpose register to vector. 1595 1596 void dup(const VRegister& vd, const Register& rn) 1597 1598 1599### DUP ### 1600 1601Duplicate vector element to vector or scalar. 1602 1603 void dup(const VRegister& vd, const VRegister& vn, int vn_index) 1604 1605 1606### EOR ### 1607 1608Bitwise eor. 1609 1610 void eor(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1611 1612 1613### EXT ### 1614 1615Extract vector from pair of vectors. 1616 1617 void ext(const VRegister& vd, 1618 const VRegister& vn, 1619 const VRegister& vm, 1620 int index) 1621 1622 1623### FABD ### 1624 1625FP absolute difference. 1626 1627 void fabd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1628 1629 1630### FABS ### 1631 1632FP absolute. 1633 1634 void fabs(const VRegister& vd, const VRegister& vn) 1635 1636 1637### FACGE ### 1638 1639FP absolute greater than or equal. 1640 1641 void facge(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1642 1643 1644### FACGT ### 1645 1646FP absolute greater than. 1647 1648 void facgt(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1649 1650 1651### FADD ### 1652 1653FP add. 1654 1655 void fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1656 1657 1658### FADDP ### 1659 1660FP pairwise add scalar. 1661 1662 void faddp(const VRegister& vd, const VRegister& vn) 1663 1664 1665### FADDP ### 1666 1667FP pairwise add vector. 1668 1669 void faddp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1670 1671 1672### FCCMP ### 1673 1674FP conditional compare. 1675 1676 void fccmp(const VRegister& vn, 1677 const VRegister& vm, 1678 StatusFlags nzcv, 1679 Condition cond) 1680 1681 1682### FCCMPE ### 1683 1684FP conditional signaling compare. 1685 1686 void fccmpe(const VRegister& vn, 1687 const VRegister& vm, 1688 StatusFlags nzcv, 1689 Condition cond) 1690 1691 1692### FCMEQ ### 1693 1694FP compare equal to zero. 1695 1696 void fcmeq(const VRegister& vd, const VRegister& vn, double imm) 1697 1698 1699### FCMEQ ### 1700 1701FP compare equal. 1702 1703 void fcmeq(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1704 1705 1706### FCMGE ### 1707 1708FP greater than or equal to zero. 1709 1710 void fcmge(const VRegister& vd, const VRegister& vn, double imm) 1711 1712 1713### FCMGE ### 1714 1715FP greater than or equal. 1716 1717 void fcmge(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1718 1719 1720### FCMGT ### 1721 1722FP greater than zero. 1723 1724 void fcmgt(const VRegister& vd, const VRegister& vn, double imm) 1725 1726 1727### FCMGT ### 1728 1729FP greater than. 1730 1731 void fcmgt(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1732 1733 1734### FCMLE ### 1735 1736FP less than or equal to zero. 1737 1738 void fcmle(const VRegister& vd, const VRegister& vn, double imm) 1739 1740 1741### FCMLT ### 1742 1743FP less than to zero. 1744 1745 void fcmlt(const VRegister& vd, const VRegister& vn, double imm) 1746 1747 1748### FCMP ### 1749 1750FP compare immediate. 1751 1752 void fcmp(const VRegister& vn, double value) 1753 1754 1755### FCMP ### 1756 1757FP compare registers. 1758 1759 void fcmp(const VRegister& vn, const VRegister& vm) 1760 1761 1762### FCMPE ### 1763 1764FP signaling compare immediate. 1765 1766 void fcmpe(const VRegister& vn, double value) 1767 1768 1769### FCMPE ### 1770 1771FP signaling compare registers. 1772 1773 void fcmpe(const VRegister& vn, const VRegister& vm) 1774 1775 1776### FCSEL ### 1777 1778FP conditional select. 1779 1780 void fcsel(const VRegister& vd, 1781 const VRegister& vn, 1782 const VRegister& vm, 1783 Condition cond) 1784 1785 1786### FCVT ### 1787 1788FP convert between precisions. 1789 1790 void fcvt(const VRegister& vd, const VRegister& vn) 1791 1792 1793### FCVTAS ### 1794 1795FP convert to signed integer, nearest with ties to away. 1796 1797 void fcvtas(const Register& rd, const VRegister& vn) 1798 1799 1800### FCVTAS ### 1801 1802FP convert to signed integer, nearest with ties to away. 1803 1804 void fcvtas(const VRegister& vd, const VRegister& vn) 1805 1806 1807### FCVTAU ### 1808 1809FP convert to unsigned integer, nearest with ties to away. 1810 1811 void fcvtau(const Register& rd, const VRegister& vn) 1812 1813 1814### FCVTAU ### 1815 1816FP convert to unsigned integer, nearest with ties to away. 1817 1818 void fcvtau(const VRegister& vd, const VRegister& vn) 1819 1820 1821### FCVTL ### 1822 1823FP convert to higher precision. 1824 1825 void fcvtl(const VRegister& vd, const VRegister& vn) 1826 1827 1828### FCVTL2 ### 1829 1830FP convert to higher precision (second part). 1831 1832 void fcvtl2(const VRegister& vd, const VRegister& vn) 1833 1834 1835### FCVTMS ### 1836 1837FP convert to signed integer, round towards -infinity. 1838 1839 void fcvtms(const Register& rd, const VRegister& vn) 1840 1841 1842### FCVTMS ### 1843 1844FP convert to signed integer, round towards -infinity. 1845 1846 void fcvtms(const VRegister& vd, const VRegister& vn) 1847 1848 1849### FCVTMU ### 1850 1851FP convert to unsigned integer, round towards -infinity. 1852 1853 void fcvtmu(const Register& rd, const VRegister& vn) 1854 1855 1856### FCVTMU ### 1857 1858FP convert to unsigned integer, round towards -infinity. 1859 1860 void fcvtmu(const VRegister& vd, const VRegister& vn) 1861 1862 1863### FCVTN ### 1864 1865FP convert to lower precision. 1866 1867 void fcvtn(const VRegister& vd, const VRegister& vn) 1868 1869 1870### FCVTN2 ### 1871 1872FP convert to lower prevision (second part). 1873 1874 void fcvtn2(const VRegister& vd, const VRegister& vn) 1875 1876 1877### FCVTNS ### 1878 1879FP convert to signed integer, nearest with ties to even. 1880 1881 void fcvtns(const Register& rd, const VRegister& vn) 1882 1883 1884### FCVTNS ### 1885 1886FP convert to signed integer, nearest with ties to even. 1887 1888 void fcvtns(const VRegister& rd, const VRegister& vn) 1889 1890 1891### FCVTNU ### 1892 1893FP convert to unsigned integer, nearest with ties to even. 1894 1895 void fcvtnu(const Register& rd, const VRegister& vn) 1896 1897 1898### FCVTNU ### 1899 1900FP convert to unsigned integer, nearest with ties to even. 1901 1902 void fcvtnu(const VRegister& rd, const VRegister& vn) 1903 1904 1905### FCVTPS ### 1906 1907FP convert to signed integer, round towards +infinity. 1908 1909 void fcvtps(const Register& rd, const VRegister& vn) 1910 1911 1912### FCVTPS ### 1913 1914FP convert to signed integer, round towards +infinity. 1915 1916 void fcvtps(const VRegister& vd, const VRegister& vn) 1917 1918 1919### FCVTPU ### 1920 1921FP convert to unsigned integer, round towards +infinity. 1922 1923 void fcvtpu(const Register& rd, const VRegister& vn) 1924 1925 1926### FCVTPU ### 1927 1928FP convert to unsigned integer, round towards +infinity. 1929 1930 void fcvtpu(const VRegister& vd, const VRegister& vn) 1931 1932 1933### FCVTXN ### 1934 1935FP convert to lower precision, rounding to odd. 1936 1937 void fcvtxn(const VRegister& vd, const VRegister& vn) 1938 1939 1940### FCVTXN2 ### 1941 1942FP convert to lower precision, rounding to odd (second part). 1943 1944 void fcvtxn2(const VRegister& vd, const VRegister& vn) 1945 1946 1947### FCVTZS ### 1948 1949FP convert to signed integer or fixed-point, round towards zero. 1950 1951 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0) 1952 1953 1954### FCVTZS ### 1955 1956FP convert to signed integer or fixed-point, round towards zero. 1957 1958 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) 1959 1960 1961### FCVTZU ### 1962 1963FP convert to unsigned integer or fixed-point, round towards zero. 1964 1965 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0) 1966 1967 1968### FCVTZU ### 1969 1970FP convert to unsigned integer or fixed-point, round towards zero. 1971 1972 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) 1973 1974 1975### FDIV ### 1976 1977FP divide. 1978 1979 void fdiv(const VRegister& vd, const VRegister& fn, const VRegister& vm) 1980 1981 1982### FMADD ### 1983 1984FP fused multiply-add. 1985 1986 void fmadd(const VRegister& vd, 1987 const VRegister& vn, 1988 const VRegister& vm, 1989 const VRegister& va) 1990 1991 1992### FMAX ### 1993 1994FP maximum. 1995 1996 void fmax(const VRegister& vd, const VRegister& fn, const VRegister& vm) 1997 1998 1999### FMAXNM ### 2000 2001FP maximum number. 2002 2003 void fmaxnm(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2004 2005 2006### FMAXNMP ### 2007 2008FP pairwise maximum number scalar. 2009 2010 void fmaxnmp(const VRegister& vd, const VRegister& vn) 2011 2012 2013### FMAXNMP ### 2014 2015FP pairwise maximum number vector. 2016 2017 void fmaxnmp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2018 2019 2020### FMAXNMV ### 2021 2022FP maximum number across vector. 2023 2024 void fmaxnmv(const VRegister& vd, const VRegister& vn) 2025 2026 2027### FMAXP ### 2028 2029FP pairwise maximum scalar. 2030 2031 void fmaxp(const VRegister& vd, const VRegister& vn) 2032 2033 2034### FMAXP ### 2035 2036FP pairwise maximum vector. 2037 2038 void fmaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2039 2040 2041### FMAXV ### 2042 2043FP maximum across vector. 2044 2045 void fmaxv(const VRegister& vd, const VRegister& vn) 2046 2047 2048### FMIN ### 2049 2050FP minimum. 2051 2052 void fmin(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2053 2054 2055### FMINNM ### 2056 2057FP minimum number. 2058 2059 void fminnm(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2060 2061 2062### FMINNMP ### 2063 2064FP pairwise minimum number scalar. 2065 2066 void fminnmp(const VRegister& vd, const VRegister& vn) 2067 2068 2069### FMINNMP ### 2070 2071FP pairwise minimum number vector. 2072 2073 void fminnmp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2074 2075 2076### FMINNMV ### 2077 2078FP minimum number across vector. 2079 2080 void fminnmv(const VRegister& vd, const VRegister& vn) 2081 2082 2083### FMINP ### 2084 2085FP pairwise minimum scalar. 2086 2087 void fminp(const VRegister& vd, const VRegister& vn) 2088 2089 2090### FMINP ### 2091 2092FP pairwise minimum vector. 2093 2094 void fminp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2095 2096 2097### FMINV ### 2098 2099FP minimum across vector. 2100 2101 void fminv(const VRegister& vd, const VRegister& vn) 2102 2103 2104### FMLA ### 2105 2106FP fused multiply-add to accumulator by element. 2107 2108 void fmla(const VRegister& vd, 2109 const VRegister& vn, 2110 const VRegister& vm, 2111 int vm_index) 2112 2113 2114### FMLA ### 2115 2116FP vector multiply accumulate. 2117 2118 void fmla(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2119 2120 2121### FMLS ### 2122 2123FP fused multiply-sub from accumulator by element. 2124 2125 void fmls(const VRegister& vd, 2126 const VRegister& vn, 2127 const VRegister& vm, 2128 int vm_index) 2129 2130 2131### FMLS ### 2132 2133FP vector multiply subtract. 2134 2135 void fmls(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2136 2137 2138### FMOV ### 2139 2140Move 64-bit register to top half of 128-bit FP register. 2141 2142 void fmov(const VRegister& vd, int index, const Register& rn) 2143 2144 2145### FMOV ### 2146 2147Move FP register to FP register. 2148 2149 void fmov(const VRegister& vd, const VRegister& fn) 2150 2151 2152### FMOV ### 2153 2154Move FP register to register. 2155 2156 void fmov(const Register& rd, const VRegister& fn) 2157 2158 2159### FMOV ### 2160 2161Move double precision immediate to FP register. 2162 2163 void fmov(const VRegister& vd, double imm) 2164 2165 2166### FMOV ### 2167 2168Move register to FP register. 2169 2170 void fmov(const VRegister& vd, const Register& rn) 2171 2172 2173### FMOV ### 2174 2175Move single precision immediate to FP register. 2176 2177 void fmov(const VRegister& vd, float imm) 2178 2179 2180### FMOV ### 2181 2182Move top half of 128-bit FP register to 64-bit register. 2183 2184 void fmov(const Register& rd, const VRegister& vn, int index) 2185 2186 2187### FMSUB ### 2188 2189FP fused multiply-subtract. 2190 2191 void fmsub(const VRegister& vd, 2192 const VRegister& vn, 2193 const VRegister& vm, 2194 const VRegister& va) 2195 2196 2197### FMUL ### 2198 2199FP multiply by element. 2200 2201 void fmul(const VRegister& vd, 2202 const VRegister& vn, 2203 const VRegister& vm, 2204 int vm_index) 2205 2206 2207### FMUL ### 2208 2209FP multiply. 2210 2211 void fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2212 2213 2214### FMULX ### 2215 2216FP multiply extended by element. 2217 2218 void fmulx(const VRegister& vd, 2219 const VRegister& vn, 2220 const VRegister& vm, 2221 int vm_index) 2222 2223 2224### FMULX ### 2225 2226FP vector multiply extended. 2227 2228 void fmulx(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2229 2230 2231### FNEG ### 2232 2233FP negate. 2234 2235 void fneg(const VRegister& vd, const VRegister& vn) 2236 2237 2238### FNMADD ### 2239 2240FP fused multiply-add and negate. 2241 2242 void fnmadd(const VRegister& vd, 2243 const VRegister& vn, 2244 const VRegister& vm, 2245 const VRegister& va) 2246 2247 2248### FNMSUB ### 2249 2250FP fused multiply-subtract and negate. 2251 2252 void fnmsub(const VRegister& vd, 2253 const VRegister& vn, 2254 const VRegister& vm, 2255 const VRegister& va) 2256 2257 2258### FNMUL ### 2259 2260FP multiply-negate scalar. 2261 2262 void fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2263 2264 2265### FRECPE ### 2266 2267FP reciprocal estimate. 2268 2269 void frecpe(const VRegister& vd, const VRegister& vn) 2270 2271 2272### FRECPS ### 2273 2274FP reciprocal step. 2275 2276 void frecps(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2277 2278 2279### FRECPX ### 2280 2281FP reciprocal exponent scalar. 2282 2283 void frecpx(const VRegister& vd, const VRegister& vn) 2284 2285 2286### FRINTA ### 2287 2288FP round to integer, nearest with ties to away. 2289 2290 void frinta(const VRegister& vd, const VRegister& vn) 2291 2292 2293### FRINTI ### 2294 2295FP round to integer, implicit rounding. 2296 2297 void frinti(const VRegister& vd, const VRegister& vn) 2298 2299 2300### FRINTM ### 2301 2302FP round to integer, toward minus infinity. 2303 2304 void frintm(const VRegister& vd, const VRegister& vn) 2305 2306 2307### FRINTN ### 2308 2309FP round to integer, nearest with ties to even. 2310 2311 void frintn(const VRegister& vd, const VRegister& vn) 2312 2313 2314### FRINTP ### 2315 2316FP round to integer, toward plus infinity. 2317 2318 void frintp(const VRegister& vd, const VRegister& vn) 2319 2320 2321### FRINTX ### 2322 2323FP round to integer, exact, implicit rounding. 2324 2325 void frintx(const VRegister& vd, const VRegister& vn) 2326 2327 2328### FRINTZ ### 2329 2330FP round to integer, towards zero. 2331 2332 void frintz(const VRegister& vd, const VRegister& vn) 2333 2334 2335### FRSQRTE ### 2336 2337FP reciprocal square root estimate. 2338 2339 void frsqrte(const VRegister& vd, const VRegister& vn) 2340 2341 2342### FRSQRTS ### 2343 2344FP reciprocal square root step. 2345 2346 void frsqrts(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2347 2348 2349### FSQRT ### 2350 2351FP square root. 2352 2353 void fsqrt(const VRegister& vd, const VRegister& vn) 2354 2355 2356### FSUB ### 2357 2358FP subtract. 2359 2360 void fsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2361 2362 2363### INS ### 2364 2365Insert vector element from another vector element. 2366 2367 void ins(const VRegister& vd, 2368 int vd_index, 2369 const VRegister& vn, 2370 int vn_index) 2371 2372 2373### INS ### 2374 2375Insert vector element from general-purpose register. 2376 2377 void ins(const VRegister& vd, int vd_index, const Register& rn) 2378 2379 2380### LD1 ### 2381 2382One-element single structure load to one lane. 2383 2384 void ld1(const VRegister& vt, int lane, const MemOperand& src) 2385 2386 2387### LD1 ### 2388 2389One-element structure load to four registers. 2390 2391 void ld1(const VRegister& vt, 2392 const VRegister& vt2, 2393 const VRegister& vt3, 2394 const VRegister& vt4, 2395 const MemOperand& src) 2396 2397 2398### LD1 ### 2399 2400One-element structure load to one register. 2401 2402 void ld1(const VRegister& vt, const MemOperand& src) 2403 2404 2405### LD1 ### 2406 2407One-element structure load to three registers. 2408 2409 void ld1(const VRegister& vt, 2410 const VRegister& vt2, 2411 const VRegister& vt3, 2412 const MemOperand& src) 2413 2414 2415### LD1 ### 2416 2417One-element structure load to two registers. 2418 2419 void ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 2420 2421 2422### LD1R ### 2423 2424One-element single structure load to all lanes. 2425 2426 void ld1r(const VRegister& vt, const MemOperand& src) 2427 2428 2429### LD2 ### 2430 2431Two-element single structure load to one lane. 2432 2433 void ld2(const VRegister& vt, 2434 const VRegister& vt2, 2435 int lane, 2436 const MemOperand& src) 2437 2438 2439### LD2 ### 2440 2441Two-element structure load. 2442 2443 void ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 2444 2445 2446### LD2R ### 2447 2448Two-element single structure load to all lanes. 2449 2450 void ld2r(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 2451 2452 2453### LD3 ### 2454 2455Three-element single structure load to one lane. 2456 2457 void ld3(const VRegister& vt, 2458 const VRegister& vt2, 2459 const VRegister& vt3, 2460 int lane, 2461 const MemOperand& src) 2462 2463 2464### LD3 ### 2465 2466Three-element structure load. 2467 2468 void ld3(const VRegister& vt, 2469 const VRegister& vt2, 2470 const VRegister& vt3, 2471 const MemOperand& src) 2472 2473 2474### LD3R ### 2475 2476Three-element single structure load to all lanes. 2477 2478 void ld3r(const VRegister& vt, 2479 const VRegister& vt2, 2480 const VRegister& vt3, 2481 const MemOperand& src) 2482 2483 2484### LD4 ### 2485 2486Four-element single structure load to one lane. 2487 2488 void ld4(const VRegister& vt, 2489 const VRegister& vt2, 2490 const VRegister& vt3, 2491 const VRegister& vt4, 2492 int lane, 2493 const MemOperand& src) 2494 2495 2496### LD4 ### 2497 2498Four-element structure load. 2499 2500 void ld4(const VRegister& vt, 2501 const VRegister& vt2, 2502 const VRegister& vt3, 2503 const VRegister& vt4, 2504 const MemOperand& src) 2505 2506 2507### LD4R ### 2508 2509Four-element single structure load to all lanes. 2510 2511 void ld4r(const VRegister& vt, 2512 const VRegister& vt2, 2513 const VRegister& vt3, 2514 const VRegister& vt4, 2515 const MemOperand& src) 2516 2517 2518### MLA ### 2519 2520Multiply-add by scalar element. 2521 2522 void mla(const VRegister& vd, 2523 const VRegister& vn, 2524 const VRegister& vm, 2525 int vm_index) 2526 2527 2528### MLA ### 2529 2530Multiply-add to accumulator. 2531 2532 void mla(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2533 2534 2535### MLS ### 2536 2537Multiply-subtract by scalar element. 2538 2539 void mls(const VRegister& vd, 2540 const VRegister& vn, 2541 const VRegister& vm, 2542 int vm_index) 2543 2544 2545### MLS ### 2546 2547Multiply-subtract to accumulator. 2548 2549 void mls(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2550 2551 2552### MOV ### 2553 2554Move general-purpose register to a vector element. 2555 2556 void mov(const VRegister& vd, int vd_index, const Register& rn) 2557 2558 2559### MOV ### 2560 2561Move register to register. 2562 2563 void mov(const VRegister& vd, const VRegister& vn) 2564 2565 2566### MOV ### 2567 2568Move vector element to another vector element. 2569 2570 void mov(const VRegister& vd, 2571 int vd_index, 2572 const VRegister& vn, 2573 int vn_index) 2574 2575 2576### MOV ### 2577 2578Move vector element to general-purpose register. 2579 2580 void mov(const Register& rd, const VRegister& vn, int vn_index) 2581 2582 2583### MOV ### 2584 2585Move vector element to scalar. 2586 2587 void mov(const VRegister& vd, const VRegister& vn, int vn_index) 2588 2589 2590### MOVI ### 2591 2592Vector move immediate. 2593 2594 void movi(const VRegister& vd, 2595 const uint64_t imm, 2596 Shift shift = LSL, 2597 const int shift_amount = 0) 2598 2599 2600### MUL ### 2601 2602Multiply by scalar element. 2603 2604 void mul(const VRegister& vd, 2605 const VRegister& vn, 2606 const VRegister& vm, 2607 int vm_index) 2608 2609 2610### MUL ### 2611 2612Multiply. 2613 2614 void mul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2615 2616 2617### MVN ### 2618 2619Bitwise not. 2620 2621 void mvn(const VRegister& vd, const VRegister& vn) 2622 2623 2624### MVNI ### 2625 2626Vector move inverted immediate. 2627 2628 void mvni(const VRegister& vd, 2629 const int imm8, 2630 Shift shift = LSL, 2631 const int shift_amount = 0) 2632 2633 2634### NEG ### 2635 2636Negate. 2637 2638 void neg(const VRegister& vd, const VRegister& vn) 2639 2640 2641### NOT ### 2642 2643Bitwise not. 2644 2645 void not_(const VRegister& vd, const VRegister& vn) 2646 2647 2648### ORN ### 2649 2650Bitwise orn. 2651 2652 void orn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2653 2654 2655### ORR ### 2656 2657Bitwise or immediate. 2658 2659 void orr(const VRegister& vd, const int imm8, const int left_shift = 0) 2660 2661 2662### ORR ### 2663 2664Bitwise or. 2665 2666 void orr(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2667 2668 2669### PMUL ### 2670 2671Polynomial multiply. 2672 2673 void pmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2674 2675 2676### PMULL ### 2677 2678Polynomial multiply long. 2679 2680 void pmull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2681 2682 2683### PMULL2 ### 2684 2685Polynomial multiply long (second part). 2686 2687 void pmull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2688 2689 2690### RADDHN ### 2691 2692Rounding add narrow returning high half. 2693 2694 void raddhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2695 2696 2697### RADDHN2 ### 2698 2699Rounding add narrow returning high half (second part). 2700 2701 void raddhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2702 2703 2704### RBIT ### 2705 2706Reverse bit order. 2707 2708 void rbit(const VRegister& vd, const VRegister& vn) 2709 2710 2711### REV16 ### 2712 2713Reverse elements in 16-bit halfwords. 2714 2715 void rev16(const VRegister& vd, const VRegister& vn) 2716 2717 2718### REV32 ### 2719 2720Reverse elements in 32-bit words. 2721 2722 void rev32(const VRegister& vd, const VRegister& vn) 2723 2724 2725### REV64 ### 2726 2727Reverse elements in 64-bit doublewords. 2728 2729 void rev64(const VRegister& vd, const VRegister& vn) 2730 2731 2732### RSHRN ### 2733 2734Rounding shift right narrow by immediate. 2735 2736 void rshrn(const VRegister& vd, const VRegister& vn, int shift) 2737 2738 2739### RSHRN2 ### 2740 2741Rounding shift right narrow by immediate (second part). 2742 2743 void rshrn2(const VRegister& vd, const VRegister& vn, int shift) 2744 2745 2746### RSUBHN ### 2747 2748Rounding subtract narrow returning high half. 2749 2750 void rsubhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2751 2752 2753### RSUBHN2 ### 2754 2755Rounding subtract narrow returning high half (second part). 2756 2757 void rsubhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2758 2759 2760### SABA ### 2761 2762Signed absolute difference and accumulate. 2763 2764 void saba(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2765 2766 2767### SABAL ### 2768 2769Signed absolute difference and accumulate long. 2770 2771 void sabal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2772 2773 2774### SABAL2 ### 2775 2776Signed absolute difference and accumulate long (second part). 2777 2778 void sabal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2779 2780 2781### SABD ### 2782 2783Signed absolute difference. 2784 2785 void sabd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2786 2787 2788### SABDL ### 2789 2790Signed absolute difference long. 2791 2792 void sabdl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2793 2794 2795### SABDL2 ### 2796 2797Signed absolute difference long (second part). 2798 2799 void sabdl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2800 2801 2802### SADALP ### 2803 2804Signed pairwise long add and accumulate. 2805 2806 void sadalp(const VRegister& vd, const VRegister& vn) 2807 2808 2809### SADDL ### 2810 2811Signed add long. 2812 2813 void saddl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2814 2815 2816### SADDL2 ### 2817 2818Signed add long (second part). 2819 2820 void saddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2821 2822 2823### SADDLP ### 2824 2825Signed pairwise long add. 2826 2827 void saddlp(const VRegister& vd, const VRegister& vn) 2828 2829 2830### SADDLV ### 2831 2832Signed add long across vector. 2833 2834 void saddlv(const VRegister& vd, const VRegister& vn) 2835 2836 2837### SADDW ### 2838 2839Signed add wide. 2840 2841 void saddw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2842 2843 2844### SADDW2 ### 2845 2846Signed add wide (second part). 2847 2848 void saddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2849 2850 2851### SCVTF ### 2852 2853Convert signed integer or fixed point to FP. 2854 2855 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0) 2856 2857 2858### SCVTF ### 2859 2860Convert signed integer or fixed-point to FP. 2861 2862 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0) 2863 2864 2865### SHADD ### 2866 2867Signed halving add. 2868 2869 void shadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2870 2871 2872### SHL ### 2873 2874Shift left by immediate. 2875 2876 void shl(const VRegister& vd, const VRegister& vn, int shift) 2877 2878 2879### SHLL ### 2880 2881Shift left long by element size. 2882 2883 void shll(const VRegister& vd, const VRegister& vn, int shift) 2884 2885 2886### SHLL2 ### 2887 2888Shift left long by element size (second part). 2889 2890 void shll2(const VRegister& vd, const VRegister& vn, int shift) 2891 2892 2893### SHRN ### 2894 2895Shift right narrow by immediate. 2896 2897 void shrn(const VRegister& vd, const VRegister& vn, int shift) 2898 2899 2900### SHRN2 ### 2901 2902Shift right narrow by immediate (second part). 2903 2904 void shrn2(const VRegister& vd, const VRegister& vn, int shift) 2905 2906 2907### SHSUB ### 2908 2909Signed halving sub. 2910 2911 void shsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2912 2913 2914### SLI ### 2915 2916Shift left by immediate and insert. 2917 2918 void sli(const VRegister& vd, const VRegister& vn, int shift) 2919 2920 2921### SMAX ### 2922 2923Signed maximum. 2924 2925 void smax(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2926 2927 2928### SMAXP ### 2929 2930Signed pairwise maximum. 2931 2932 void smaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2933 2934 2935### SMAXV ### 2936 2937Signed maximum across vector. 2938 2939 void smaxv(const VRegister& vd, const VRegister& vn) 2940 2941 2942### SMIN ### 2943 2944Signed minimum. 2945 2946 void smin(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2947 2948 2949### SMINP ### 2950 2951Signed minimum pairwise. 2952 2953 void sminp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2954 2955 2956### SMINV ### 2957 2958Signed minimum across vector. 2959 2960 void sminv(const VRegister& vd, const VRegister& vn) 2961 2962 2963### SMLAL ### 2964 2965Signed long multiply-add by scalar element. 2966 2967 void smlal(const VRegister& vd, 2968 const VRegister& vn, 2969 const VRegister& vm, 2970 int vm_index) 2971 2972 2973### SMLAL ### 2974 2975Signed long multiply-add. 2976 2977 void smlal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2978 2979 2980### SMLAL2 ### 2981 2982Signed long multiply-add (second part). 2983 2984 void smlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2985 2986 2987### SMLAL2 ### 2988 2989Signed long multiply-add by scalar element (second part). 2990 2991 void smlal2(const VRegister& vd, 2992 const VRegister& vn, 2993 const VRegister& vm, 2994 int vm_index) 2995 2996 2997### SMLSL ### 2998 2999Signed long multiply-sub by scalar element. 3000 3001 void smlsl(const VRegister& vd, 3002 const VRegister& vn, 3003 const VRegister& vm, 3004 int vm_index) 3005 3006 3007### SMLSL ### 3008 3009Signed long multiply-sub. 3010 3011 void smlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3012 3013 3014### SMLSL2 ### 3015 3016Signed long multiply-sub (second part). 3017 3018 void smlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3019 3020 3021### SMLSL2 ### 3022 3023Signed long multiply-sub by scalar element (second part). 3024 3025 void smlsl2(const VRegister& vd, 3026 const VRegister& vn, 3027 const VRegister& vm, 3028 int vm_index) 3029 3030 3031### SMOV ### 3032 3033Signed move vector element to general-purpose register. 3034 3035 void smov(const Register& rd, const VRegister& vn, int vn_index) 3036 3037 3038### SMULL ### 3039 3040Signed long multiply by scalar element. 3041 3042 void smull(const VRegister& vd, 3043 const VRegister& vn, 3044 const VRegister& vm, 3045 int vm_index) 3046 3047 3048### SMULL ### 3049 3050Signed long multiply. 3051 3052 void smull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3053 3054 3055### SMULL2 ### 3056 3057Signed long multiply (second part). 3058 3059 void smull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3060 3061 3062### SMULL2 ### 3063 3064Signed long multiply by scalar element (second part). 3065 3066 void smull2(const VRegister& vd, 3067 const VRegister& vn, 3068 const VRegister& vm, 3069 int vm_index) 3070 3071 3072### SQABS ### 3073 3074Signed saturating absolute value. 3075 3076 void sqabs(const VRegister& vd, const VRegister& vn) 3077 3078 3079### SQADD ### 3080 3081Signed saturating add. 3082 3083 void sqadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3084 3085 3086### SQDMLAL ### 3087 3088Signed saturating doubling long multiply-add by element. 3089 3090 void sqdmlal(const VRegister& vd, 3091 const VRegister& vn, 3092 const VRegister& vm, 3093 int vm_index) 3094 3095 3096### SQDMLAL ### 3097 3098Signed saturating doubling long multiply-add. 3099 3100 void sqdmlal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3101 3102 3103### SQDMLAL2 ### 3104 3105Signed saturating doubling long multiply-add (second part). 3106 3107 void sqdmlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3108 3109 3110### SQDMLAL2 ### 3111 3112Signed saturating doubling long multiply-add by element (second part). 3113 3114 void sqdmlal2(const VRegister& vd, 3115 const VRegister& vn, 3116 const VRegister& vm, 3117 int vm_index) 3118 3119 3120### SQDMLSL ### 3121 3122Signed saturating doubling long multiply-sub by element. 3123 3124 void sqdmlsl(const VRegister& vd, 3125 const VRegister& vn, 3126 const VRegister& vm, 3127 int vm_index) 3128 3129 3130### SQDMLSL ### 3131 3132Signed saturating doubling long multiply-subtract. 3133 3134 void sqdmlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3135 3136 3137### SQDMLSL2 ### 3138 3139Signed saturating doubling long multiply-sub by element (second part). 3140 3141 void sqdmlsl2(const VRegister& vd, 3142 const VRegister& vn, 3143 const VRegister& vm, 3144 int vm_index) 3145 3146 3147### SQDMLSL2 ### 3148 3149Signed saturating doubling long multiply-subtract (second part). 3150 3151 void sqdmlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3152 3153 3154### SQDMULH ### 3155 3156Signed saturating doubling multiply element returning high half. 3157 3158 void sqdmulh(const VRegister& vd, 3159 const VRegister& vn, 3160 const VRegister& vm, 3161 int vm_index) 3162 3163 3164### SQDMULH ### 3165 3166Signed saturating doubling multiply returning high half. 3167 3168 void sqdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3169 3170 3171### SQDMULL ### 3172 3173Signed saturating double long multiply by element. 3174 3175 void sqdmull(const VRegister& vd, 3176 const VRegister& vn, 3177 const VRegister& vm, 3178 int vm_index) 3179 3180 3181### SQDMULL ### 3182 3183Signed saturating doubling long multiply. 3184 3185 void sqdmull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3186 3187 3188### SQDMULL2 ### 3189 3190Signed saturating double long multiply by element (second part). 3191 3192 void sqdmull2(const VRegister& vd, 3193 const VRegister& vn, 3194 const VRegister& vm, 3195 int vm_index) 3196 3197 3198### SQDMULL2 ### 3199 3200Signed saturating doubling long multiply (second part). 3201 3202 void sqdmull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3203 3204 3205### SQNEG ### 3206 3207Signed saturating negate. 3208 3209 void sqneg(const VRegister& vd, const VRegister& vn) 3210 3211 3212### SQRDMULH ### 3213 3214Signed saturating rounding doubling multiply element returning high half. 3215 3216 void sqrdmulh(const VRegister& vd, 3217 const VRegister& vn, 3218 const VRegister& vm, 3219 int vm_index) 3220 3221 3222### SQRDMULH ### 3223 3224Signed saturating rounding doubling multiply returning high half. 3225 3226 void sqrdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3227 3228 3229### SQRSHL ### 3230 3231Signed saturating rounding shift left by register. 3232 3233 void sqrshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3234 3235 3236### SQRSHRN ### 3237 3238Signed saturating rounded shift right narrow by immediate. 3239 3240 void sqrshrn(const VRegister& vd, const VRegister& vn, int shift) 3241 3242 3243### SQRSHRN2 ### 3244 3245Signed saturating rounded shift right narrow by immediate (second part). 3246 3247 void sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) 3248 3249 3250### SQRSHRUN ### 3251 3252Signed sat rounded shift right unsigned narrow by immediate. 3253 3254 void sqrshrun(const VRegister& vd, const VRegister& vn, int shift) 3255 3256 3257### SQRSHRUN2 ### 3258 3259Signed sat rounded shift right unsigned narrow by immediate (second part). 3260 3261 void sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) 3262 3263 3264### SQSHL ### 3265 3266Signed saturating shift left by immediate. 3267 3268 void sqshl(const VRegister& vd, const VRegister& vn, int shift) 3269 3270 3271### SQSHL ### 3272 3273Signed saturating shift left by register. 3274 3275 void sqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3276 3277 3278### SQSHLU ### 3279 3280Signed saturating shift left unsigned by immediate. 3281 3282 void sqshlu(const VRegister& vd, const VRegister& vn, int shift) 3283 3284 3285### SQSHRN ### 3286 3287Signed saturating shift right narrow by immediate. 3288 3289 void sqshrn(const VRegister& vd, const VRegister& vn, int shift) 3290 3291 3292### SQSHRN2 ### 3293 3294Signed saturating shift right narrow by immediate (second part). 3295 3296 void sqshrn2(const VRegister& vd, const VRegister& vn, int shift) 3297 3298 3299### SQSHRUN ### 3300 3301Signed saturating shift right unsigned narrow by immediate. 3302 3303 void sqshrun(const VRegister& vd, const VRegister& vn, int shift) 3304 3305 3306### SQSHRUN2 ### 3307 3308Signed saturating shift right unsigned narrow by immediate (second part). 3309 3310 void sqshrun2(const VRegister& vd, const VRegister& vn, int shift) 3311 3312 3313### SQSUB ### 3314 3315Signed saturating subtract. 3316 3317 void sqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3318 3319 3320### SQXTN ### 3321 3322Signed saturating extract narrow. 3323 3324 void sqxtn(const VRegister& vd, const VRegister& vn) 3325 3326 3327### SQXTN2 ### 3328 3329Signed saturating extract narrow (second part). 3330 3331 void sqxtn2(const VRegister& vd, const VRegister& vn) 3332 3333 3334### SQXTUN ### 3335 3336Signed saturating extract unsigned narrow. 3337 3338 void sqxtun(const VRegister& vd, const VRegister& vn) 3339 3340 3341### SQXTUN2 ### 3342 3343Signed saturating extract unsigned narrow (second part). 3344 3345 void sqxtun2(const VRegister& vd, const VRegister& vn) 3346 3347 3348### SRHADD ### 3349 3350Signed rounding halving add. 3351 3352 void srhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3353 3354 3355### SRI ### 3356 3357Shift right by immediate and insert. 3358 3359 void sri(const VRegister& vd, const VRegister& vn, int shift) 3360 3361 3362### SRSHL ### 3363 3364Signed rounding shift left by register. 3365 3366 void srshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3367 3368 3369### SRSHR ### 3370 3371Signed rounding shift right by immediate. 3372 3373 void srshr(const VRegister& vd, const VRegister& vn, int shift) 3374 3375 3376### SRSRA ### 3377 3378Signed rounding shift right by immediate and accumulate. 3379 3380 void srsra(const VRegister& vd, const VRegister& vn, int shift) 3381 3382 3383### SSHL ### 3384 3385Signed shift left by register. 3386 3387 void sshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3388 3389 3390### SSHLL ### 3391 3392Signed shift left long by immediate. 3393 3394 void sshll(const VRegister& vd, const VRegister& vn, int shift) 3395 3396 3397### SSHLL2 ### 3398 3399Signed shift left long by immediate (second part). 3400 3401 void sshll2(const VRegister& vd, const VRegister& vn, int shift) 3402 3403 3404### SSHR ### 3405 3406Signed shift right by immediate. 3407 3408 void sshr(const VRegister& vd, const VRegister& vn, int shift) 3409 3410 3411### SSRA ### 3412 3413Signed shift right by immediate and accumulate. 3414 3415 void ssra(const VRegister& vd, const VRegister& vn, int shift) 3416 3417 3418### SSUBL ### 3419 3420Signed subtract long. 3421 3422 void ssubl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3423 3424 3425### SSUBL2 ### 3426 3427Signed subtract long (second part). 3428 3429 void ssubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3430 3431 3432### SSUBW ### 3433 3434Signed integer subtract wide. 3435 3436 void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3437 3438 3439### SSUBW2 ### 3440 3441Signed integer subtract wide (second part). 3442 3443 void ssubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3444 3445 3446### ST1 ### 3447 3448One-element single structure store from one lane. 3449 3450 void st1(const VRegister& vt, int lane, const MemOperand& src) 3451 3452 3453### ST1 ### 3454 3455One-element structure store from four registers. 3456 3457 void st1(const VRegister& vt, 3458 const VRegister& vt2, 3459 const VRegister& vt3, 3460 const VRegister& vt4, 3461 const MemOperand& src) 3462 3463 3464### ST1 ### 3465 3466One-element structure store from one register. 3467 3468 void st1(const VRegister& vt, const MemOperand& src) 3469 3470 3471### ST1 ### 3472 3473One-element structure store from three registers. 3474 3475 void st1(const VRegister& vt, 3476 const VRegister& vt2, 3477 const VRegister& vt3, 3478 const MemOperand& src) 3479 3480 3481### ST1 ### 3482 3483One-element structure store from two registers. 3484 3485 void st1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 3486 3487 3488### ST2 ### 3489 3490Two-element single structure store from two lanes. 3491 3492 void st2(const VRegister& vt, 3493 const VRegister& vt2, 3494 int lane, 3495 const MemOperand& src) 3496 3497 3498### ST2 ### 3499 3500Two-element structure store from two registers. 3501 3502 void st2(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 3503 3504 3505### ST3 ### 3506 3507Three-element single structure store from three lanes. 3508 3509 void st3(const VRegister& vt, 3510 const VRegister& vt2, 3511 const VRegister& vt3, 3512 int lane, 3513 const MemOperand& src) 3514 3515 3516### ST3 ### 3517 3518Three-element structure store from three registers. 3519 3520 void st3(const VRegister& vt, 3521 const VRegister& vt2, 3522 const VRegister& vt3, 3523 const MemOperand& src) 3524 3525 3526### ST4 ### 3527 3528Four-element single structure store from four lanes. 3529 3530 void st4(const VRegister& vt, 3531 const VRegister& vt2, 3532 const VRegister& vt3, 3533 const VRegister& vt4, 3534 int lane, 3535 const MemOperand& src) 3536 3537 3538### ST4 ### 3539 3540Four-element structure store from four registers. 3541 3542 void st4(const VRegister& vt, 3543 const VRegister& vt2, 3544 const VRegister& vt3, 3545 const VRegister& vt4, 3546 const MemOperand& src) 3547 3548 3549### SUB ### 3550 3551Subtract. 3552 3553 void sub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3554 3555 3556### SUBHN ### 3557 3558Subtract narrow returning high half. 3559 3560 void subhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3561 3562 3563### SUBHN2 ### 3564 3565Subtract narrow returning high half (second part). 3566 3567 void subhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3568 3569 3570### SUQADD ### 3571 3572Signed saturating accumulate of unsigned value. 3573 3574 void suqadd(const VRegister& vd, const VRegister& vn) 3575 3576 3577### SXTL ### 3578 3579Signed extend long. 3580 3581 void sxtl(const VRegister& vd, const VRegister& vn) 3582 3583 3584### SXTL2 ### 3585 3586Signed extend long (second part). 3587 3588 void sxtl2(const VRegister& vd, const VRegister& vn) 3589 3590 3591### TBL ### 3592 3593Table lookup from four registers. 3594 3595 void tbl(const VRegister& vd, 3596 const VRegister& vn, 3597 const VRegister& vn2, 3598 const VRegister& vn3, 3599 const VRegister& vn4, 3600 const VRegister& vm) 3601 3602 3603### TBL ### 3604 3605Table lookup from one register. 3606 3607 void tbl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3608 3609 3610### TBL ### 3611 3612Table lookup from three registers. 3613 3614 void tbl(const VRegister& vd, 3615 const VRegister& vn, 3616 const VRegister& vn2, 3617 const VRegister& vn3, 3618 const VRegister& vm) 3619 3620 3621### TBL ### 3622 3623Table lookup from two registers. 3624 3625 void tbl(const VRegister& vd, 3626 const VRegister& vn, 3627 const VRegister& vn2, 3628 const VRegister& vm) 3629 3630 3631### TBX ### 3632 3633Table lookup extension from four registers. 3634 3635 void tbx(const VRegister& vd, 3636 const VRegister& vn, 3637 const VRegister& vn2, 3638 const VRegister& vn3, 3639 const VRegister& vn4, 3640 const VRegister& vm) 3641 3642 3643### TBX ### 3644 3645Table lookup extension from one register. 3646 3647 void tbx(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3648 3649 3650### TBX ### 3651 3652Table lookup extension from three registers. 3653 3654 void tbx(const VRegister& vd, 3655 const VRegister& vn, 3656 const VRegister& vn2, 3657 const VRegister& vn3, 3658 const VRegister& vm) 3659 3660 3661### TBX ### 3662 3663Table lookup extension from two registers. 3664 3665 void tbx(const VRegister& vd, 3666 const VRegister& vn, 3667 const VRegister& vn2, 3668 const VRegister& vm) 3669 3670 3671### TRN1 ### 3672 3673Transpose vectors (primary). 3674 3675 void trn1(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3676 3677 3678### TRN2 ### 3679 3680Transpose vectors (secondary). 3681 3682 void trn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3683 3684 3685### UABA ### 3686 3687Unsigned absolute difference and accumulate. 3688 3689 void uaba(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3690 3691 3692### UABAL ### 3693 3694Unsigned absolute difference and accumulate long. 3695 3696 void uabal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3697 3698 3699### UABAL2 ### 3700 3701Unsigned absolute difference and accumulate long (second part). 3702 3703 void uabal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3704 3705 3706### UABD ### 3707 3708Unsigned absolute difference. 3709 3710 void uabd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3711 3712 3713### UABDL ### 3714 3715Unsigned absolute difference long. 3716 3717 void uabdl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3718 3719 3720### UABDL2 ### 3721 3722Unsigned absolute difference long (second part). 3723 3724 void uabdl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3725 3726 3727### UADALP ### 3728 3729Unsigned pairwise long add and accumulate. 3730 3731 void uadalp(const VRegister& vd, const VRegister& vn) 3732 3733 3734### UADDL ### 3735 3736Unsigned add long. 3737 3738 void uaddl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3739 3740 3741### UADDL2 ### 3742 3743Unsigned add long (second part). 3744 3745 void uaddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3746 3747 3748### UADDLP ### 3749 3750Unsigned pairwise long add. 3751 3752 void uaddlp(const VRegister& vd, const VRegister& vn) 3753 3754 3755### UADDLV ### 3756 3757Unsigned add long across vector. 3758 3759 void uaddlv(const VRegister& vd, const VRegister& vn) 3760 3761 3762### UADDW ### 3763 3764Unsigned add wide. 3765 3766 void uaddw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3767 3768 3769### UADDW2 ### 3770 3771Unsigned add wide (second part). 3772 3773 void uaddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3774 3775 3776### UCVTF ### 3777 3778Convert unsigned integer or fixed point to FP. 3779 3780 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0) 3781 3782 3783### UCVTF ### 3784 3785Convert unsigned integer or fixed-point to FP. 3786 3787 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0) 3788 3789 3790### UHADD ### 3791 3792Unsigned halving add. 3793 3794 void uhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3795 3796 3797### UHSUB ### 3798 3799Unsigned halving sub. 3800 3801 void uhsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3802 3803 3804### UMAX ### 3805 3806Unsigned maximum. 3807 3808 void umax(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3809 3810 3811### UMAXP ### 3812 3813Unsigned pairwise maximum. 3814 3815 void umaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3816 3817 3818### UMAXV ### 3819 3820Unsigned maximum across vector. 3821 3822 void umaxv(const VRegister& vd, const VRegister& vn) 3823 3824 3825### UMIN ### 3826 3827Unsigned minimum. 3828 3829 void umin(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3830 3831 3832### UMINP ### 3833 3834Unsigned pairwise minimum. 3835 3836 void uminp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3837 3838 3839### UMINV ### 3840 3841Unsigned minimum across vector. 3842 3843 void uminv(const VRegister& vd, const VRegister& vn) 3844 3845 3846### UMLAL ### 3847 3848Unsigned long multiply-add by scalar element. 3849 3850 void umlal(const VRegister& vd, 3851 const VRegister& vn, 3852 const VRegister& vm, 3853 int vm_index) 3854 3855 3856### UMLAL ### 3857 3858Unsigned long multiply-add. 3859 3860 void umlal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3861 3862 3863### UMLAL2 ### 3864 3865Unsigned long multiply-add (second part). 3866 3867 void umlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3868 3869 3870### UMLAL2 ### 3871 3872Unsigned long multiply-add by scalar element (second part). 3873 3874 void umlal2(const VRegister& vd, 3875 const VRegister& vn, 3876 const VRegister& vm, 3877 int vm_index) 3878 3879 3880### UMLSL ### 3881 3882Unsigned long multiply-sub by scalar element. 3883 3884 void umlsl(const VRegister& vd, 3885 const VRegister& vn, 3886 const VRegister& vm, 3887 int vm_index) 3888 3889 3890### UMLSL ### 3891 3892Unsigned long multiply-sub. 3893 3894 void umlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3895 3896 3897### UMLSL2 ### 3898 3899Unsigned long multiply-sub (second part). 3900 3901 void umlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3902 3903 3904### UMLSL2 ### 3905 3906Unsigned long multiply-sub by scalar element (second part). 3907 3908 void umlsl2(const VRegister& vd, 3909 const VRegister& vn, 3910 const VRegister& vm, 3911 int vm_index) 3912 3913 3914### UMOV ### 3915 3916Unsigned move vector element to general-purpose register. 3917 3918 void umov(const Register& rd, const VRegister& vn, int vn_index) 3919 3920 3921### UMULL ### 3922 3923Unsigned long multiply by scalar element. 3924 3925 void umull(const VRegister& vd, 3926 const VRegister& vn, 3927 const VRegister& vm, 3928 int vm_index) 3929 3930 3931### UMULL ### 3932 3933Unsigned long multiply long. 3934 3935 void umull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3936 3937 3938### UMULL2 ### 3939 3940Unsigned long multiply (second part). 3941 3942 void umull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3943 3944 3945### UMULL2 ### 3946 3947Unsigned long multiply by scalar element (second part). 3948 3949 void umull2(const VRegister& vd, 3950 const VRegister& vn, 3951 const VRegister& vm, 3952 int vm_index) 3953 3954 3955### UQADD ### 3956 3957Unsigned saturating add. 3958 3959 void uqadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3960 3961 3962### UQRSHL ### 3963 3964Unsigned saturating rounding shift left by register. 3965 3966 void uqrshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3967 3968 3969### UQRSHRN ### 3970 3971Unsigned saturating rounding shift right narrow by immediate. 3972 3973 void uqrshrn(const VRegister& vd, const VRegister& vn, int shift) 3974 3975 3976### UQRSHRN2 ### 3977 3978Unsigned saturating rounding shift right narrow by immediate (second part). 3979 3980 void uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) 3981 3982 3983### UQSHL ### 3984 3985Unsigned saturating shift left by immediate. 3986 3987 void uqshl(const VRegister& vd, const VRegister& vn, int shift) 3988 3989 3990### UQSHL ### 3991 3992Unsigned saturating shift left by register. 3993 3994 void uqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3995 3996 3997### UQSHRN ### 3998 3999Unsigned saturating shift right narrow by immediate. 4000 4001 void uqshrn(const VRegister& vd, const VRegister& vn, int shift) 4002 4003 4004### UQSHRN2 ### 4005 4006Unsigned saturating shift right narrow by immediate (second part). 4007 4008 void uqshrn2(const VRegister& vd, const VRegister& vn, int shift) 4009 4010 4011### UQSUB ### 4012 4013Unsigned saturating subtract. 4014 4015 void uqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4016 4017 4018### UQXTN ### 4019 4020Unsigned saturating extract narrow. 4021 4022 void uqxtn(const VRegister& vd, const VRegister& vn) 4023 4024 4025### UQXTN2 ### 4026 4027Unsigned saturating extract narrow (second part). 4028 4029 void uqxtn2(const VRegister& vd, const VRegister& vn) 4030 4031 4032### URECPE ### 4033 4034Unsigned reciprocal estimate. 4035 4036 void urecpe(const VRegister& vd, const VRegister& vn) 4037 4038 4039### URHADD ### 4040 4041Unsigned rounding halving add. 4042 4043 void urhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4044 4045 4046### URSHL ### 4047 4048Unsigned rounding shift left by register. 4049 4050 void urshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4051 4052 4053### URSHR ### 4054 4055Unsigned rounding shift right by immediate. 4056 4057 void urshr(const VRegister& vd, const VRegister& vn, int shift) 4058 4059 4060### URSQRTE ### 4061 4062Unsigned reciprocal square root estimate. 4063 4064 void ursqrte(const VRegister& vd, const VRegister& vn) 4065 4066 4067### URSRA ### 4068 4069Unsigned rounding shift right by immediate and accumulate. 4070 4071 void ursra(const VRegister& vd, const VRegister& vn, int shift) 4072 4073 4074### USHL ### 4075 4076Unsigned shift left by register. 4077 4078 void ushl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4079 4080 4081### USHLL ### 4082 4083Unsigned shift left long by immediate. 4084 4085 void ushll(const VRegister& vd, const VRegister& vn, int shift) 4086 4087 4088### USHLL2 ### 4089 4090Unsigned shift left long by immediate (second part). 4091 4092 void ushll2(const VRegister& vd, const VRegister& vn, int shift) 4093 4094 4095### USHR ### 4096 4097Unsigned shift right by immediate. 4098 4099 void ushr(const VRegister& vd, const VRegister& vn, int shift) 4100 4101 4102### USQADD ### 4103 4104Unsigned saturating accumulate of signed value. 4105 4106 void usqadd(const VRegister& vd, const VRegister& vn) 4107 4108 4109### USRA ### 4110 4111Unsigned shift right by immediate and accumulate. 4112 4113 void usra(const VRegister& vd, const VRegister& vn, int shift) 4114 4115 4116### USUBL ### 4117 4118Unsigned subtract long. 4119 4120 void usubl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4121 4122 4123### USUBL2 ### 4124 4125Unsigned subtract long (second part). 4126 4127 void usubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4128 4129 4130### USUBW ### 4131 4132Unsigned subtract wide. 4133 4134 void usubw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4135 4136 4137### USUBW2 ### 4138 4139Unsigned subtract wide (second part). 4140 4141 void usubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4142 4143 4144### UXTL ### 4145 4146Unsigned extend long. 4147 4148 void uxtl(const VRegister& vd, const VRegister& vn) 4149 4150 4151### UXTL2 ### 4152 4153Unsigned extend long (second part). 4154 4155 void uxtl2(const VRegister& vd, const VRegister& vn) 4156 4157 4158### UZP1 ### 4159 4160Unzip vectors (primary). 4161 4162 void uzp1(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4163 4164 4165### UZP2 ### 4166 4167Unzip vectors (secondary). 4168 4169 void uzp2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4170 4171 4172### XTN ### 4173 4174Extract narrow. 4175 4176 void xtn(const VRegister& vd, const VRegister& vn) 4177 4178 4179### XTN2 ### 4180 4181Extract narrow (second part). 4182 4183 void xtn2(const VRegister& vd, const VRegister& vn) 4184 4185 4186### ZIP1 ### 4187 4188Zip vectors (primary). 4189 4190 void zip1(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4191 4192 4193### ZIP2 ### 4194 4195Zip vectors (secondary). 4196 4197 void zip2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4198 4199 4200 4201Additional or pseudo instructions 4202--------------------------------- 4203 4204### BIND ### 4205 4206Bind a label to the current PC. 4207 4208 void bind(Label* label) 4209 4210 4211### DC32 ### 4212 4213Emit 32 bits of data into the instruction stream. 4214 4215 void dc32(uint32_t data) 4216 4217 4218### DC64 ### 4219 4220Emit 64 bits of data into the instruction stream. 4221 4222 void dc64(uint64_t data) 4223 4224 4225### DCI ### 4226 4227Emit raw instructions into the instruction stream. 4228 4229 void dci(Instr raw_inst) 4230 4231 4232### PLACE ### 4233 4234Place a literal at the current PC. 4235 4236 void place(RawLiteral* literal) 4237 4238 4239 4240