Lines Matching refs:u32
46 #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
57 #define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
62 #define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
63 #define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
64 #define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
65 #define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
66 #define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
67 #define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
70 #define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
75 #define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
76 #define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
77 #define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
78 #define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
79 #define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
80 #define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
81 #define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
82 #define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
83 #define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
84 #define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
85 #define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
86 #define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
87 #define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
88 #define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
89 #define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
90 #define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
91 #define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
92 #define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
93 #define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
94 #define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
95 #define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
96 #define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
97 #define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
98 #define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
106 #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
107 #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
117 #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
118 #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
119 #define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
120 #define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
121 #define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
122 #define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
123 #define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
124 #define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
125 #define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
126 #define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
127 #define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
128 #define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
129 #define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
130 #define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
131 #define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
132 #define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
133 #define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
134 #define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
135 #define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
136 #define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
137 #define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
145 #define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
146 #define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
147 #define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
148 #define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
149 #define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
150 #define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
151 #define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
152 #define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
153 #define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
154 #define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
155 #define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
156 #define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
157 #define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
158 #define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
159 #define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
160 #define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
161 #define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
164 #define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
165 #define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
166 #define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
167 #define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
169 #define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
172 #define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0000)
173 #define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
174 #define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
177 #define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
178 #define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
179 #define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
180 #define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
181 #define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
182 #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
183 #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
184 #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
202 #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
203 #define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
204 #define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
205 #define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
206 #define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
207 #define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
208 #define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
209 #define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
210 #define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
211 #define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
227 #define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\
238 static inline void write_tmr0(u32 val) in write_tmr0()
243 static inline void write_tmr1(u32 val) in write_tmr1()
248 static inline u32 read_tcr0(void) in read_tcr0()
250 u32 val; in read_tcr0()
255 static inline u32 read_tcr1(void) in read_tcr1()
257 u32 val; in read_tcr1()
262 static inline void write_trr0(u32 val) in write_trr0()
267 static inline void write_trr1(u32 val) in write_trr1()
272 static inline void write_tisr(u32 val) in write_tisr()
277 static inline u32 read_wdtcr(void) in read_wdtcr()
279 u32 val; in read_wdtcr()
283 static inline void write_wdtcr(u32 val) in write_wdtcr()
294 static inline u32 read_rcsr(void) in read_rcsr()
298 static inline void write_wdtsr(u32 val) in write_wdtsr()