65 	int div;  in _clk_simple_round_rate()  local
70 	div = parent_rate / rate;  in _clk_simple_round_rate()
72 		div++;  in _clk_simple_round_rate()
74 	if (div > limit)  in _clk_simple_round_rate()
75 		div = limit;  in _clk_simple_round_rate()
77 	return parent_rate / div;  in _clk_simple_round_rate()
245 	unsigned int div;  in hclk_set_rate()  local
251 	div = parent_rate / rate;  in hclk_set_rate()
253 	if (div > 16 || div < 1 || ((parent_rate / div) != rate))  in hclk_set_rate()
256 	div--;  in hclk_set_rate()
260 	reg |= div << CCM_CSCR_BCLK_OFFSET;  in hclk_set_rate()
287 	unsigned int div;  in clk48m_set_rate()  local
293 	div = parent_rate / rate;  in clk48m_set_rate()
295 	if (div > 8 || div < 1 || ((parent_rate / div) != rate))  in clk48m_set_rate()
298 	div--;  in clk48m_set_rate()
302 	reg |= div << CCM_CSCR_USB_OFFSET;  in clk48m_set_rate()
332 	unsigned int div;  in perclk1_set_rate()  local
338 	div = parent_rate / rate;  in perclk1_set_rate()
340 	if (div > 16 || div < 1 || ((parent_rate / div) != rate))  in perclk1_set_rate()
343 	div--;  in perclk1_set_rate()
347 	reg |= div << CCM_PCDR_PCLK1_OFFSET;  in perclk1_set_rate()
369 	unsigned int div;  in perclk2_set_rate()  local
375 	div = parent_rate / rate;  in perclk2_set_rate()
377 	if (div > 16 || div < 1 || ((parent_rate / div) != rate))  in perclk2_set_rate()
380 	div--;  in perclk2_set_rate()
384 	reg |= div << CCM_PCDR_PCLK2_OFFSET;  in perclk2_set_rate()
406 	unsigned int div;  in perclk3_set_rate()  local
412 	div = parent_rate / rate;  in perclk3_set_rate()
414 	if (div > 128 || div < 1 || ((parent_rate / div) != rate))  in perclk3_set_rate()
417 	div--;  in perclk3_set_rate()
421 	reg |= div << CCM_PCDR_PCLK3_OFFSET;  in perclk3_set_rate()