Lines Matching refs:omap_readw
223 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); in omap1_ckctl_recalc()
401 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; in omap1_set_ext_clk_rate()
443 ratio_bits = omap_readw(clk->enable_reg) & ~1; in omap1_init_ext_clk()
524 regval16 = omap_readw(clk->enable_reg); in omap1_clk_enable_generic()
557 regval16 = omap_readw(clk->enable_reg); in omap1_clk_disable_generic()
601 regval = omap_readw(ARM_CKCTL); in omap1_clk_set_rate()
644 regval32 = omap_readw(clk->enable_reg); in omap1_clk_disable_unused()
693 reg = omap_readw(SOFT_REQ_REG) & (1 << 4); in omap1_clk_init()
739 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), in omap1_clk_init()
740 omap_readw(ARM_CKCTL)); in omap1_clk_init()
750 unsigned pll_ctl_val = omap_readw(DPLL_CTL); in omap1_clk_init()
794 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); in omap1_clk_init()
806 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); in omap1_clk_init()
808 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); in omap1_clk_init()