Lines Matching refs:L1

690 	bool "Locate interrupt entry code in L1 Memory"
694 	  into L1 instruction memory. (less latency)
697 …bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memor…
701 	  (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
705 	bool "Locate frequently called do_irq dispatcher function in L1 Memory"
709 	  into L1 instruction memory. (less latency)
712 	bool "Locate frequently called timer_interrupt() function in L1 Memory"
716 	  into L1 instruction memory. (less latency)
719 	bool "Locate frequently idle function in L1 Memory"
723 	  into L1 instruction memory. (less latency)
726 	bool "Locate kernel schedule function in L1 Memory"
730 	  into L1 instruction memory. (less latency)
733 	bool "Locate kernel owned arithmetic functions in L1 Memory"
737 	  into L1 instruction memory. (less latency)
740 	bool "Locate access_ok function in L1 Memory"
744 	  into L1 instruction memory. (less latency)
747 	bool "Locate memset function in L1 Memory"
751 	  into L1 instruction memory. (less latency)
754 	bool "Locate memcpy function in L1 Memory"
758 	  into L1 instruction memory. (less latency)
761 	bool "Locate sys_bfin_spinlock function in L1 Memory"
765 	  into L1 instruction memory. (less latency)
768 	bool "Locate IP Checksum function in L1 Memory"
772 	  into L1 instruction memory. (less latency)
775 	bool "Locate cacheline_aligned data to L1 Data Memory"
781 	  into L1 data memory. (less latency)
784 	bool "Locate Syscall Table L1 Data Memory"
789 	  into L1 data memory. (less latency)
792 	bool "Locate CPLB Switch Tables L1 Data Memory"
797 	  into L1 data memory. (less latency)
800 	bool "Support locating application stack in L1 Scratch Memory"
803 	  If enabled the application stack can be located in L1
809 	bool "Locate exception stack in L1 Scratch Memory"
813 	  Whenever an exception occurs, use the L1 Scratch memory for
815 	  in L1 when using this option.
817 	  If you don't use L1 Scratch, then you should say Y here.
950 	  Select to make L2 SRAM cacheable in L1 data and instruction cache.
1113 	  When in the sleep mode, system DMA access to L1 memory is not supported.
1124 	  up the processor. When in the sleep mode, system DMA access to L1