Lines Matching refs:bfin_write32

59 #define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
61 #define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
63 #define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
65 #define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
67 #define bfin_write_SIC_IMASK(val)            bfin_write32(SIC_IMASK,val)
69 #define bfin_write_SIC_ISR(val)              bfin_write32(SIC_ISR,val)
71 #define bfin_write_SIC_IWR(val)              bfin_write32(SIC_IWR,val)
77 #define bfin_write_WDOG_CNT(val)             bfin_write32(WDOG_CNT,val)
79 #define bfin_write_WDOG_STAT(val)            bfin_write32(WDOG_STAT,val)
83 #define bfin_write_RTC_STAT(val)             bfin_write32(RTC_STAT,val)
91 #define bfin_write_RTC_ALARM(val)            bfin_write32(RTC_ALARM,val)
141 #define bfin_write_DMA0_NEXT_DESC_PTR(val)   bfin_write32(DMA0_NEXT_DESC_PTR,val)
143 #define bfin_write_DMA0_START_ADDR(val)      bfin_write32(DMA0_START_ADDR,val)
153 #define bfin_write_DMA0_CURR_DESC_PTR(val)   bfin_write32(DMA0_CURR_DESC_PTR,val)
155 #define bfin_write_DMA0_CURR_ADDR(val)       bfin_write32(DMA0_CURR_ADDR,val)
168 #define bfin_write_DMA1_NEXT_DESC_PTR(val)   bfin_write32(DMA1_NEXT_DESC_PTR,val)
170 #define bfin_write_DMA1_START_ADDR(val)      bfin_write32(DMA1_START_ADDR,val)
180 #define bfin_write_DMA1_CURR_DESC_PTR(val)   bfin_write32(DMA1_CURR_DESC_PTR,val)
182 #define bfin_write_DMA1_CURR_ADDR(val)       bfin_write32(DMA1_CURR_ADDR,val)
195 #define bfin_write_DMA2_NEXT_DESC_PTR(val)   bfin_write32(DMA2_NEXT_DESC_PTR,val)
197 #define bfin_write_DMA2_START_ADDR(val)      bfin_write32(DMA2_START_ADDR,val)
207 #define bfin_write_DMA2_CURR_DESC_PTR(val)   bfin_write32(DMA2_CURR_DESC_PTR,val)
209 #define bfin_write_DMA2_CURR_ADDR(val)       bfin_write32(DMA2_CURR_ADDR,val)
222 #define bfin_write_DMA3_NEXT_DESC_PTR(val)   bfin_write32(DMA3_NEXT_DESC_PTR,val)
224 #define bfin_write_DMA3_START_ADDR(val)      bfin_write32(DMA3_START_ADDR,val)
234 #define bfin_write_DMA3_CURR_DESC_PTR(val)   bfin_write32(DMA3_CURR_DESC_PTR,val)
236 #define bfin_write_DMA3_CURR_ADDR(val)       bfin_write32(DMA3_CURR_ADDR,val)
249 #define bfin_write_DMA4_NEXT_DESC_PTR(val)   bfin_write32(DMA4_NEXT_DESC_PTR,val)
251 #define bfin_write_DMA4_START_ADDR(val)      bfin_write32(DMA4_START_ADDR,val)
261 #define bfin_write_DMA4_CURR_DESC_PTR(val)   bfin_write32(DMA4_CURR_DESC_PTR,val)
263 #define bfin_write_DMA4_CURR_ADDR(val)       bfin_write32(DMA4_CURR_ADDR,val)
276 #define bfin_write_DMA5_NEXT_DESC_PTR(val)   bfin_write32(DMA5_NEXT_DESC_PTR,val)
278 #define bfin_write_DMA5_START_ADDR(val)      bfin_write32(DMA5_START_ADDR,val)
288 #define bfin_write_DMA5_CURR_DESC_PTR(val)   bfin_write32(DMA5_CURR_DESC_PTR,val)
290 #define bfin_write_DMA5_CURR_ADDR(val)       bfin_write32(DMA5_CURR_ADDR,val)
303 #define bfin_write_DMA6_NEXT_DESC_PTR(val)   bfin_write32(DMA6_NEXT_DESC_PTR,val)
305 #define bfin_write_DMA6_START_ADDR(val)      bfin_write32(DMA6_START_ADDR,val)
315 #define bfin_write_DMA6_CURR_DESC_PTR(val)   bfin_write32(DMA6_CURR_DESC_PTR,val)
317 #define bfin_write_DMA6_CURR_ADDR(val)       bfin_write32(DMA6_CURR_ADDR,val)
330 #define bfin_write_DMA7_NEXT_DESC_PTR(val)   bfin_write32(DMA7_NEXT_DESC_PTR,val)
332 #define bfin_write_DMA7_START_ADDR(val)      bfin_write32(DMA7_START_ADDR,val)
342 #define bfin_write_DMA7_CURR_DESC_PTR(val)   bfin_write32(DMA7_CURR_DESC_PTR,val)
344 #define bfin_write_DMA7_CURR_ADDR(val)       bfin_write32(DMA7_CURR_ADDR,val)
357 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
359 #define bfin_write_MDMA_D1_START_ADDR(val)   bfin_write32(MDMA_D1_START_ADDR,val)
369 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
371 #define bfin_write_MDMA_D1_CURR_ADDR(val)    bfin_write32(MDMA_D1_CURR_ADDR,val)
384 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
386 #define bfin_write_MDMA_S1_START_ADDR(val)   bfin_write32(MDMA_S1_START_ADDR,val)
396 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
398 #define bfin_write_MDMA_S1_CURR_ADDR(val)    bfin_write32(MDMA_S1_CURR_ADDR,val)
411 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
413 #define bfin_write_MDMA_D0_START_ADDR(val)   bfin_write32(MDMA_D0_START_ADDR,val)
423 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
425 #define bfin_write_MDMA_D0_CURR_ADDR(val)    bfin_write32(MDMA_D0_CURR_ADDR,val)
438 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
440 #define bfin_write_MDMA_S0_START_ADDR(val)   bfin_write32(MDMA_S0_START_ADDR,val)
450 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
452 #define bfin_write_MDMA_S0_CURR_ADDR(val)    bfin_write32(MDMA_S0_CURR_ADDR,val)
466 #define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)
468 #define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)
472 #define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)
527 #define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
529 #define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
531 #define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
536 #define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
538 #define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
540 #define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
545 #define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
547 #define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
549 #define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
568 #define bfin_write_SPORT0_TX(val)            bfin_write32(SPORT0_TX,val)
570 #define bfin_write_SPORT0_RX(val)            bfin_write32(SPORT0_RX,val)
572 #define bfin_write_SPORT0_TX32(val)          bfin_write32(SPORT0_TX,val)
574 #define bfin_write_SPORT0_RX32(val)          bfin_write32(SPORT0_RX,val)
596 #define bfin_write_SPORT0_MTCS0(val)         bfin_write32(SPORT0_MTCS0,val)
598 #define bfin_write_SPORT0_MTCS1(val)         bfin_write32(SPORT0_MTCS1,val)
600 #define bfin_write_SPORT0_MTCS2(val)         bfin_write32(SPORT0_MTCS2,val)
602 #define bfin_write_SPORT0_MTCS3(val)         bfin_write32(SPORT0_MTCS3,val)
604 #define bfin_write_SPORT0_MRCS0(val)         bfin_write32(SPORT0_MRCS0,val)
606 #define bfin_write_SPORT0_MRCS1(val)         bfin_write32(SPORT0_MRCS1,val)
608 #define bfin_write_SPORT0_MRCS2(val)         bfin_write32(SPORT0_MRCS2,val)
610 #define bfin_write_SPORT0_MRCS3(val)         bfin_write32(SPORT0_MRCS3,val)
622 #define bfin_write_SPORT1_TX(val)            bfin_write32(SPORT1_TX,val)
624 #define bfin_write_SPORT1_RX(val)            bfin_write32(SPORT1_RX,val)
626 #define bfin_write_SPORT1_TX32(val)          bfin_write32(SPORT1_TX,val)
628 #define bfin_write_SPORT1_RX32(val)          bfin_write32(SPORT1_RX,val)
650 #define bfin_write_SPORT1_MTCS0(val)         bfin_write32(SPORT1_MTCS0,val)
652 #define bfin_write_SPORT1_MTCS1(val)         bfin_write32(SPORT1_MTCS1,val)
654 #define bfin_write_SPORT1_MTCS2(val)         bfin_write32(SPORT1_MTCS2,val)
656 #define bfin_write_SPORT1_MTCS3(val)         bfin_write32(SPORT1_MTCS3,val)
658 #define bfin_write_SPORT1_MRCS0(val)         bfin_write32(SPORT1_MRCS0,val)
660 #define bfin_write_SPORT1_MRCS1(val)         bfin_write32(SPORT1_MRCS1,val)
662 #define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)
664 #define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)
736 	bfin_write32(SIC_IWR, IWR_ENABLE(0));
742 	bfin_write32(SIC_IWR, iwr);
758 	bfin_write32(SIC_IWR, IWR_ENABLE(0));  in bfin_write_VR_CTL()
764 	bfin_write32(SIC_IWR, iwr);  in bfin_write_VR_CTL()