Lines Matching refs:P0

23 	P0.H = hi(PLL_CTL);
24 	P0.L = lo(PLL_CTL);
25 	R1 = W[P0](z);
27 	W[P0] = R1.L;
42 	P0.H = hi(PLL_CTL);
43 	P0.L = lo(PLL_CTL);
71 	P0.H = hi(VR_CTL);
72 	P0.L = lo(VR_CTL);
74 	W[P0] = R3.L;
101 	P0.H = hi(PLL_DIV);
102 	P0.L = lo(PLL_DIV);
103 	R6 = W[P0](z);
105 	W[P0] = R0.l;		/* Set Max VCO to SCLK divider */
107 	P0.H = hi(PLL_CTL);
108 	P0.L = lo(PLL_CTL);
109 	R5 = W[P0](z);
111 	W[P0] = R0.l;		/* Set Min CLKIN to VCO multiplier */
118 	P0.H = hi(VR_CTL);
119 	P0.L = lo(VR_CTL);
120 	R7 = W[P0](z);
127 	W[P0] = R2;		/* Set Min Core Voltage */
139 	P0.H = hi(PLL_CTL);
140 	P0.L = lo(PLL_CTL);
141 	R0 = W[P0](z);
143 	W[P0] = R0.L;		/* Turn CCLK OFF */
155 	P0.H = hi(VR_CTL);
156 	P0.L = lo(VR_CTL);
157 	W[P0]= R7;
164 	P0.H = hi(PLL_DIV);
165 	P0.L = lo(PLL_DIV);
166 	W[P0]= R6;		/* Restore CCLK and SCLK divider */
168 	P0.H = hi(PLL_CTL);
169 	P0.L = lo(PLL_CTL);
187 	P0.H = hi(EBIU_RSTCTL);
188 	P0.L = lo(EBIU_RSTCTL);
189 	R2 = [P0];
191 	[P0] = R2;
194 	R2 = [P0];
198 	P0.L = lo(EBIU_SDGCTL);
199 	P0.H = hi(EBIU_SDGCTL);
200 	R2 = [P0];
202 	[P0] = R2;
205 	P0.L = lo(EBIU_SDSTAT);
206 	P0.H = hi(EBIU_SDSTAT);
208 	R2 = w[P0];
213 	P0.L = lo(EBIU_SDGCTL);
214 	P0.H = hi(EBIU_SDGCTL);
215 	R2 = [P0];
217 	[P0] = R2;
225 	P0.H = hi(EBIU_RSTCTL);
226 	P0.L = lo(EBIU_RSTCTL);
227 	R2 = [P0];
229 	[P0] = R2;
232 	P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
233 	P0.H = hi(EBIU_SDGCTL);
234 	R2 = [P0];
236 	[P0] = R2
239 	P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
240 	P0.H = hi(EBIU_SDGCTL);
241 	R2 = [P0];
243 	[P0] = R2
252 	P0.H = hi(SIC_IWR0);
253 	P0.L = lo(SIC_IWR0);
263 	P0.H = hi(SIC_IWR);
264 	P0.L = lo(SIC_IWR);
266 	[P0] = R0;
274 	P0.H = hi(RTC_ISTAT);
275 	P0.L = lo(RTC_ISTAT);
276 	w[P0] = R0.L;
288 	P0.H = hi(PLL_STAT);
289 	P0.L = lo(PLL_STAT);
291 	R0 = W[P0] (Z);
304 	P0.H = hi(PLL_CTL);
305 	P0.L = lo(PLL_CTL);
410 	P0.H = hi(SRAM_BASE_ADDRESS);
411 	P0.L = lo(SRAM_BASE_ADDRESS);
554 	P0.H = 0;
555 	P0.L = 0;
558 	[P0++] = R0;	/* Store Hibernate Magic */
561 	[P0++] = R0;	/* Save Return Address */
562 	[P0++] = SP;	/* Save Stack Pointer */
563 	P0.H = _hibernate_mode;
564 	P0.L = _hibernate_mode;
566 	call (P0); /* Goodbye */
715 	P0.H = hi(PLL_CTL);
716 	P0.L = lo(PLL_CTL);