Lines Matching refs:gr31
75 movgs gr31,psr
114 movgs gr31,psr
151 srlicc.p gr31,#26,gr0,icc0
153 srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
163 and gr31,gr30,gr31
165 add gr30,gr31,gr31
166 ldi @(gr31,#0),gr30 /* fetch the PTE */
170 sti.p gr30,@(gr31,#0) /* update the PTE */
177 movsg iampr1,gr31
178 andicc gr31,#xAMPRx_V,gr0,icc0
179 setlos.p 0xfffff000,gr31
182 movsg iamlr1,gr31
183 movgs gr31,tplr /* set TPLR.CXN */
184 tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
186 movsg dampr1,gr31
187 ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
188 movgs gr31,tppr
189 movsg iamlr1,gr31 /* set TPLR.CXN */
190 movgs gr31,tplr
191 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
192 movsg tpxr,gr31 /* check the TLB write error flag */
193 andicc.p gr31,#TPXR_E,gr0,icc0
194 setlos #0xfffff000,gr31
200 and gr29,gr31,gr29
201 movsg cxnr,gr31
202 or gr29,gr31,gr29
306 movsg dampr1,gr31
307 andicc gr31,#xAMPRx_V,gr0,icc0
308 setlos.p 0xfffff000,gr31
311 movsg damlr1,gr31
312 movgs gr31,tplr /* set TPLR.CXN */
313 tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
315 movsg dampr1,gr31
316 ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
317 movgs gr31,tppr
318 movsg damlr1,gr31 /* set TPLR.CXN */
319 movgs gr31,tplr
320 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
321 movsg tpxr,gr31 /* check the TLB write error flag */
322 andicc.p gr31,#TPXR_E,gr0,icc0
323 setlos #0xfffff000,gr31
329 and gr29,gr31,gr29
330 movsg cxnr,gr31
331 or gr29,gr31,gr29
432 movsg dampr1,gr31
433 andicc gr31,#xAMPRx_V,gr0,icc0
434 setlos.p 0xfffff000,gr31
437 movsg dampr1,gr31
438 movgs gr31,tppr
439 movsg damlr1,gr31 /* set TPLR.CXN */
440 movgs gr31,tplr
441 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
442 movsg tpxr,gr31 /* check the TLB write error flag */
443 andicc.p gr31,#TPXR_E,gr0,icc0
444 setlos #0xfffff000,gr31
450 and gr28,gr31,gr28
451 movsg cxnr,gr31
452 or gr28,gr31,gr28
552 movsg dampr1,gr31
553 andicc gr31,#xAMPRx_V,gr0,icc0
554 setlos.p 0xfffff000,gr31
557 movsg dampr1,gr31
558 movgs gr31,tppr
559 movsg damlr1,gr31 /* set TPLR.CXN */
560 movgs gr31,tplr
561 tlbpr gr31,gr0,#2,#0 /* save to the TLB */
562 movsg tpxr,gr31 /* check the TLB write error flag */
563 andicc.p gr31,#TPXR_E,gr0,icc0
564 setlos #0xfffff000,gr31
570 and gr28,gr31,gr28
571 movsg cxnr,gr31
572 or gr28,gr31,gr28
599 and gr31,gr30,gr31
604 srli gr28,#26,gr31 /* calculate PGE offset */
605 slli gr31,#8,gr31 /* and clear bottom bits */
608 ld @(gr31,gr30),gr30 /* access the PGE */
616 slli.p gr31,#18,gr31
619 movgs gr31,scr1
623 srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */