114 	unsigned int io;  member
165 	au_writel(DMA_BE0, chan->io + DMA_MODE_SET);  in enable_dma_buffer0()
174 	au_writel(DMA_BE1, chan->io + DMA_MODE_SET);  in enable_dma_buffer1()
182 	au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);  in enable_dma_buffers()
191 	au_writel(DMA_GO, chan->io + DMA_MODE_SET);  in start_dma()
203 	au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);  in halt_dma()
207 		if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)  in halt_dma()
223 	au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);  in disable_dma()
232 	return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;  in dma_halted()
247 	au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);  in init_dma()
253 	au_writel(~mode, chan->io + DMA_MODE_CLEAR);  in init_dma()
254 	au_writel(mode,  chan->io + DMA_MODE_SET);  in init_dma()
291 	return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;  in get_dma_active_buffer()
312 	au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);  in set_dma_fifo_addr()
324 	au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);  in clear_dma_done0()
333 	au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);  in clear_dma_done1()
352 	au_writel(a, chan->io + DMA_BUFFER0_START);  in set_dma_addr0()
364 	au_writel(a, chan->io + DMA_BUFFER1_START);  in set_dma_addr1()
378 	au_writel(count, chan->io + DMA_BUFFER0_COUNT);  in set_dma_count0()
391 	au_writel(count, chan->io + DMA_BUFFER1_COUNT);  in set_dma_count1()
404 	au_writel(count, chan->io + DMA_BUFFER0_COUNT);  in set_dma_count()
405 	au_writel(count, chan->io + DMA_BUFFER1_COUNT);  in set_dma_count()
418 	return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);  in get_dma_buffer_done()
445 	curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?  in get_dma_residue()
448 	count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;  in get_dma_residue()