Lines Matching refs:u32

49 	u32	ddma_config;
50 	u32	ddma_intstat;
51 	u32	ddma_throttle;
52 	u32	ddma_inten;
64 	u32	ddma_cfg;	/* See below */
65 	u32	ddma_desptr;	/* 32-byte aligned pointer to descriptor */
66 	u32	ddma_statptr;	/* word aligned pointer to status word */
67 	u32	ddma_dbell;	/* A write activates channel operation */
68 	u32	ddma_irq;	/* If bit 0 set, interrupt pending */
69 	u32	ddma_stat;	/* See below */
70 	u32	ddma_bytecnt;	/* Byte count, valid only when chan idle */
101 	u32	dscr_cmd0;		/* See below */
102 	u32	dscr_cmd1;		/* See below */
103 	u32	dscr_source0;		/* source phys address */
104 	u32	dscr_source1;		/* See below */
105 	u32	dscr_dest0;		/* Destination address */
106 	u32	dscr_dest1;		/* See below */
107 	u32	dscr_stat;		/* completion status */
108 	u32	dscr_nxtptr;		/* Next descriptor pointer (mostly) */
113 	u32	sw_status;
114 	u32 	sw_context;
115 	u32	sw_reserved[6];
289 	u32	dev_id;
290 	u32	dev_flags;
291 	u32	dev_tsize;
292 	u32	dev_devwidth;
293 	u32	dev_physaddr;		/* If FIFO */
294 	u32	dev_intlevel;
295 	u32	dev_intpolarity;
302 	u32			chan_flags;
303 	u32			chan_index;
328 extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
335 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
338 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
341 u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
342 u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
345 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
347 void au1xxx_dbdma_stop(u32 chanid);
348 void au1xxx_dbdma_start(u32 chanid);
349 void au1xxx_dbdma_reset(u32 chanid);
350 u32 au1xxx_get_dma_residue(u32 chanid);
352 void au1xxx_dbdma_chan_free(u32 chanid);
353 void au1xxx_dbdma_dump(u32 chanid);
355 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
357 u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
358 extern void au1xxx_ddma_del_device(u32 devid);