Lines Matching refs:v0
31 dmfc0 v0, CP0_CVMMEMCTL_REG
33 dins v0, $0, 0, 6
34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
39 or v0, v0, 0x5001
40 xor v0, v0, 0x1001
43 or v0, v0, 0x5001
44 xor v0, v0, 0x5001
49 or v0, v0, 0x2000
54 xor v0, v0, 0x2000
62 or v0, v0, 0x400
64 or v0, v0, 0x2000
67 dmtc0 v0, CP0_CVMCTL_REG
72 rdhwr v0, $0