Lines Matching refs:MIPSInst_RT
126 switch (MIPSInst_RT(*i)) { in isBranchInstr()
267 DITOREG(val, MIPSInst_RT(ir)); in cop1Emulate()
277 DIFROMREG(val, MIPSInst_RT(ir)); in cop1Emulate()
295 SITOREG(val, MIPSInst_RT(ir)); in cop1Emulate()
305 SIFROMREG(val, MIPSInst_RT(ir)); in cop1Emulate()
319 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
320 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
327 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
333 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
334 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
341 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
354 MIPSInst_RT(ir), value); in cop1Emulate()
361 if (MIPSInst_RT(ir)) in cop1Emulate()
362 xcp->regs[MIPSInst_RT(ir)] = value; in cop1Emulate()
370 if (MIPSInst_RT(ir) == 0) in cop1Emulate()
373 value = xcp->regs[MIPSInst_RT(ir)]; in cop1Emulate()
381 MIPSInst_RT(ir), value); in cop1Emulate()
401 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
405 switch (MIPSInst_RT(ir) & 3) { in cop1Emulate()
507 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
508 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) in cop1Emulate()