Lines Matching refs:r11
113 mtspr SPRN_SPRG1,r11; \
119 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
120 andi. r11,r11,MSR_PR; \
121 tophys(r11,r1); /* use tophys(r1) if kernel */ \
123 mfspr r11,SPRN_SPRG3; \
124 lwz r11,THREAD_INFO-THREAD(r11); \
125 addi r11,r11,THREAD_SIZE; \
126 tophys(r11,r11); \
127 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
131 CLR_TOP32(r11); \
132 stw r10,_CCR(r11); /* save registers */ \
133 stw r12,GPR12(r11); \
134 stw r9,GPR9(r11); \
136 stw r10,GPR10(r11); \
138 stw r12,GPR11(r11); \
140 stw r10,_LINK(r11); \
143 stw r1,GPR1(r11); \
144 stw r1,0(r11); \
145 tovirt(r1,r11); /* set new kernel sp */ \
148 stw r0,GPR0(r11); \
149 SAVE_4GPRS(3, r11); \
150 SAVE_2GPRS(7, r11)
172 stw r10,_TRAP(r11); \
207 stw r4,_DAR(r11)
209 stw r5,_DSISR(r11)
221 stw r10,_DSISR(r11)
245 stw r4,_DAR(r11)
247 stw r5,_DSISR(r11)
299 stw r11, 4(r0)
302 addi r11, r10, 0x1000
303 tlbie r11
304 addi r11, r10, -0x1000
305 tlbie r11
314 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
316 lis r11, swapper_pg_dir@h
317 ori r11, r11, swapper_pg_dir@l
318 rlwimi r10, r11, 0, 2, 19
320 lwz r11, 0(r10) /* Get the level 1 entry */
321 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
327 ori r11,r11,1 /* Set valid bit */
329 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
331 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
332 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
333 lwz r10, 0(r11) /* Get the pte */
337 andi. r11, r10, _PAGE_PRESENT
340 mfspr r11, SPRN_MD_TWC /* get the pte address again */
341 stw r10, 0(r11)
345 stw r10, 0(r11)
354 2: li r11, 0x00f0
355 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
360 lwz r11, 0(r0)
361 mtcr r11
362 lwz r11, 4(r0)
377 stw r11, 4(r0)
383 andi. r11, r10, 0x0800
385 lis r11, swapper_pg_dir@h
386 ori r11, r11, swapper_pg_dir@l
387 rlwimi r10, r11, 0, 2, 19
389 lwz r11, 0(r10) /* Get the level 1 entry */
390 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
395 ori r11, r11, 1 /* Set valid bit in physical L2 page */
397 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
407 rlwimi r11, r10, 0, 27, 27
409 mtspr SPRN_MD_TWC, r11
413 andi. r11, r10, _PAGE_PRESENT
421 mfspr r11, SPRN_MD_TWC /* get the pte address again */
422 stw r10, 0(r11)
430 2: li r11, 0x00f0
431 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
436 lwz r11, 0(r0)
437 mtcr r11
438 lwz r11, 4(r0)
469 stw r11, 4(r0)
474 andis. r11, r10, 0x0200 /* If set, indicates store op */
494 rlwinm r11, r10, 0, 0, 19
495 ori r11, r11, MD_EVALID
497 rlwimi r11, r10, 0, 28, 31
499 mtspr SPRN_MD_EPN, r11
506 andi. r11, r10, 0x0800
508 lis r11, swapper_pg_dir@h
509 ori r11, r11, swapper_pg_dir@l
510 rlwimi r10, r11, 0, 2, 19
512 lwz r11, 0(r10) /* Get the level 1 entry */
513 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
518 ori r11, r11, 1 /* Set valid bit in physical L2 page */
520 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
521 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
522 lwz r10, 0(r11) /* Get the pte */
524 andi. r11, r10, _PAGE_RW /* Is it writeable? */
532 andi. r11, r10, _PAGE_PRESENT
539 mfspr r11, SPRN_MD_TWC /* Get pte address again */
540 stw r10, 0(r11) /* and update pte in table */
548 li r11, 0x00f0
549 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
554 lwz r11, 0(r0)
555 mtcr r11
556 lwz r11, 4(r0)
563 lwz r11, 0(r0)
564 mtcr r11
565 lwz r11, 4(r0)
762 li r11, MI_BOOTINIT /* Create RPN for address 0 */
763 addis r11, r11, 0x0080 /* Add 8M */
764 mtspr SPRN_MD_RPN, r11
769 addis r11, r11, 0x0080 /* Add 8M */
770 mtspr SPRN_MD_RPN, r11