Lines Matching refs:r21
186 movi MMUIR_FIRST, r21
189 putcfg r21, 0, ZERO /* Clear MMUIR[n].PTEH.V */
190 addi r21, MMUIR_STEP, r21
191 bne r21, r22, tr1
195 movi MMUDR_FIRST, r21
198 putcfg r21, 0, ZERO /* Clear MMUDR[n].PTEH.V */
199 addi r21, MMUDR_STEP, r21
200 bne r21, r22, tr1
203 movi MMUIR_FIRST, r21
206 putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */
209 putcfg r21, 0, r22 /* Set MMUIR[0].PTEH */
212 movi MMUDR_FIRST, r21
215 putcfg r21, 1, r22 /* Set MMUDR[0].PTEL */
218 putcfg r21, 0, r22 /* Set MMUDR[0].PTEH */
224 addi r21, MMUDR_STEP, r21
227 putcfg r21, 1, r22 /* PTEL first */
230 putcfg r21, 0, r22 /* PTEH last */
237 movi ICCR_BASE, r21
240 putcfg r21, ICCR_REG0, r22
241 putcfg r21, ICCR_REG1, r23
244 movi OCCR_BASE, r21
247 putcfg r21, OCCR_REG0, r22
248 putcfg r21, OCCR_REG1, r23
256 getcon SR, r21
258 or r21, r22, r21
259 putcon r21, SSR
299 getcon SR, r21
301 and r21, r22, r22
304 xor r21, r22, r21
305 shlri r21, 15, r21 /* Supposedly 0/1 */
306 st.q r31, 0 , r21 /* Set fpu_in_use */
308 movi 0, r21
309 st.q r31, 0 , r21 /* Set fpu_in_use */
311 or r21, ZERO, r31 /* Set FPU flag at last */