71 	u32 l, h;  in intel_init_thermal()  local
86 	rdmsr(MSR_IA32_MISC_ENABLE, l, h);  in intel_init_thermal()
87 	h = apic_read(APIC_LVTTHMR);  in intel_init_thermal()
88 	if ((l & (1<<3)) && (h & APIC_DM_SMI)) {  in intel_init_thermal()
95 	if (h & APIC_VECTOR_MASK) {  in intel_init_thermal()
98 			cpu, (h & APIC_VECTOR_MASK));  in intel_init_thermal()
103 	h = THERMAL_APIC_VECTOR;		/* our delivery vector */  in intel_init_thermal()
104 	h |= (APIC_DM_FIXED | APIC_LVT_MASKED);	/* we'll mask till we're ready */  in intel_init_thermal()
105 	apic_write(APIC_LVTTHMR, h);  in intel_init_thermal()
107 	rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);  in intel_init_thermal()
108 	wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);  in intel_init_thermal()
113 	rdmsr(MSR_IA32_MISC_ENABLE, l, h);  in intel_init_thermal()
114 	wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);  in intel_init_thermal()
130 	u32 h;  in intel_get_extended_msrs()  local
132 	rdmsr(MSR_IA32_MCG_EAX, r->eax, h);  in intel_get_extended_msrs()
133 	rdmsr(MSR_IA32_MCG_EBX, r->ebx, h);  in intel_get_extended_msrs()
134 	rdmsr(MSR_IA32_MCG_ECX, r->ecx, h);  in intel_get_extended_msrs()
135 	rdmsr(MSR_IA32_MCG_EDX, r->edx, h);  in intel_get_extended_msrs()
136 	rdmsr(MSR_IA32_MCG_ESI, r->esi, h);  in intel_get_extended_msrs()
137 	rdmsr(MSR_IA32_MCG_EDI, r->edi, h);  in intel_get_extended_msrs()
138 	rdmsr(MSR_IA32_MCG_EBP, r->ebp, h);  in intel_get_extended_msrs()
139 	rdmsr(MSR_IA32_MCG_ESP, r->esp, h);  in intel_get_extended_msrs()
140 	rdmsr(MSR_IA32_MCG_EFLAGS, r->eflags, h);  in intel_get_extended_msrs()
141 	rdmsr(MSR_IA32_MCG_EIP, r->eip, h);  in intel_get_extended_msrs()
223 	u32 l, h;  in intel_p4_mcheck_init()  local
230 	rdmsr(MSR_IA32_MCG_CAP, l, h);  in intel_p4_mcheck_init()
245 	rdmsr(MSR_IA32_MCG_CAP, l, h);  in intel_p4_mcheck_init()