Lines Matching refs:BIT8
506 #define RXSTATUS_SHORT_FRAME BIT8
507 #define RXSTATUS_CODE_VIOLATION BIT8
568 #define MISCSTATUS_DSR BIT8
591 #define SICR_DSR_INACTIVE BIT8
592 #define SICR_DSR (BIT9+BIT8)
1649 usc_OutDmaReg(info, CDIR, BIT8+BIT0 ); in mgsl_isr_transmit_dma()
4861 RegValue |= BIT9 + BIT8; in usc_set_sdlc_mode()
4863 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
5030 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break; in usc_set_sdlc_mode()
5034 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break; in usc_set_sdlc_mode()
5081 info->mbre_bit = BIT8; in usc_set_sdlc_mode()
5082 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */ in usc_set_sdlc_mode()
5194 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break; in usc_set_sdlc_mode()
5195 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break; in usc_set_sdlc_mode()
5197 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break; in usc_set_sdlc_mode()
6144 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1)) in usc_loopback_frame()
7348 if ( status & (BIT8 + BIT3 + BIT1) ) { in mgsl_dma_test()