Lines Matching refs:BIT4
380 #define MASK_OVERRUN BIT4
416 #define IRQ_RI BIT4
2183 if (status & (BIT5 + BIT4)) { in isr_rdma()
2208 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4011 case 6: val |= BIT4; break; in async_mode()
4013 case 8: val |= BIT5 + BIT4; break; in async_mode()
4051 case 6: val |= BIT4; break; in async_mode()
4053 case 8: val |= BIT5 + BIT4; break; in async_mode()
4159 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; in sync_mode()
4160 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4249 val |= BIT4; /* 100, rxclk = DPLL */ in sync_mode()
4322 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; in tx_set_idle()
4327 tcr &= ~(BIT5 + BIT4); in tx_set_idle()
4400 val |= BIT4; in msc_set_vcr()