Lines Matching refs:OUT_RING
476 OUT_RING(GFX_OP_COLOR_FACTOR); in i810EmitContextVerified()
477 OUT_RING(code[I810_CTXREG_CF1]); in i810EmitContextVerified()
479 OUT_RING(GFX_OP_STIPPLE); in i810EmitContextVerified()
480 OUT_RING(code[I810_CTXREG_ST1]); in i810EmitContextVerified()
487 OUT_RING(tmp); in i810EmitContextVerified()
494 OUT_RING(0); in i810EmitContextVerified()
508 OUT_RING(GFX_OP_MAP_INFO); in i810EmitTexVerified()
509 OUT_RING(code[I810_TEXREG_MI1]); in i810EmitTexVerified()
510 OUT_RING(code[I810_TEXREG_MI2]); in i810EmitTexVerified()
511 OUT_RING(code[I810_TEXREG_MI3]); in i810EmitTexVerified()
518 OUT_RING(tmp); in i810EmitTexVerified()
525 OUT_RING(0); in i810EmitTexVerified()
543 OUT_RING(CMD_OP_DESTBUFFER_INFO); in i810EmitDestVerified()
544 OUT_RING(tmp); in i810EmitDestVerified()
551 OUT_RING(CMD_OP_Z_BUFFER_INFO); in i810EmitDestVerified()
552 OUT_RING(dev_priv->zi1); in i810EmitDestVerified()
554 OUT_RING(GFX_OP_DESTBUFFER_VARS); in i810EmitDestVerified()
555 OUT_RING(code[I810_DESTREG_DV1]); in i810EmitDestVerified()
557 OUT_RING(GFX_OP_DRAWRECT_INFO); in i810EmitDestVerified()
558 OUT_RING(code[I810_DESTREG_DR1]); in i810EmitDestVerified()
559 OUT_RING(code[I810_DESTREG_DR2]); in i810EmitDestVerified()
560 OUT_RING(code[I810_DESTREG_DR3]); in i810EmitDestVerified()
561 OUT_RING(code[I810_DESTREG_DR4]); in i810EmitDestVerified()
562 OUT_RING(0); in i810EmitDestVerified()
640 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); in i810_dma_dispatch_clear()
641 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); in i810_dma_dispatch_clear()
642 OUT_RING((height << 16) | width); in i810_dma_dispatch_clear()
643 OUT_RING(start); in i810_dma_dispatch_clear()
644 OUT_RING(clear_color); in i810_dma_dispatch_clear()
645 OUT_RING(0); in i810_dma_dispatch_clear()
651 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); in i810_dma_dispatch_clear()
652 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); in i810_dma_dispatch_clear()
653 OUT_RING((height << 16) | width); in i810_dma_dispatch_clear()
654 OUT_RING(dev_priv->back_offset + start); in i810_dma_dispatch_clear()
655 OUT_RING(clear_color); in i810_dma_dispatch_clear()
656 OUT_RING(0); in i810_dma_dispatch_clear()
662 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); in i810_dma_dispatch_clear()
663 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); in i810_dma_dispatch_clear()
664 OUT_RING((height << 16) | width); in i810_dma_dispatch_clear()
665 OUT_RING(dev_priv->depth_offset + start); in i810_dma_dispatch_clear()
666 OUT_RING(clear_zval); in i810_dma_dispatch_clear()
667 OUT_RING(0); in i810_dma_dispatch_clear()
703 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4); in i810_dma_dispatch_swap()
704 OUT_RING(pitch | (0xCC << 16)); in i810_dma_dispatch_swap()
705 OUT_RING((h << 16) | (w * cpp)); in i810_dma_dispatch_swap()
707 OUT_RING(dev_priv->front_offset + start); in i810_dma_dispatch_swap()
709 OUT_RING(dev_priv->back_offset + start); in i810_dma_dispatch_swap()
710 OUT_RING(pitch); in i810_dma_dispatch_swap()
712 OUT_RING(dev_priv->back_offset + start); in i810_dma_dispatch_swap()
714 OUT_RING(dev_priv->front_offset + start); in i810_dma_dispatch_swap()
761 OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | in i810_dma_dispatch_vertex()
763 OUT_RING(GFX_OP_SCISSOR_INFO); in i810_dma_dispatch_vertex()
764 OUT_RING(box[i].x1 | (box[i].y1 << 16)); in i810_dma_dispatch_vertex()
765 OUT_RING((box[i].x2 - in i810_dma_dispatch_vertex()
771 OUT_RING(CMD_OP_BATCH_BUFFER); in i810_dma_dispatch_vertex()
772 OUT_RING(start | BB1_PROTECTED); in i810_dma_dispatch_vertex()
773 OUT_RING(start + used - 4); in i810_dma_dispatch_vertex()
774 OUT_RING(0); in i810_dma_dispatch_vertex()
787 OUT_RING(CMD_STORE_DWORD_IDX); in i810_dma_dispatch_vertex()
788 OUT_RING(20); in i810_dma_dispatch_vertex()
789 OUT_RING(dev_priv->counter); in i810_dma_dispatch_vertex()
790 OUT_RING(CMD_STORE_DWORD_IDX); in i810_dma_dispatch_vertex()
791 OUT_RING(buf_priv->my_use_idx); in i810_dma_dispatch_vertex()
792 OUT_RING(I810_BUF_FREE); in i810_dma_dispatch_vertex()
793 OUT_RING(CMD_REPORT_HEAD); in i810_dma_dispatch_vertex()
794 OUT_RING(0); in i810_dma_dispatch_vertex()
812 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); in i810_dma_dispatch_flip()
813 OUT_RING(0); in i810_dma_dispatch_flip()
821 OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ ); in i810_dma_dispatch_flip()
823 OUT_RING(dev_priv->back_offset); in i810_dma_dispatch_flip()
826 OUT_RING(dev_priv->front_offset); in i810_dma_dispatch_flip()
829 OUT_RING(0); in i810_dma_dispatch_flip()
833 OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP); in i810_dma_dispatch_flip()
834 OUT_RING(0); in i810_dma_dispatch_flip()
853 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); in i810_dma_quiescent()
854 OUT_RING(CMD_REPORT_HEAD); in i810_dma_quiescent()
855 OUT_RING(0); in i810_dma_quiescent()
856 OUT_RING(0); in i810_dma_quiescent()
872 OUT_RING(CMD_REPORT_HEAD); in i810_flush_queue()
873 OUT_RING(0); in i810_flush_queue()
1083 OUT_RING(CMD_OP_BATCH_BUFFER); in i810_dma_dispatch_mc()
1084 OUT_RING(start | BB1_PROTECTED); in i810_dma_dispatch_mc()
1085 OUT_RING(start + used - 4); in i810_dma_dispatch_mc()
1086 OUT_RING(0); in i810_dma_dispatch_mc()
1090 OUT_RING(CMD_STORE_DWORD_IDX); in i810_dma_dispatch_mc()
1091 OUT_RING(buf_priv->my_use_idx); in i810_dma_dispatch_mc()
1092 OUT_RING(I810_BUF_FREE); in i810_dma_dispatch_mc()
1093 OUT_RING(0); in i810_dma_dispatch_mc()
1095 OUT_RING(CMD_STORE_DWORD_IDX); in i810_dma_dispatch_mc()
1096 OUT_RING(16); in i810_dma_dispatch_mc()
1097 OUT_RING(last_render); in i810_dma_dispatch_mc()
1098 OUT_RING(0); in i810_dma_dispatch_mc()