Lines Matching refs:OUT_RING
435 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); in radeon_emit_clip_rect()
436 OUT_RING((box->y1 << 16) | box->x1); in radeon_emit_clip_rect()
437 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); in radeon_emit_clip_rect()
438 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); in radeon_emit_clip_rect()
467 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); in radeon_emit_state()
468 OUT_RING(ctx->pp_misc); in radeon_emit_state()
469 OUT_RING(ctx->pp_fog_color); in radeon_emit_state()
470 OUT_RING(ctx->re_solid_color); in radeon_emit_state()
471 OUT_RING(ctx->rb3d_blendcntl); in radeon_emit_state()
472 OUT_RING(ctx->rb3d_depthoffset); in radeon_emit_state()
473 OUT_RING(ctx->rb3d_depthpitch); in radeon_emit_state()
474 OUT_RING(ctx->rb3d_zstencilcntl); in radeon_emit_state()
475 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2)); in radeon_emit_state()
476 OUT_RING(ctx->pp_cntl); in radeon_emit_state()
477 OUT_RING(ctx->rb3d_cntl); in radeon_emit_state()
478 OUT_RING(ctx->rb3d_coloroffset); in radeon_emit_state()
479 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); in radeon_emit_state()
480 OUT_RING(ctx->rb3d_colorpitch); in radeon_emit_state()
486 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0)); in radeon_emit_state()
487 OUT_RING(ctx->se_coord_fmt); in radeon_emit_state()
493 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1)); in radeon_emit_state()
494 OUT_RING(ctx->re_line_pattern); in radeon_emit_state()
495 OUT_RING(ctx->re_line_state); in radeon_emit_state()
496 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0)); in radeon_emit_state()
497 OUT_RING(ctx->se_line_width); in radeon_emit_state()
503 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0)); in radeon_emit_state()
504 OUT_RING(ctx->pp_lum_matrix); in radeon_emit_state()
505 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1)); in radeon_emit_state()
506 OUT_RING(ctx->pp_rot_matrix_0); in radeon_emit_state()
507 OUT_RING(ctx->pp_rot_matrix_1); in radeon_emit_state()
513 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2)); in radeon_emit_state()
514 OUT_RING(ctx->rb3d_stencilrefmask); in radeon_emit_state()
515 OUT_RING(ctx->rb3d_ropcntl); in radeon_emit_state()
516 OUT_RING(ctx->rb3d_planemask); in radeon_emit_state()
522 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5)); in radeon_emit_state()
523 OUT_RING(ctx->se_vport_xscale); in radeon_emit_state()
524 OUT_RING(ctx->se_vport_xoffset); in radeon_emit_state()
525 OUT_RING(ctx->se_vport_yscale); in radeon_emit_state()
526 OUT_RING(ctx->se_vport_yoffset); in radeon_emit_state()
527 OUT_RING(ctx->se_vport_zscale); in radeon_emit_state()
528 OUT_RING(ctx->se_vport_zoffset); in radeon_emit_state()
534 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0)); in radeon_emit_state()
535 OUT_RING(ctx->se_cntl); in radeon_emit_state()
536 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0)); in radeon_emit_state()
537 OUT_RING(ctx->se_cntl_status); in radeon_emit_state()
543 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0)); in radeon_emit_state()
544 OUT_RING(ctx->re_misc); in radeon_emit_state()
556 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5)); in radeon_emit_state()
557 OUT_RING(tex[0].pp_txfilter); in radeon_emit_state()
558 OUT_RING(tex[0].pp_txformat); in radeon_emit_state()
559 OUT_RING(tex[0].pp_txoffset); in radeon_emit_state()
560 OUT_RING(tex[0].pp_txcblend); in radeon_emit_state()
561 OUT_RING(tex[0].pp_txablend); in radeon_emit_state()
562 OUT_RING(tex[0].pp_tfactor); in radeon_emit_state()
563 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0)); in radeon_emit_state()
564 OUT_RING(tex[0].pp_border_color); in radeon_emit_state()
576 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5)); in radeon_emit_state()
577 OUT_RING(tex[1].pp_txfilter); in radeon_emit_state()
578 OUT_RING(tex[1].pp_txformat); in radeon_emit_state()
579 OUT_RING(tex[1].pp_txoffset); in radeon_emit_state()
580 OUT_RING(tex[1].pp_txcblend); in radeon_emit_state()
581 OUT_RING(tex[1].pp_txablend); in radeon_emit_state()
582 OUT_RING(tex[1].pp_tfactor); in radeon_emit_state()
583 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0)); in radeon_emit_state()
584 OUT_RING(tex[1].pp_border_color); in radeon_emit_state()
596 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5)); in radeon_emit_state()
597 OUT_RING(tex[2].pp_txfilter); in radeon_emit_state()
598 OUT_RING(tex[2].pp_txformat); in radeon_emit_state()
599 OUT_RING(tex[2].pp_txoffset); in radeon_emit_state()
600 OUT_RING(tex[2].pp_txcblend); in radeon_emit_state()
601 OUT_RING(tex[2].pp_txablend); in radeon_emit_state()
602 OUT_RING(tex[2].pp_tfactor); in radeon_emit_state()
603 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0)); in radeon_emit_state()
604 OUT_RING(tex[2].pp_border_color); in radeon_emit_state()
621 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1)); in radeon_emit_state2()
622 OUT_RING(state->context2.se_zbias_factor); in radeon_emit_state2()
623 OUT_RING(state->context2.se_zbias_constant); in radeon_emit_state2()
767 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); in radeon_clear_box()
768 OUT_RING(0xffffffff); in radeon_clear_box()
773 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); in radeon_clear_box()
774 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_clear_box()
781 OUT_RING(dev_priv->front_pitch_offset); in radeon_clear_box()
783 OUT_RING(dev_priv->back_pitch_offset); in radeon_clear_box()
786 OUT_RING(color); in radeon_clear_box()
788 OUT_RING((x << 16) | y); in radeon_clear_box()
789 OUT_RING((w << 16) | h); in radeon_clear_box()
889 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); in radeon_cp_dispatch_clear()
890 OUT_RING(clear->color_mask); in radeon_cp_dispatch_clear()
910 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
912 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_clear()
920 OUT_RING(dev_priv->front_pitch_offset); in radeon_cp_dispatch_clear()
921 OUT_RING(clear->clear_color); in radeon_cp_dispatch_clear()
923 OUT_RING((x << 16) | y); in radeon_cp_dispatch_clear()
924 OUT_RING((w << 16) | h); in radeon_cp_dispatch_clear()
932 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
934 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_clear()
942 OUT_RING(dev_priv->back_pitch_offset); in radeon_cp_dispatch_clear()
943 OUT_RING(clear->clear_color); in radeon_cp_dispatch_clear()
945 OUT_RING((x << 16) | y); in radeon_cp_dispatch_clear()
946 OUT_RING((w << 16) | h); in radeon_cp_dispatch_clear()
1039 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
1042 OUT_RING(tileoffset * 8); in radeon_cp_dispatch_clear()
1044 OUT_RING(nrtilesx + 4); in radeon_cp_dispatch_clear()
1046 OUT_RING(clearmask); in radeon_cp_dispatch_clear()
1062 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
1069 OUT_RING(tileoffset * 16); in radeon_cp_dispatch_clear()
1071 OUT_RING(nrtilesx + 1); in radeon_cp_dispatch_clear()
1073 OUT_RING(clearmask); in radeon_cp_dispatch_clear()
1090 OUT_RING(CP_PACKET3 in radeon_cp_dispatch_clear()
1092 OUT_RING(tileoffset * 128); in radeon_cp_dispatch_clear()
1094 OUT_RING(nrtilesx + 4); in radeon_cp_dispatch_clear()
1096 OUT_RING(clearmask); in radeon_cp_dispatch_clear()
1113 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2)); in radeon_cp_dispatch_clear()
1114 OUT_RING(0x0); /* First tile */ in radeon_cp_dispatch_clear()
1115 OUT_RING(0x3cc0); in radeon_cp_dispatch_clear()
1116 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f); in radeon_cp_dispatch_clear()
1230 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); in radeon_cp_dispatch_clear()
1231 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | in radeon_cp_dispatch_clear()
1234 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); in radeon_cp_dispatch_clear()
1235 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); in radeon_cp_dispatch_clear()
1236 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1237 OUT_RING(0x3f800000); in radeon_cp_dispatch_clear()
1238 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); in radeon_cp_dispatch_clear()
1239 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); in radeon_cp_dispatch_clear()
1240 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1241 OUT_RING(0x3f800000); in radeon_cp_dispatch_clear()
1242 OUT_RING(depth_boxes[i].ui[CLEAR_X2]); in radeon_cp_dispatch_clear()
1243 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); in radeon_cp_dispatch_clear()
1244 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1245 OUT_RING(0x3f800000); in radeon_cp_dispatch_clear()
1279 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1)); in radeon_cp_dispatch_clear()
1280 OUT_RING(0x00000000); in radeon_cp_dispatch_clear()
1281 OUT_RING(rb3d_cntl); in radeon_cp_dispatch_clear()
1302 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); in radeon_cp_dispatch_clear()
1303 OUT_RING(RADEON_VTX_Z_PRESENT | in radeon_cp_dispatch_clear()
1305 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | in radeon_cp_dispatch_clear()
1311 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); in radeon_cp_dispatch_clear()
1312 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); in radeon_cp_dispatch_clear()
1313 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1314 OUT_RING(0x0); in radeon_cp_dispatch_clear()
1316 OUT_RING(depth_boxes[i].ui[CLEAR_X1]); in radeon_cp_dispatch_clear()
1317 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); in radeon_cp_dispatch_clear()
1318 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1319 OUT_RING(0x0); in radeon_cp_dispatch_clear()
1321 OUT_RING(depth_boxes[i].ui[CLEAR_X2]); in radeon_cp_dispatch_clear()
1322 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); in radeon_cp_dispatch_clear()
1323 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); in radeon_cp_dispatch_clear()
1324 OUT_RING(0x0); in radeon_cp_dispatch_clear()
1379 OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0)); in radeon_cp_dispatch_swap()
1380 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_swap()
1391 OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1)); in radeon_cp_dispatch_swap()
1393 OUT_RING(dev_priv->back_pitch_offset); in radeon_cp_dispatch_swap()
1394 OUT_RING(dev_priv->front_pitch_offset); in radeon_cp_dispatch_swap()
1396 OUT_RING(dev_priv->front_pitch_offset); in radeon_cp_dispatch_swap()
1397 OUT_RING(dev_priv->back_pitch_offset); in radeon_cp_dispatch_swap()
1400 OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2)); in radeon_cp_dispatch_swap()
1401 OUT_RING((x << 16) | y); in radeon_cp_dispatch_swap()
1402 OUT_RING((x << 16) | y); in radeon_cp_dispatch_swap()
1403 OUT_RING((w << 16) | h); in radeon_cp_dispatch_swap()
1534 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3)); in radeon_cp_dispatch_vertex()
1535 OUT_RING(offset); in radeon_cp_dispatch_vertex()
1536 OUT_RING(numverts); in radeon_cp_dispatch_vertex()
1537 OUT_RING(prim->vc_format); in radeon_cp_dispatch_vertex()
1538 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST | in radeon_cp_dispatch_vertex()
1593 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1)); in radeon_cp_dispatch_indirect()
1594 OUT_RING(offset); in radeon_cp_dispatch_indirect()
1595 OUT_RING(dwords); in radeon_cp_dispatch_indirect()
1865 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5)); in radeon_cp_dispatch_texture()
1866 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | in radeon_cp_dispatch_texture()
1874 OUT_RING((spitch << 22) | (offset >> 10)); in radeon_cp_dispatch_texture()
1875 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10))); in radeon_cp_dispatch_texture()
1876 OUT_RING(0); in radeon_cp_dispatch_texture()
1877 OUT_RING((image->x << 16) | (image->y % 2048)); in radeon_cp_dispatch_texture()
1878 OUT_RING((image->width << 16) | height); in radeon_cp_dispatch_texture()
1913 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0)); in radeon_cp_dispatch_stipple()
1914 OUT_RING(0x00000000); in radeon_cp_dispatch_stipple()
1916 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31)); in radeon_cp_dispatch_stipple()
1918 OUT_RING(stipple[i]); in radeon_cp_dispatch_stipple()
2158 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0)); in radeon_do_init_pageflip()
2159 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) | in radeon_do_init_pageflip()
2161 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0)); in radeon_do_init_pageflip()
2162 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) | in radeon_do_init_pageflip()
2620 OUT_RING(CP_PACKET0(reg, (sz - 1))); in radeon_emit_packets()
2639 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); in radeon_emit_scalars()
2640 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); in radeon_emit_scalars()
2641 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); in radeon_emit_scalars()
2661 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); in radeon_emit_scalars2()
2662 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); in radeon_emit_scalars2()
2663 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); in radeon_emit_scalars2()
2682 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); in radeon_emit_vectors()
2683 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); in radeon_emit_vectors()
2684 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); in radeon_emit_vectors()
2708 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); in radeon_emit_veclinear()
2709 OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); in radeon_emit_veclinear()
2710 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); in radeon_emit_veclinear()