264 static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)  in dib7000p_set_bandwidth()  argument
269 	state->current_bandwidth = bw;  in dib7000p_set_bandwidth()
273 		timf = state->cfg.bw->timf;  in dib7000p_set_bandwidth()
279 	timf = timf * (bw / 50) / 160;  in dib7000p_set_bandwidth()
315 	struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];  in dib7000p_reset_pll()  local
319 	clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |  in dib7000p_reset_pll()
320 		(bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) |  in dib7000p_reset_pll()
321 		(bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);  in dib7000p_reset_pll()
326 …dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw-…  in dib7000p_reset_pll()
327 	clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);  in dib7000p_reset_pll()
330 	dib7000p_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));  in dib7000p_reset_pll()
331 	dib7000p_write_word(state, 19, (u16) ( (bw->internal*1000       ) & 0xffff));  in dib7000p_reset_pll()
332 	dib7000p_write_word(state, 21, (u16) ( (bw->ifreq          >> 16) & 0xffff));  in dib7000p_reset_pll()
333 	dib7000p_write_word(state, 22, (u16) ( (bw->ifreq               ) & 0xffff));  in dib7000p_reset_pll()
335 	dib7000p_write_word(state, 72, bw->sad_cfg);  in dib7000p_reset_pll()
700 	dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->cfg.bw->timf);  in dib7000p_update_timf()
832 	value = 30 * state->cfg.bw->internal * factor;  in dib7000p_autosearch_start()
835 	value = 100 * state->cfg.bw->internal * factor;  in dib7000p_autosearch_start()
838 	value = 500 * state->cfg.bw->internal * factor;  in dib7000p_autosearch_start()
864 static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)  in dib7000p_spur_protect()  argument
885 	u32 xtal = state->cfg.bw->xtal_hz / 1000;  in dib7000p_spur_protect()
889 	int bw_khz = bw;  in dib7000p_spur_protect()