Lines Matching refs:uint
84 static uint first_id_byte = CONFIG_NANDSIM_FIRST_ID_BYTE;
85 static uint second_id_byte = CONFIG_NANDSIM_SECOND_ID_BYTE;
86 static uint third_id_byte = CONFIG_NANDSIM_THIRD_ID_BYTE;
87 static uint fourth_id_byte = CONFIG_NANDSIM_FOURTH_ID_BYTE;
88 static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY;
89 static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY;
90 static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY;
91 static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE;
92 static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE;
93 static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH;
94 static uint do_delays = CONFIG_NANDSIM_DO_DELAYS;
95 static uint log = CONFIG_NANDSIM_LOG;
96 static uint dbg = CONFIG_NANDSIM_DBG;
108 module_param(first_id_byte, uint, 0400);
109 module_param(second_id_byte, uint, 0400);
110 module_param(third_id_byte, uint, 0400);
111 module_param(fourth_id_byte, uint, 0400);
112 module_param(access_delay, uint, 0400);
113 module_param(programm_delay, uint, 0400);
114 module_param(erase_delay, uint, 0400);
115 module_param(output_cycle, uint, 0400);
116 module_param(input_cycle, uint, 0400);
117 module_param(bus_width, uint, 0400);
118 module_param(do_delays, uint, 0400);
119 module_param(log, uint, 0400);
120 module_param(dbg, uint, 0400);
125 module_param(bitflips, uint, 0400);
127 module_param(rptwear, uint, 0400);
128 module_param(overridesize, uint, 0400);
293 uint busw; /* flash chip bus width (8 or 16) */
317 uint pgsz; /* NAND flash page size, bytes */
318 uint oobsz; /* page OOB area size, bytes */
320 uint pgszoob; /* page size including OOB , bytes*/
321 uint secszoob; /* sector size including OOB, bytes */
322 uint pgnum; /* total number of pages */
323 uint pgsec; /* number of pages per sector */
324 uint secshift; /* bits number in sector size */
325 uint pgshift; /* bits number in page size */
326 uint oobshift; /* bits number in OOB size */
327 uint pgaddrbytes; /* bytes per page address */
328 uint secaddrbytes; /* bytes per sector address */
329 uint idbytes; /* the number ID bytes that this chip outputs */
336 uint row; /* the page number */
337 uint column; /* the offset within page */
338 uint count; /* internal counter */
339 uint num; /* number of bytes which must be processed */
340 uint off; /* fixed page offset */
1127 uint byte = (uint)bt; in accept_addr_byte()
1879 NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb); in ns_nand_read_byte()
1883 NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb); in ns_nand_read_byte()
1888 "return %#x\n", get_state_name(ns->state), (uint)outb); in ns_nand_read_byte()
1900 NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb); in ns_nand_read_byte()
1972 NS_ERR("write_byte: unknown command %#x\n", (uint)byte); in ns_nand_write_byte()
1997 "ignore previous states\n", (uint)byte, get_state_name(ns->nxstate)); in ns_nand_write_byte()
2043 "switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate)); in ns_nand_write_byte()
2060 (uint)byte, ns->regs.count, ns->regs.num); in ns_nand_write_byte()
2075 "switch to %s\n", (uint)byte, in ns_nand_write_byte()