Lines Matching refs:lp
146 struct at91_private *lp = netdev_priv(dev); in update_linkspeed() local
150 if (!mii_link_ok(&lp->mii)) { /* no link */ in update_linkspeed()
158 read_phy(lp->phy_address, MII_BMSR, &bmsr); in update_linkspeed()
159 read_phy(lp->phy_address, MII_BMCR, &bmcr); in update_linkspeed()
164 read_phy(lp->phy_address, MII_LPA, &lpa); in update_linkspeed()
199 struct at91_private *lp = netdev_priv(dev); in at91ether_phy_interrupt() local
208 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { in at91ether_phy_interrupt()
209 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ in at91ether_phy_interrupt()
213 else if (lp->phy_type == MII_LXT971A_ID) { in at91ether_phy_interrupt()
214 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ in at91ether_phy_interrupt()
218 else if (lp->phy_type == MII_BCM5221_ID) { in at91ether_phy_interrupt()
219 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */ in at91ether_phy_interrupt()
223 else if (lp->phy_type == MII_KS8721_ID) { in at91ether_phy_interrupt()
224 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */ in at91ether_phy_interrupt()
228 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */ in at91ether_phy_interrupt()
229 read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy); in at91ether_phy_interrupt()
233 else if (lp->phy_type == MII_DP83848_ID) { in at91ether_phy_interrupt()
234 read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */ in at91ether_phy_interrupt()
252 struct at91_private *lp = netdev_priv(dev); in enable_phyirq() local
256 irq_number = lp->board_data.phy_irq_pin; in enable_phyirq()
262 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); in enable_phyirq()
272 spin_lock_irq(&lp->lock); in enable_phyirq()
275 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ in enable_phyirq()
276 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); in enable_phyirq()
278 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); in enable_phyirq()
280 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ in enable_phyirq()
281 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); in enable_phyirq()
283 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); in enable_phyirq()
285 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ in enable_phyirq()
287 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); in enable_phyirq()
289 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ in enable_phyirq()
291 write_phy(lp->phy_address, MII_TPISTATUS, dsintr); in enable_phyirq()
293 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ in enable_phyirq()
294 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); in enable_phyirq()
296 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); in enable_phyirq()
298 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ in enable_phyirq()
299 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); in enable_phyirq()
301 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); in enable_phyirq()
302 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); in enable_phyirq()
304 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); in enable_phyirq()
308 spin_unlock_irq(&lp->lock); in enable_phyirq()
316 struct at91_private *lp = netdev_priv(dev); in disable_phyirq() local
320 irq_number = lp->board_data.phy_irq_pin; in disable_phyirq()
322 del_timer_sync(&lp->check_timer); in disable_phyirq()
326 spin_lock_irq(&lp->lock); in disable_phyirq()
329 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ in disable_phyirq()
330 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); in disable_phyirq()
332 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); in disable_phyirq()
334 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ in disable_phyirq()
335 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); in disable_phyirq()
337 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); in disable_phyirq()
339 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ in disable_phyirq()
340 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); in disable_phyirq()
342 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); in disable_phyirq()
344 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ in disable_phyirq()
345 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); in disable_phyirq()
347 write_phy(lp->phy_address, MII_TPISTATUS, dsintr); in disable_phyirq()
349 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ in disable_phyirq()
350 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); in disable_phyirq()
352 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); in disable_phyirq()
354 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ in disable_phyirq()
355 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); in disable_phyirq()
357 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); in disable_phyirq()
358 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); in disable_phyirq()
360 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); in disable_phyirq()
364 spin_unlock_irq(&lp->lock); in disable_phyirq()
375 struct at91_private *lp = netdev_priv(dev);
378 spin_lock_irq(&lp->lock);
382 write_phy(lp->phy_address, MII_BMCR, BMCR_RESET);
386 read_phy(lp->phy_address, MII_BMCR, &bmcr);
390 spin_unlock_irq(&lp->lock);
397 struct at91_private *lp = netdev_priv(dev); in at91ether_check_link() local
403 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); in at91ether_check_link()
624 struct at91_private *lp = netdev_priv(dev); in at91ether_get_settings() local
627 spin_lock_irq(&lp->lock); in at91ether_get_settings()
630 ret = mii_ethtool_gset(&lp->mii, cmd); in at91ether_get_settings()
633 spin_unlock_irq(&lp->lock); in at91ether_get_settings()
635 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */ in at91ether_get_settings()
645 struct at91_private *lp = netdev_priv(dev); in at91ether_set_settings() local
648 spin_lock_irq(&lp->lock); in at91ether_set_settings()
651 ret = mii_ethtool_sset(&lp->mii, cmd); in at91ether_set_settings()
654 spin_unlock_irq(&lp->lock); in at91ether_set_settings()
661 struct at91_private *lp = netdev_priv(dev); in at91ether_nwayreset() local
664 spin_lock_irq(&lp->lock); in at91ether_nwayreset()
667 ret = mii_nway_restart(&lp->mii); in at91ether_nwayreset()
670 spin_unlock_irq(&lp->lock); in at91ether_nwayreset()
692 struct at91_private *lp = netdev_priv(dev); in at91ether_ioctl() local
698 spin_lock_irq(&lp->lock); in at91ether_ioctl()
700 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL); in at91ether_ioctl()
702 spin_unlock_irq(&lp->lock); in at91ether_ioctl()
714 struct at91_private *lp = netdev_priv(dev); in at91ether_start() local
719 dlist = lp->dlist; in at91ether_start()
720 dlist_phys = lp->dlist_phys; in at91ether_start()
731 lp->rxBuffIndex = 0; in at91ether_start()
746 struct at91_private *lp = netdev_priv(dev); in at91ether_open() local
752 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */ in at91ether_open()
770 spin_lock_irq(&lp->lock); in at91ether_open()
774 spin_unlock_irq(&lp->lock); in at91ether_open()
786 struct at91_private *lp = netdev_priv(dev); in at91ether_close() local
803 clk_disable(lp->ether_clk); /* Disable Peripheral clock */ in at91ether_close()
813 struct at91_private *lp = netdev_priv(dev); in at91ether_tx() local
819 lp->skb = skb; in at91ether_tx()
820 lp->skb_length = skb->len; in at91ether_tx()
821 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); in at91ether_tx()
825 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr); in at91ether_tx()
880 struct at91_private *lp = netdev_priv(dev); in at91ether_rx() local
886 dlist = lp->dlist; in at91ether_rx()
887 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) { in at91ether_rx()
888 p_recv = dlist->recv_buf[lp->rxBuffIndex]; in at91ether_rx()
889 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */ in at91ether_rx()
904 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST) in at91ether_rx()
907 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */ in at91ether_rx()
908 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */ in at91ether_rx()
909 lp->rxBuffIndex = 0; in at91ether_rx()
911 lp->rxBuffIndex++; in at91ether_rx()
921 struct at91_private *lp = netdev_priv(dev); in at91ether_interrupt() local
936 if (lp->skb) { in at91ether_interrupt()
937 dev_kfree_skb_irq(lp->skb); in at91ether_interrupt()
938 lp->skb = NULL; in at91ether_interrupt()
939 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE); in at91ether_interrupt()
976 struct at91_private *lp; in at91ether_setup() local
994 lp = netdev_priv(dev); in at91ether_setup()
995 …lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma… in at91ether_setup()
996 if (lp->dlist == NULL) { in at91ether_setup()
1001 lp->board_data = *board_data; in at91ether_setup()
1002 lp->ether_clk = ether_clk; in at91ether_setup()
1005 spin_lock_init(&lp->lock); in at91ether_setup()
1027 if (lp->board_data.is_rmii) in at91ether_setup()
1033 spin_lock_irq(&lp->lock); in at91ether_setup()
1035 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { in at91ether_setup()
1038 lp->phy_media = PORT_FIBRE; in at91ether_setup()
1046 spin_unlock_irq(&lp->lock); in at91ether_setup()
1048 lp->mii.dev = dev; /* Support for ethtool */ in at91ether_setup()
1049 lp->mii.mdio_read = mdio_read; in at91ether_setup()
1050 lp->mii.mdio_write = mdio_write; in at91ether_setup()
1051 lp->mii.phy_id = phy_address; in at91ether_setup()
1052 lp->mii.phy_id_mask = 0x1f; in at91ether_setup()
1053 lp->mii.reg_num_mask = 0x1f; in at91ether_setup()
1055 lp->phy_type = phy_type; /* Type of PHY connected */ in at91ether_setup()
1056 lp->phy_address = phy_address; /* MDI address of PHY */ in at91ether_setup()
1063 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); in at91ether_setup()
1068 spin_lock_irq(&lp->lock); in at91ether_setup()
1072 spin_unlock_irq(&lp->lock); in at91ether_setup()
1076 if (!lp->board_data.phy_irq_pin) { in at91ether_setup()
1077 init_timer(&lp->check_timer); in at91ether_setup()
1078 lp->check_timer.data = (unsigned long)dev; in at91ether_setup()
1079 lp->check_timer.function = at91ether_check_link; in at91ether_setup()
1080 } else if (lp->board_data.phy_irq_pin >= 32) in at91ether_setup()
1081 gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy"); in at91ether_setup()
1089 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) in at91ether_setup()
1090 …printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)"… in at91ether_setup()
1166 struct at91_private *lp = netdev_priv(dev); in at91ether_remove() local
1168 if (lp->board_data.phy_irq_pin >= 32) in at91ether_remove()
1169 gpio_free(lp->board_data.phy_irq_pin); in at91ether_remove()
1173 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); in at91ether_remove()
1174 clk_put(lp->ether_clk); in at91ether_remove()
1186 struct at91_private *lp = netdev_priv(net_dev); in at91ether_suspend() local
1187 int phy_irq = lp->board_data.phy_irq_pin; in at91ether_suspend()
1196 clk_disable(lp->ether_clk); in at91ether_suspend()
1204 struct at91_private *lp = netdev_priv(net_dev); in at91ether_resume() local
1205 int phy_irq = lp->board_data.phy_irq_pin; in at91ether_resume()
1208 clk_enable(lp->ether_clk); in at91ether_resume()