2580 	int reg_offset;  in bnx2x_attn_int_deasserted0()  local
2583 	reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :  in bnx2x_attn_int_deasserted0()
2588 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted0()
2590 		REG_WR(bp, reg_offset, val);  in bnx2x_attn_int_deasserted0()
2629 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted0()
2631 		REG_WR(bp, reg_offset, val);  in bnx2x_attn_int_deasserted0()
2655 		int reg_offset;  in bnx2x_attn_int_deasserted1()  local
2657 		reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :  in bnx2x_attn_int_deasserted1()
2660 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted1()
2662 		REG_WR(bp, reg_offset, val);  in bnx2x_attn_int_deasserted1()
2695 		int reg_offset;  in bnx2x_attn_int_deasserted2()  local
2697 		reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :  in bnx2x_attn_int_deasserted2()
2700 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted2()
2702 		REG_WR(bp, reg_offset, val);  in bnx2x_attn_int_deasserted2()
4115 	int index, val, reg_offset;  in bnx2x_init_def_sb()  local
4125 	reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :  in bnx2x_init_def_sb()
4130 						     reg_offset + 0x10*index);  in bnx2x_init_def_sb()
4132 					       reg_offset + 0x4 + 0x10*index);  in bnx2x_init_def_sb()
4134 					       reg_offset + 0x8 + 0x10*index);  in bnx2x_init_def_sb()
4136 					       reg_offset + 0xc + 0x10*index);  in bnx2x_init_def_sb()
4139 	reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :  in bnx2x_init_def_sb()
4142 	REG_WR(bp, reg_offset, U64_LO(section));  in bnx2x_init_def_sb()
4143 	REG_WR(bp, reg_offset + 4, U64_HI(section));  in bnx2x_init_def_sb()
4145 	reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);  in bnx2x_init_def_sb()
4147 	val = REG_RD(bp, reg_offset);  in bnx2x_init_def_sb()
4149 	REG_WR(bp, reg_offset, val);  in bnx2x_init_def_sb()