Lines Matching refs:mii_rw
1060 static int mii_rw(struct net_device *dev, int addr, int miireg, int value) in mii_rw() function
1111 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { in phy_reset()
1121 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
1137 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in phy_init()
1139 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { in phy_init()
1147 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { in phy_init()
1151 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { in phy_init()
1155 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { in phy_init()
1159 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { in phy_init()
1163 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { in phy_init()
1167 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { in phy_init()
1171 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { in phy_init()
1189 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in phy_init()
1191 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) { in phy_init()
1195 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) { in phy_init()
1199 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); in phy_init()
1202 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) { in phy_init()
1207 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { in phy_init()
1221 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in phy_init()
1223 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { in phy_init()
1232 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in phy_init()
1234 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { in phy_init()
1243 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in phy_init()
1246 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in phy_init()
1253 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { in phy_init()
1261 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1269 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
1285 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); in phy_init()
1288 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { in phy_init()
1292 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in phy_init()
1294 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { in phy_init()
1300 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); in phy_init()
1302 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { in phy_init()
1308 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) { in phy_init()
1312 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) { in phy_init()
1316 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); in phy_init()
1317 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { in phy_init()
1321 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); in phy_init()
1324 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { in phy_init()
1328 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) { in phy_init()
1332 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { in phy_init()
1336 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); in phy_init()
1339 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { in phy_init()
1343 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); in phy_init()
1344 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { in phy_init()
1348 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) { in phy_init()
1352 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) { in phy_init()
1356 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); in phy_init()
1357 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { in phy_init()
1361 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); in phy_init()
1364 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { in phy_init()
1368 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) { in phy_init()
1372 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) { in phy_init()
1381 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { in phy_init()
1385 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { in phy_init()
1389 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { in phy_init()
1393 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { in phy_init()
1397 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { in phy_init()
1401 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { in phy_init()
1405 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { in phy_init()
1419 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in phy_init()
1421 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { in phy_init()
1427 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { in phy_init()
1431 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); in phy_init()
1434 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) { in phy_init()
1438 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { in phy_init()
1447 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); in phy_init()
1450 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1452 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
3125 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3126 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3166 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_update_linkspeed()
3167 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); in nv_update_linkspeed()
3173 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_update_linkspeed()
3174 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); in nv_update_linkspeed()
3247 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ in nv_update_linkspeed()
4219 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_get_settings()
4229 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_get_settings()
4315 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_settings()
4329 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_settings()
4332 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_settings()
4336 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_settings()
4341 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_settings()
4352 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_settings()
4359 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_settings()
4378 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_settings()
4382 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_settings()
4384 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_settings()
4387 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_settings()
4400 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_settings()
4461 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_nway_reset()
4471 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_nway_reset()
4669 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_pauseparam()
4675 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_pauseparam()
4679 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_pauseparam()
4681 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_pauseparam()
4795 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
4796 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5214 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_open()
5215 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); in nv_open()
5412 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_close()
5413 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); in nv_close()
5797 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); in nv_probe()
5802 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); in nv_probe()
5820 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; in nv_probe()
5835 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_probe()
5908 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); in nv_restore_phy()
5909 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); in nv_restore_phy()
5912 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); in nv_restore_phy()
5913 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); in nv_restore_phy()
5916 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_restore_phy()
5918 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); in nv_restore_phy()