Lines Matching refs:writedatareg
164 #define writedatareg(val) {outw(val,PORT+L_DATAREG);inw(PORT+L_DATAREG);}
166 #define writedatareg(val) { writereg(val,CSR0); }
171 #define writedatareg(val) { writereg(val,CSR0); } macro
722 writedatareg(CSR0_STOP); in ni65_stop_start()
760 writedatareg(CSR0_STRT | csr0); in ni65_stop_start()
769 writedatareg(CSR0_TDMD | CSR0_INEA | csr0); in ni65_stop_start()
782 writedatareg(CSR0_STRT | csr0); in ni65_stop_start()
857 writedatareg(CSR0_CLRALL | CSR0_INEA | CSR0_STRT); in ni65_lance_reinit()
885 writedatareg( (csr0 & CSR0_CLRALL) ); /* ack interrupts, disable int. */ in ni65_interrupt()
887 writedatareg( (csr0 & CSR0_CLRALL) | CSR0_INEA ); /* ack interrupts, interrupts enabled */ in ni65_interrupt()
971 writedatareg(CSR0_INEA); in ni65_interrupt()
1200 writedatareg(CSR0_TDMD | CSR0_INEA); /* enable xmit & interrupt */ in ni65_send_packet()