Lines Matching refs:lp
59 #define SMC_IO_SHIFT (lp->io_shift)
416 #define SMC_IO_SHIFT (lp->io_shift)
503 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
505 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, in smc_pxa_dma_insl() argument
508 u_long physaddr = lp->physaddr; in smc_pxa_dma_insl()
525 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); in smc_pxa_dma_insl()
535 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); in smc_pxa_dma_insl()
542 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
544 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, in smc_pxa_dma_insw() argument
547 u_long physaddr = lp->physaddr; in smc_pxa_dma_insw()
564 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); in smc_pxa_dma_insw()
574 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); in smc_pxa_dma_insw()
680 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) argument
699 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) argument
718 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) argument
735 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) argument
740 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0) argument
745 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) argument
771 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) argument
783 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) argument
788 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) argument
789 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) argument
790 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) argument
795 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1) argument
800 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) argument
813 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) argument
827 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2) argument
832 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2) argument
838 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) argument
843 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) argument
846 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) argument
850 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) argument
858 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) argument
863 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2) argument
868 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2) argument
881 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) argument
882 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) argument
883 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) argument
884 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) argument
889 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3) argument
900 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3) argument
906 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) argument
913 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7) argument
1037 #define SMC_REG(lp, reg, bank) \ argument
1039 int __b = SMC_CURRENT_BANK(lp); \
1048 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) argument
1060 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp) argument
1062 #define SMC_GET_PN(lp) \ argument
1063 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1064 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1066 #define SMC_SET_PN(lp, x) \ argument
1068 if (SMC_MUST_ALIGN_WRITE(lp)) \
1069 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1070 else if (SMC_8BIT(lp)) \
1071 SMC_outb(x, ioaddr, PN_REG(lp)); \
1073 SMC_outw(x, ioaddr, PN_REG(lp)); \
1076 #define SMC_GET_AR(lp) \ argument
1077 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1078 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1080 #define SMC_GET_TXFIFO(lp) \ argument
1081 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1082 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1084 #define SMC_GET_RXFIFO(lp) \ argument
1085 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1086 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1088 #define SMC_GET_INT(lp) \ argument
1089 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1090 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1092 #define SMC_ACK_INT(lp, x) \ argument
1094 if (SMC_8BIT(lp)) \
1095 SMC_outb(x, ioaddr, INT_REG(lp)); \
1100 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1101 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1106 #define SMC_GET_INT_MASK(lp) \ argument
1107 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1108 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1110 #define SMC_SET_INT_MASK(lp, x) \ argument
1112 if (SMC_8BIT(lp)) \
1113 SMC_outb(x, ioaddr, IM_REG(lp)); \
1115 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1118 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) argument
1120 #define SMC_SELECT_BANK(lp, x) \ argument
1122 if (SMC_MUST_ALIGN_WRITE(lp)) \
1128 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp)) argument
1130 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp)) argument
1132 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp)) argument
1134 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp)) argument
1136 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp)) argument
1138 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp)) argument
1140 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp)) argument
1142 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp)) argument
1144 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp)) argument
1146 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp)) argument
1148 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp)) argument
1150 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp)) argument
1152 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp)) argument
1154 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp)) argument
1156 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp)) argument
1158 #define SMC_SET_PTR(lp, x) \ argument
1160 if (SMC_MUST_ALIGN_WRITE(lp)) \
1161 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1163 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1166 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp)) argument
1168 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp)) argument
1170 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp)) argument
1172 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp)) argument
1174 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp)) argument
1176 #define SMC_SET_RPC(lp, x) \ argument
1178 if (SMC_MUST_ALIGN_WRITE(lp)) \
1179 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1181 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1184 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp)) argument
1186 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp)) argument
1189 #define SMC_GET_MAC_ADDR(lp, addr) \ argument
1192 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1194 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1196 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1201 #define SMC_SET_MAC_ADDR(lp, addr) \ argument
1203 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1204 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1205 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1208 #define SMC_SET_MCAST(lp, x) \ argument
1211 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1212 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1213 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1214 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1217 #define SMC_PUT_PKT_HDR(lp, status, length) \ argument
1219 if (SMC_32BIT(lp)) \
1221 DATA_REG(lp)); \
1223 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1224 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1228 #define SMC_GET_PKT_HDR(lp, status, length) \ argument
1230 if (SMC_32BIT(lp)) { \
1231 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1235 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1236 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1240 #define SMC_PUSH_DATA(lp, p, l) \ argument
1242 if (SMC_32BIT(lp)) { \
1249 DATA_REG(lp)); \
1252 if (SMC_CAN_USE_DATACS && lp->datacs) \
1253 __ioaddr = lp->datacs; \
1254 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1258 DATA_REG(lp)); \
1260 } else if (SMC_16BIT(lp)) \
1261 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1262 else if (SMC_8BIT(lp)) \
1263 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1266 #define SMC_PULL_DATA(lp, p, l) \ argument
1268 if (SMC_32BIT(lp)) { \
1288 SMC_SET_PTR(lp, \
1291 if (SMC_CAN_USE_DATACS && lp->datacs) \
1292 __ioaddr = lp->datacs; \
1294 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1295 } else if (SMC_16BIT(lp)) \
1296 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1297 else if (SMC_8BIT(lp)) \
1298 SMC_insb(ioaddr, DATA_REG(lp), p, l); \