404 #define tc_readl(addr)	ioread32(addr)  macro
599 	while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {  in tc_mdio_read()
604 	return tc_readl(&tr->MD_Data) & 0xffff;  in tc_mdio_read()
617 	while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {  in tc_mdio_write()
639 		reg = tc_readl(&tr->MAC_Ctl);  in tc_handle_link_change()
663 			tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,  in tc_handle_link_change()
849 	while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)  in tc35815_init_dev_addr()
854 		while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)  in tc35815_init_dev_addr()
856 		data = tc_readl(&tr->PROM_Data);  in tc35815_init_dev_addr()
1351 	tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);  in tc35815_schedule_restart()
1361 	       dev->name, tc_readl(&tr->Tx_Stat));  in tc35815_tx_timeout()
1551 		tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);  in tc35815_do_interrupt()
1560 		tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);  in tc35815_do_interrupt()
1607 	u32 dmactl = tc_readl(&tr->DMA_Ctl);  in tc35815_interrupt()
1619 		(void)tc_readl(&tr->Int_Src);	/* flush */  in tc35815_interrupt()
1628 	status = tc_readl(&tr->Int_Src);  in tc35815_interrupt()
1631 	(void)tc_readl(&tr->Int_Src);	/* flush */  in tc35815_interrupt()
1884 		u32 en, en_old = tc_readl(&tr->Int_En);  in tc35815_rx()
1907 	status = tc_readl(&tr->Int_Src);  in tc35815_poll()
1917 		status = tc_readl(&tr->Int_Src);  in tc35815_poll()
1924 		tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);  in tc35815_poll()
2143 		dev->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);  in tc35815_get_stats()
2157 	saved_addr = tc_readl(&tr->CAM_Adr);  in tc35815_set_cam_entry()
2165 		cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;  in tc35815_set_cam_entry()
2179 		cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;  in tc35815_set_cam_entry()
2344 	while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {  in tc35815_chip_reset()
2366 	(void)tc_readl(&tr->Miss_Cnt);	/* Read to clear */  in tc35815_chip_reset()