Lines Matching refs:tr32
483 #define tr32(reg) tp->read32(tp, reg) macro
529 *val = tr32(TG3PCI_MEM_WIN_DATA); in tg3_read_mem()
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); in tg3_switch_clocks()
757 frame_val = tr32(MAC_MI_COM); in tg3_readphy()
761 frame_val = tr32(MAC_MI_COM); in tg3_readphy()
809 frame_val = tr32(MAC_MI_COM); in tg3_writephy()
812 frame_val = tr32(MAC_MI_COM); in tg3_writephy()
919 val = tr32(MAC_PHYCFG1); in tg3_mdio_config_5785()
936 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC | in tg3_mdio_config_5785()
946 val = tr32(MAC_EXT_RGMII_MODE); in tg3_mdio_config_5785()
1093 val = tr32(GRC_RX_CPU_EVENT); in tg3_generate_fw_event()
1123 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) in tg3_wait_for_event_ack()
1787 val = tr32(GRC_MISC_CFG); in tg3_phy_reset()
1813 cpmuctrl = tr32(TG3_CPMU_CTRL); in tg3_phy_reset()
1836 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); in tg3_phy_reset()
2062 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); in tg3_power_down_phy()
2063 u32 serdes_cfg = tr32(MAC_SERDES_CFG); in tg3_power_down_phy()
2075 val = tr32(GRC_MISC_CFG); in tg3_power_down_phy()
2101 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); in tg3_power_down_phy()
2194 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); in tg3_set_power_state()
2270 val = tr32(GRC_VCPU_EXT_CTRL); in tg3_set_power_state()
2407 u32 val = tr32(0x7d00); in tg3_set_power_state()
3075 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { in tg3_fiber_aneg_smachine()
3076 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); in tg3_fiber_aneg_smachine()
3356 u32 mac_status = tr32(MAC_STATUS); in tg3_init_bcm8002()
3421 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_setup_fiber_hw_autoneg()
3426 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; in tg3_setup_fiber_hw_autoneg()
3429 sg_dig_ctrl = tr32(SG_DIG_CTRL); in tg3_setup_fiber_hw_autoneg()
3482 sg_dig_status = tr32(SG_DIG_STATUS); in tg3_setup_fiber_hw_autoneg()
3483 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_hw_autoneg()
3524 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_hw_autoneg()
3580 if ((tr32(MAC_STATUS) & in tg3_setup_fiber_by_hand()
3586 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_by_hand()
3624 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
3652 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
3667 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | in tg3_setup_fiber_phy()
3673 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
3747 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
3821 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
3959 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; in tg3_setup_phy()
3967 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; in tg3_setup_phy()
3994 u32 val = tr32(PCIE_PWR_MGMT_THRESH); in tg3_setup_phy()
4567 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_interrupt()
4616 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_interrupt_tagged()
4658 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_test_isr()
4752 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS)); in tg3_dump_short_state()
4754 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS)); in tg3_dump_short_state()
5550 val = tr32(ofs); in tg3_stop_block()
5556 val = tr32(ofs); in tg3_stop_block()
5606 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) in tg3_abort_hw()
5612 tp->dev->name, tr32(MAC_TX_MODE)); in tg3_abort_hw()
5643 if (tr32(NVRAM_SWARB) & SWARB_GNT1) in tg3_nvram_lock()
5673 u32 nvaccess = tr32(NVRAM_ACCESS); in tg3_enable_nvram_access()
5684 u32 nvaccess = tr32(NVRAM_ACCESS); in tg3_disable_nvram_access()
5862 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) in tg3_poll_fw()
5957 val = tr32(MSGINT_MODE); in tg3_restore_pci_state()
6022 if (tr32(0x7e2c) == 0x60) { in tg3_chip_reset()
6032 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); in tg3_chip_reset()
6034 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); in tg3_chip_reset()
6107 val = tr32(MEMARB_MODE); in tg3_chip_reset()
6118 val = tr32(0xc4); in tg3_chip_reset()
6156 val = tr32(0x7c00); in tg3_chip_reset()
6232 u32 val = tr32(GRC_VCPU_EXT_CTRL); in tg3_halt_cpu()
6241 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) in tg3_halt_cpu()
6252 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) in tg3_halt_cpu()
6310 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); in tg3_load_firmware_cpu()
6359 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) in tg3_load_5701_a0_firmware_fix()
6369 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC), in tg3_load_5701_a0_firmware_fix()
6425 if (tr32(cpu_base + CPU_PC) == info.fw_base) in tg3_load_tso_firmware()
6435 tp->dev->name, tr32(cpu_base + CPU_PC), in tg3_load_tso_firmware()
6462 addr0_high = tr32(MAC_ADDR_0_HIGH); in tg3_set_mac_addr()
6463 addr0_low = tr32(MAC_ADDR_0_LOW); in tg3_set_mac_addr()
6464 addr1_high = tr32(MAC_ADDR_1_HIGH); in tg3_set_mac_addr()
6465 addr1_low = tr32(MAC_ADDR_1_LOW); in tg3_set_mac_addr()
6550 val = tr32(TG3_CPMU_CTRL); in tg3_reset_hw()
6554 val = tr32(TG3_CPMU_LSPD_10MB_CLK); in tg3_reset_hw()
6559 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); in tg3_reset_hw()
6564 val = tr32(TG3_CPMU_HST_ACC); in tg3_reset_hw()
6583 val = tr32(TG3PCI_PCISTATE); in tg3_reset_hw()
6592 val = tr32(TG3PCI_PCISTATE); in tg3_reset_hw()
6600 val = tr32(TG3PCI_MSI_DATA); in tg3_reset_hw()
6641 val = tr32(GRC_MISC_CFG); in tg3_reset_hw()
6691 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) in tg3_reset_hw()
6709 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); in tg3_reset_hw()
6864 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
6882 val = tr32(RCVLPC_STATS_ENABLE); in tg3_reset_hw()
6887 val = tr32(RCVLPC_STATS_ENABLE); in tg3_reset_hw()
6902 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) in tg3_reset_hw()
6985 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
7017 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
7107 val = tr32(MAC_SERDES_CFG); in tg3_reset_hw()
7131 tmp = tr32(SERDES_RX_CTRL); in tg3_reset_hw()
7237 do { u32 __val = tr32(REG); \
7306 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_timer()
7323 mac_stat = tr32(MAC_STATUS); in tg3_timer()
7335 u32 mac_stat = tr32(MAC_STATUS); in tg3_timer()
7452 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); in tg3_test_interrupt()
7621 msi_mode = tr32(MSGINT_MODE); in tg3_open()
7699 u32 val = tr32(PCIE_TRANSACTION_CFG); in tg3_open()
7736 tr32(MAC_MODE), tr32(MAC_STATUS));
7738 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7740 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7742 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7746 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7748 tr32(SNDDATAI_STATSCTRL));
7751 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7755 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7759 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7762 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7766 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7768 tr32(RCVLPC_STATSCTRL));
7772 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7776 tr32(RCVDCC_MODE));
7780 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7784 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7788 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7792 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7796 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7798 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7799 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7801 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7802 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7804 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7806 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7810 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7814 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7816 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7819 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7820 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7824 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7828 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7832 tr32(DMAC_MODE));
7836 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7838 tr32(GRC_LOCAL_CTRL));
7842 tr32(RCVDBDI_JUMBO_BD + 0x0),
7843 tr32(RCVDBDI_JUMBO_BD + 0x4),
7844 tr32(RCVDBDI_JUMBO_BD + 0x8),
7845 tr32(RCVDBDI_JUMBO_BD + 0xc));
7847 tr32(RCVDBDI_STD_BD + 0x0),
7848 tr32(RCVDBDI_STD_BD + 0x4),
7849 tr32(RCVDBDI_STD_BD + 0x8),
7850 tr32(RCVDBDI_STD_BD + 0xc));
7852 tr32(RCVDBDI_MINI_BD + 0x0),
7853 tr32(RCVDBDI_MINI_BD + 0x4),
7854 tr32(RCVDBDI_MINI_BD + 0x8),
7855 tr32(RCVDBDI_MINI_BD + 0xc));
8326 #define __GET_REG32(reg) (*(p)++ = tr32(reg)) in tg3_get_regs()
9361 save_val = tr32(offset); in tg3_test_registers()
9371 val = tr32(offset); in tg3_test_registers()
9383 val = tr32(offset); in tg3_test_registers()
9679 status = tr32(TG3_CPMU_MUTEX_GNT); in tg3_test_loopback()
9689 cpmuctrl = tr32(TG3_CPMU_CTRL); in tg3_test_loopback()
10031 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_nvram_info()
10084 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5752_nvram_info()
10145 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5755_nvram_info()
10201 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5787_nvram_info()
10239 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5761_nvram_info()
10279 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
10321 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_57780_nvram_info()
10425 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); in tg3_nvram_init()
10481 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | in tg3_nvram_read_using_eeprom()
10492 tmp = tr32(GRC_EEPROM_ADDR); in tg3_nvram_read_using_eeprom()
10501 *val = tr32(GRC_EEPROM_DATA); in tg3_nvram_read_using_eeprom()
10514 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { in tg3_nvram_exec_cmd()
10578 *val = swab32(tr32(NVRAM_RDDATA)); in tg3_nvram_read()
10622 val = tr32(GRC_EEPROM_ADDR); in tg3_nvram_write_block_using_eeprom()
10634 val = tr32(GRC_EEPROM_ADDR); in tg3_nvram_write_block_using_eeprom()
10823 grc_mode = tr32(GRC_MODE); in tg3_nvram_write_block()
10837 grc_mode = tr32(GRC_MODE); in tg3_nvram_write_block()
10933 val = tr32(MEMARB_MODE); in tg3_get_eeprom_hw_cfg()
10943 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { in tg3_get_eeprom_hw_cfg()
10947 val = tr32(VCPU_CFGSHDW); in tg3_get_eeprom_hw_cfg()
11132 val = tr32(OTP_STATUS); in tg3_issue_otp_command()
11159 thalf_otp = tr32(OTP_READ_DATA); in tg3_read_otp_phycfg()
11166 bhalf_otp = tr32(OTP_READ_DATA); in tg3_read_otp_phycfg()
12097 val = tr32(GRC_MODE); in tg3_get_invariants()
12135 grc_misc_cfg = tr32(GRC_MISC_CFG); in tg3_get_invariants()
12157 tp->mac_mode = tr32(MAC_MODE) | in tg3_get_invariants()
12240 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
12288 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_get_device_address()
12326 hi = tr32(MAC_ADDR_0_HIGH); in tg3_get_device_address()
12327 lo = tr32(MAC_ADDR_0_LOW); in tg3_get_device_address()
12556 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); in tg3_do_test_dma()
12558 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); in tg3_do_test_dma()
12601 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); in tg3_test_dma()
12851 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; in tg3_bus_string()
12856 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == in tg3_bus_string()
13181 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { in tg3_init_one()
13210 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || in tg3_init_one()
13211 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_init_one()