126 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_start_tx_dma()  argument
131 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_start_tx_dma()
134 	if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)  in ath5k_hw_start_tx_dma()
143 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_start_tx_dma()
165 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))  in ath5k_hw_start_tx_dma()
169 		AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);  in ath5k_hw_start_tx_dma()
186 int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_stop_tx_dma()  argument
192 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_stop_tx_dma()
195 	if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)  in ath5k_hw_stop_tx_dma()
204 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_stop_tx_dma()
225 		AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);  in ath5k_hw_stop_tx_dma()
230 				AR5K_QUEUE_STATUS(queue)) &  in ath5k_hw_stop_tx_dma()
266 					AR5K_QUEUE_STATUS(queue)) &  in ath5k_hw_stop_tx_dma()
298 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_get_txdp()  argument
303 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_get_txdp()
310 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_get_txdp()
322 		tx_reg = AR5K_QUEUE_TXDP(queue);  in ath5k_hw_get_txdp()
341 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)  in ath5k_hw_set_txdp()  argument
346 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_set_txdp()
353 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_set_txdp()
370 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))  in ath5k_hw_set_txdp()
373 		tx_reg = AR5K_QUEUE_TXDP(queue);  in ath5k_hw_set_txdp()