Lines Matching refs:of
11 * 1. Redistributions of source code must retain the above copyright
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23 * Alternatively, this software may be distributed under the terms of the
46 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
47 * a C header file for use in the kernel portion of the Aic7xxx driver.
56 * of debug code for them.
116 * Reads the actual state of the SCSI bus pins
175 * Contents of this register determine the Synchronous SCSI data transfer
176 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
193 * Contains the ID of the board and the current target on the
205 * The aic7890/91 allow an offset of up to 127 transfers in both wide
217 * upper byte of a 16bit wide asynchronouse data phase transfer.
232 * These registers count down the number of bytes transferred
297 * Contains one set of SCSI Interrupt codes
298 * These are most likely of interest to the sequencer
442 * to determine the address of the last byte transferred since HADDR
506 * perform the tasks of accessing a serial eeprom, testing termination
507 * strength, and performing cable detection. On the aic7860, most of
548 * Controls the reading and writing of an external serial 1-bit
557 * After successful arbitration for the memory port, the SEECS bit of
560 * lines respectively. The SEERDY bit of SEECTL is useful in that it
587 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
637 * Only the first bit of SEQADDR1 holds addressing information
821 * Overall host control of the device.
839 * This register contains the address of the byte about
858 * Gate one of the SCBs into the SCBARRAY window.
906 * beyond the bounds of its
937 * Reporting of catastrophic errors. You usually cannot recover from
1017 * incrementing of the address during download and upload operations
1041 * Number of queued SCBs
1050 * Queue of SCBs that have completed and await the host
1075 * Number of queued SCBs in the Out FIFO
1388 * on top of the BIOS values, so we re-use those for our per-target
1392 * bits of the target scratch space. This should work regardless of
1409 * Bit vector of targets that have ULTRA enabled as set by
1422 * Bit vector of targets that have disconnection disabled as set by
1444 * SCBID of the next SCB to be started by the controller.
1489 * target/channel/lun of a
1518 * head of list of SCBs awaiting
1526 * head of list of SCBs that are
1535 * head of list of SCBs that are
1543 * head of list of SCBs that have
1551 * Address of the hardware scb array in the host.
1558 * Base address of our shared data with the kernel driver in host
1579 * Kernel and sequencer offsets into the queue of
1611 * Snapshot of MSG_OUT taken after each message is sent.
1669 * The EISA configuraiton chip is mapped here. On Rev E. of the
1673 * Even on later chips, many of these locations are initialized by