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10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification, immediately at the beginning of the file.
13  * 2. The name of the author may not be used to endorse or promote products
16  * Where this Software is combined with software released under the terms of 
17  * the GNU General Public License ("GPL") and the terms of the GPL would require the 
18  * combined work to also be released under the terms of the GPL, the terms
19  * and conditions of this License will apply in addition to those of the
20  * GPL with the exception of any terms or conditions of this License that
40  * firmware for the aic7xxx family of SCSI host adapters as well as to generate
41  * a C header file for use in the kernel portion of the Aic7xxx driver.
98  * Reads the actual state of the SCSI bus pins
154  * Contents of this register determine the Synchronous SCSI data transfer
155  * rate and the maximum synchronous Req/Ack offset.  An offset of 0 in the
170  * Contains the ID of the board and the current target on the
180 	 * The aic7890/91 allow an offset of up to 127 transfers in both wide
191  * upper byte of a 16bit wide asynchronouse data phase transfer.
205  * These registers count down the number of bytes transferred
251  * Contains one set of SCSI Interrupt codes
252  * These are most likely of interest to the sequencer
392  * to determine the address of the last byte transferred since HADDR
430  * perform the tasks of accessing a serial eeprom, testing termination
431  * strength, and performing cable detection.  On the aic7860, most of
452  * register.  SELWIDE allows for the coexistence of 8bit and 16bit devices
499  * Only the first bit of SEQADDR1 holds addressing information
638  * Overall host control of the device.
654  * This register contains the address of the byte about
671  * Gate one of the four SCBs into the SCBARRAY window.
720 						 * beyond the bounds of its
730  * Reporting of catastrophic errors.  You usually cannot recover from
795  * incrementing of the address during download and upload operations
815  * Number of queued SCBs
835  * Queue of SCBs that have completed and await the host
859  * Number of queued SCBs in the Out FIFO
1114  * Controls the reading and writing of an external serial 1-bit
1123  * After successful arbitration for the memory port, the SEECS bit of 
1126  * lines respectively.  The SEERDY bit of SEECTL is useful in that it 
1154  * on top of the BIOS values, so we re-use those for our per-target
1158  * bits of the target scratch space.  This should work regardless of
1172 	 * Bit vector of targets that have ULTRA enabled.
1178 	 * Bit vector of targets that have disconnection disabled.
1215 	 * target/channel/lun of a
1221 	/* Working value of the number of SG segments left */
1225 	/* Working value of SG pointer */
1247 	 * head of list of SCBs awaiting
1254 	 * head of list of SCBs that are
1262 	 * head of list of SCBs that are
1269 	 * Address of the hardware scb array in the host.
1275 	 * Address of the 256 byte array storing the SCBID of outstanding
1282 	 * Address of the array of command descriptors used to store
1318 	 * Snapshot of MSG_OUT taken after each message is sent.
1325 	 * Number of times we have filled the CCSGRAM with prefetched
1334 	 * These are reserved registers in the card's scratch ram.  Some of
1399  * Number of command descriptors in the command descriptor array.