836 	u32 rx_desc = le32_to_cpu(mvi->rx[entry]);  in mvs_hba_cq_dump()  local
841 		   mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);  in mvs_hba_cq_dump()
846 	mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),  in mvs_hba_cq_dump()
1271 static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)  in mvs_slot_free()  argument
1273 	u32 slot_idx = rx_desc & RXQ_SLOT_MASK;  in mvs_slot_free()
1337 static int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)  in mvs_slot_complete()  argument
1339 	u32 slot_idx = rx_desc & RXQ_SLOT_MASK;  in mvs_slot_complete()
1363 		mvs_slot_free(mvi, rx_desc);  in mvs_slot_complete()
1380 	if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {  in mvs_slot_complete()
1388 		if (rx_desc & RXQ_GOOD) {  in mvs_slot_complete()
1393 		else if (rx_desc & RXQ_RSP) {  in mvs_slot_complete()
1430 		mvs_slot_free(mvi, rx_desc);  in mvs_slot_complete()
1444 	u32 rx_desc;  in mvs_release_task()  local
1451 		rx_desc = (u32) (slot - mvi->slot_info);  in mvs_release_task()
1452 		mvs_slot_complete(mvi, rx_desc, 1);  in mvs_release_task()
1481 	u32 rx_prod_idx, rx_desc;  in mvs_int_rx()  local
1510 		rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);  in mvs_int_rx()
1512 		if (likely(rx_desc & RXQ_DONE))  in mvs_int_rx()
1513 			mvs_slot_complete(mvi, rx_desc, 0);  in mvs_int_rx()
1514 		if (rx_desc & RXQ_ATTN) {  in mvs_int_rx()
1517 				rx_desc);  in mvs_int_rx()
1518 		} else if (rx_desc & RXQ_ERR) {  in mvs_int_rx()
1519 			if (!(rx_desc & RXQ_DONE))  in mvs_int_rx()
1520 				mvs_slot_complete(mvi, rx_desc, 0);  in mvs_int_rx()
1522 				rx_desc);  in mvs_int_rx()
1523 		} else if (rx_desc & RXQ_SLOT_RESET) {  in mvs_int_rx()
1525 				rx_desc);  in mvs_int_rx()
1526 			mvs_slot_free(mvi, rx_desc);  in mvs_int_rx()