100 static volatile struct sun3_dma_regs *dregs;  variable
191 		dregs = (struct sun3_dma_regs *)(((unsigned char *)ioaddr) + 8);  in sun3scsi_detect()
193 		if(sun3_map_test((unsigned long)dregs, &x)) {  in sun3scsi_detect()
196 			oldcsr = dregs->csr;  in sun3scsi_detect()
197 			dregs->csr = 0;  in sun3scsi_detect()
199 			if(dregs->csr == 0x1400)  in sun3scsi_detect()
202 			dregs->csr = oldcsr;  in sun3scsi_detect()
257 	dregs->csr = 0;  in sun3scsi_detect()
259 	dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;  in sun3scsi_detect()
261 	dregs->fifo_count = 0;  in sun3scsi_detect()
262 	dregs->fifo_count_hi = 0;  in sun3scsi_detect()
263 	dregs->dma_addr_hi = 0;  in sun3scsi_detect()
264 	dregs->dma_addr_lo = 0;  in sun3scsi_detect()
265 	dregs->dma_count_hi = 0;  in sun3scsi_detect()
266 	dregs->dma_count_lo = 0;  in sun3scsi_detect()
268 	dregs->ivect = VME_DATA24 | (instance->irq & 0xff);  in sun3scsi_detect()
344 	unsigned short csr = dregs->csr;  in scsi_sun3_intr()
347 	dregs->csr &= ~CSR_DMA_ENABLE;  in scsi_sun3_intr()
359 			       dregs->fifo_count,  in scsi_sun3_intr()
360 			       dregs->dma_count_lo | (dregs->dma_count_hi << 16),  in scsi_sun3_intr()
362 			       dregs->dma_addr_lo | (dregs->dma_addr_hi << 16));  in scsi_sun3_intr()
422 	dregs->csr &= ~CSR_FIFO;  in sun3scsi_dma_setup()
423 	dregs->csr |= CSR_FIFO;  in sun3scsi_dma_setup()
427 		dregs->csr |= CSR_SEND;  in sun3scsi_dma_setup()
429 		dregs->csr &= ~CSR_SEND;  in sun3scsi_dma_setup()
435 	dregs->csr |= CSR_PACK_ENABLE;  in sun3scsi_dma_setup()
437 	dregs->dma_addr_hi = ((unsigned long)addr >> 16);  in sun3scsi_dma_setup()
438 	dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);  in sun3scsi_dma_setup()
440 	dregs->dma_count_hi = 0;  in sun3scsi_dma_setup()
441 	dregs->dma_count_lo = 0;  in sun3scsi_dma_setup()
442 	dregs->fifo_count_hi = 0;  in sun3scsi_dma_setup()
443 	dregs->fifo_count = 0;  in sun3scsi_dma_setup()
446 	printk("scsi: dma_setup done csr %x\n", dregs->csr);  in sun3scsi_dma_setup()
472 	csr = dregs->csr;  in sun3scsi_dma_start()
474 	printk("scsi: dma_start data %p count %x csr %x fifo %x\n", data, count, csr, dregs->fifo_count);  in sun3scsi_dma_start()
477 	dregs->dma_count_hi = (sun3_dma_orig_count >> 16);  in sun3scsi_dma_start()
478 	dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);  in sun3scsi_dma_start()
480 	dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);  in sun3scsi_dma_start()
481 	dregs->fifo_count = (sun3_dma_orig_count & 0xffff);  in sun3scsi_dma_start()
497 	dregs->csr &= ~CSR_DMA_ENABLE;  in sun3scsi_dma_finish()
499 	fifo = dregs->fifo_count;  in sun3scsi_dma_finish()
510 	if((!write_flag) && (dregs->csr & CSR_LEFT)) {  in sun3scsi_dma_finish()
522 		switch(dregs->csr & CSR_LEFT) {  in sun3scsi_dma_finish()
524 			*vaddr = (dregs->bpack_lo & 0xff00) >> 8;  in sun3scsi_dma_finish()
528 			*vaddr = (dregs->bpack_hi & 0x00ff);  in sun3scsi_dma_finish()
532 			*vaddr = (dregs->bpack_hi & 0xff00) >> 8;  in sun3scsi_dma_finish()
542 	dregs->dma_addr_hi = 0;  in sun3scsi_dma_finish()
543 	dregs->dma_addr_lo = 0;  in sun3scsi_dma_finish()
544 	dregs->dma_count_hi = 0;  in sun3scsi_dma_finish()
545 	dregs->dma_count_lo = 0;  in sun3scsi_dma_finish()
547 	dregs->fifo_count = 0;  in sun3scsi_dma_finish()
548 	dregs->fifo_count_hi = 0;  in sun3scsi_dma_finish()
550 	dregs->csr &= ~CSR_SEND;  in sun3scsi_dma_finish()
556 	dregs->csr &= ~CSR_FIFO;  in sun3scsi_dma_finish()
557 	dregs->csr |= CSR_FIFO;  in sun3scsi_dma_finish()