Lines Matching refs:csr
102 u32 csr; in proc_ep_show() local
108 csr = __raw_readl(ep->creg); in proc_ep_show()
122 csr, in proc_ep_show()
123 (csr & 0x07ff0000) >> 16, in proc_ep_show()
124 (csr & (1 << 15)) ? "enabled" : "disabled", in proc_ep_show()
125 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show()
126 types[(csr & 0x700) >> 8], in proc_ep_show()
129 (!(csr & 0x700)) in proc_ep_show()
130 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show()
132 (csr & (1 << 6)) ? " rxdatabk1" : "", in proc_ep_show()
133 (csr & (1 << 5)) ? " forcestall" : "", in proc_ep_show()
134 (csr & (1 << 4)) ? " txpktrdy" : "", in proc_ep_show()
136 (csr & (1 << 3)) ? " stallsent" : "", in proc_ep_show()
137 (csr & (1 << 2)) ? " rxsetup" : "", in proc_ep_show()
138 (csr & (1 << 1)) ? " rxdatabk0" : "", in proc_ep_show()
139 (csr & (1 << 0)) ? " txcomp" : ""); in proc_ep_show()
314 u32 csr; in read_fifo() local
326 csr = __raw_readl(creg); in read_fifo()
327 if ((csr & RX_DATA_READY) == 0) in read_fifo()
330 count = (csr & AT91_UDP_RXBYTECNT) >> 16; in read_fifo()
341 csr |= CLR_FX; in read_fifo()
344 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in read_fifo()
347 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1); in read_fifo()
351 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in read_fifo()
352 __raw_writel(csr, creg); in read_fifo()
381 u32 csr = __raw_readl(creg); in write_fifo() local
398 if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) { in write_fifo()
399 if (csr & AT91_UDP_TXCOMP) { in write_fifo()
400 csr |= CLR_FX; in write_fifo()
401 csr &= ~(SET_FX | AT91_UDP_TXCOMP); in write_fifo()
402 __raw_writel(csr, creg); in write_fifo()
403 csr = __raw_readl(creg); in write_fifo()
405 if (csr & AT91_UDP_TXPKTRDY) in write_fifo()
434 csr &= ~SET_FX; in write_fifo()
435 csr |= CLR_FX | AT91_UDP_TXPKTRDY; in write_fifo()
436 __raw_writel(csr, creg); in write_fifo()
724 u32 csr; in at91_ep_set_halt() local
734 csr = __raw_readl(creg); in at91_ep_set_halt()
741 if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0)) in at91_ep_set_halt()
744 csr |= CLR_FX; in at91_ep_set_halt()
745 csr &= ~SET_FX; in at91_ep_set_halt()
747 csr |= AT91_UDP_FORCESTALL; in at91_ep_set_halt()
752 csr &= ~AT91_UDP_FORCESTALL; in at91_ep_set_halt()
754 __raw_writel(csr, creg); in at91_ep_set_halt()
984 u32 csr = __raw_readl(creg); in handle_ep() local
993 if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) { in handle_ep()
994 csr |= CLR_FX; in handle_ep()
995 csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP); in handle_ep()
996 __raw_writel(csr, creg); in handle_ep()
1002 if (csr & AT91_UDP_STALLSENT) { in handle_ep()
1006 csr |= CLR_FX; in handle_ep()
1007 csr &= ~(SET_FX | AT91_UDP_STALLSENT); in handle_ep()
1008 __raw_writel(csr, creg); in handle_ep()
1009 csr = __raw_readl(creg); in handle_ep()
1011 if (req && (csr & RX_DATA_READY)) in handle_ep()
1022 static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr) in handle_setup() argument
1032 rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16; in handle_setup()
1037 csr |= AT91_UDP_DIR; in handle_setup()
1040 csr &= ~AT91_UDP_DIR; in handle_setup()
1045 ERR("SETUP len %d, csr %08x\n", rxcount, csr); in handle_setup()
1048 csr |= CLR_FX; in handle_setup()
1049 csr &= ~(SET_FX | AT91_UDP_RXSETUP); in handle_setup()
1050 __raw_writel(csr, creg); in handle_setup()
1070 csr = __raw_readl(creg); in handle_setup()
1071 csr |= CLR_FX; in handle_setup()
1072 csr &= ~SET_FX; in handle_setup()
1077 __raw_writel(csr | AT91_UDP_TXPKTRDY, creg); in handle_setup()
1230 csr |= AT91_UDP_FORCESTALL; in handle_setup()
1231 __raw_writel(csr, creg); in handle_setup()
1240 csr |= AT91_UDP_TXPKTRDY; in handle_setup()
1241 __raw_writel(csr, creg); in handle_setup()
1250 u32 csr = __raw_readl(creg); in handle_ep0() local
1253 if (unlikely(csr & AT91_UDP_STALLSENT)) { in handle_ep0()
1256 csr |= CLR_FX; in handle_ep0()
1257 csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL); in handle_ep0()
1258 __raw_writel(csr, creg); in handle_ep0()
1260 csr = __raw_readl(creg); in handle_ep0()
1262 if (csr & AT91_UDP_RXSETUP) { in handle_ep0()
1265 handle_setup(udc, ep0, csr); in handle_ep0()
1275 if (csr & AT91_UDP_TXCOMP) { in handle_ep0()
1276 csr |= CLR_FX; in handle_ep0()
1277 csr &= ~(SET_FX | AT91_UDP_TXCOMP); in handle_ep0()
1294 __raw_writel(csr, creg); in handle_ep0()
1318 else if (csr & AT91_UDP_RX_DATA_BK0) { in handle_ep0()
1319 csr |= CLR_FX; in handle_ep0()
1320 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in handle_ep0()
1328 csr = __raw_readl(creg); in handle_ep0()
1329 csr &= ~SET_FX; in handle_ep0()
1330 csr |= CLR_FX | AT91_UDP_TXPKTRDY; in handle_ep0()
1331 __raw_writel(csr, creg); in handle_ep0()
1353 __raw_writel(csr | AT91_UDP_FORCESTALL, creg); in handle_ep0()
1360 __raw_writel(csr, creg); in handle_ep0()