Lines Matching refs:aty_st_le32
522 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) macro
546 aty_st_le32(CLOCK_CNTL_DATA, val); in _aty_st_pll()
591 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); in register_test()
593 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); in register_test()
599 aty_st_le32(BIOS_0_SCRATCH, val); // restore value in register_test()
657 aty_st_le32(PC_NGUI_CTLSTAT, tmp); in aty128_flush_pixel_cache()
677 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); in aty128_reset_engine()
679 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); in aty128_reset_engine()
683 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); in aty128_reset_engine()
684 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); in aty128_reset_engine()
687 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); in aty128_reset_engine()
701 aty_st_le32(SCALE_3D_CNTL, 0x00000000); in aty128_init_engine()
712 aty_st_le32(DEFAULT_OFFSET, 0x00000000); in aty128_init_engine()
715 aty_st_le32(DEFAULT_PITCH, pitch_value); in aty128_init_engine()
718 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); in aty128_init_engine()
721 aty_st_le32(DP_GUI_MASTER_CNTL, in aty128_init_engine()
740 aty_st_le32(DST_BRES_ERR, 0); in aty128_init_engine()
741 aty_st_le32(DST_BRES_INC, 0); in aty128_init_engine()
742 aty_st_le32(DST_BRES_DEC, 0); in aty128_init_engine()
745 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ in aty128_init_engine()
746 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ in aty128_init_engine()
749 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ in aty128_init_engine()
750 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ in aty128_init_engine()
753 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); in aty128_init_engine()
795 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); in aty128_map_ROM()
988 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); in aty128_set_crtc()
989 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); in aty128_set_crtc()
990 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); in aty128_set_crtc()
991 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); in aty128_set_crtc()
992 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); in aty128_set_crtc()
993 aty_st_le32(CRTC_PITCH, crtc->pitch); in aty128_set_crtc()
994 aty_st_le32(CRTC_OFFSET, crtc->offset); in aty128_set_crtc()
995 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); in aty128_set_crtc()
1251 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON); in aty128_set_crt_enable()
1252 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN)); in aty128_set_crt_enable()
1254 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON); in aty128_set_crt_enable()
1268 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_lcd_enable()
1278 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_lcd_enable()
1281 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_lcd_enable()
1293 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); in aty128_set_pll()
1381 aty_st_le32(DDA_CONFIG, dsp->dda_config); in aty128_set_fifo()
1382 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); in aty128_set_fifo()
1459 aty_st_le32(OVR_CLR, 0); in aty128fb_set_par()
1460 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); in aty128fb_set_par()
1461 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); in aty128fb_set_par()
1462 aty_st_le32(OV0_SCALE_CNTL, 0); in aty128fb_set_par()
1463 aty_st_le32(MPP_TB_CONFIG, 0); in aty128fb_set_par()
1464 aty_st_le32(MPP_GP_CONFIG, 0); in aty128fb_set_par()
1465 aty_st_le32(SUBPIC_CNTL, 0); in aty128fb_set_par()
1466 aty_st_le32(VIPH_CONTROL, 0); in aty128fb_set_par()
1467 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ in aty128fb_set_par()
1468 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ in aty128fb_set_par()
1469 aty_st_le32(CAP0_TRIG_CNTL, 0); in aty128fb_set_par()
1470 aty_st_le32(CAP1_TRIG_CNTL, 0); in aty128fb_set_par()
1487 aty_st_le32(CNFG_CNTL, config); in aty128fb_set_par()
1603 aty_st_le32(CRTC_OFFSET, offset); in aty128fb_pan_display()
1624 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL); in aty128_st_pal()
1626 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); in aty128_st_pal()
1628 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL); in aty128_st_pal()
1632 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); in aty128_st_pal()
1750 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_bl_update_status()
1754 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_bl_update_status()
1762 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_bl_update_status()
1764 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); in aty128_bl_update_status()
1771 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_bl_update_status()
1776 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_bl_update_status()
1778 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); in aty128_bl_update_status()
1985 aty_st_le32(DAC_CNTL, dac); in aty128_init()
1988 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); in aty128_init()
2338 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2339 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2340 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2341 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2343 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2344 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2349 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2350 aty_st_le32(DP_CNTL, save_dp_cntl);
2392 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & in aty128_set_suspend()
2400 aty_st_le32(BUS_CNTL1, 0x00000010); in aty128_set_suspend()
2401 aty_st_le32(MEM_POWER_MISC, 0x0c830000); in aty128_set_suspend()