Lines Matching refs:OUTPLL
136 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
145 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
158 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
168 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_disable_dynamic_mode()
179 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
184 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
192 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
198 OUTPLL(pllVCLK_ECP_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
215 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
255 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
263 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_disable_dynamic_mode()
269 OUTPLL(pllCLK_PIN_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
279 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
289 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
297 OUTPLL(pllMCLK_MISC, tmp); in radeon_pm_disable_dynamic_mode()
306 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
318 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
324 OUTPLL( pllVCLK_ECP_CNTL, tmp); in radeon_pm_disable_dynamic_mode()
343 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
356 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_enable_dynamic_mode()
368 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
375 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
380 OUTPLL(pllVCLK_ECP_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
396 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
401 OUTPLL(pllMCLK_MISC, tmp); in radeon_pm_enable_dynamic_mode()
428 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
437 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
444 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_pm_enable_dynamic_mode()
455 OUTPLL( pllCLK_PWRMGT_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
460 OUTPLL(pllCLK_PIN_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
477 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
492 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
503 OUTPLL(pllPLL_PWRMGT_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
515 OUTPLL(pllPIXCLKS_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
521 OUTPLL(pllVCLK_ECP_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
531 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_enable_dynamic_mode()
539 OUTPLL(pllMCLK_MISC, tmp); in radeon_pm_enable_dynamic_mode()
687 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */ in radeon_pm_restore_regs()
689 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]); in radeon_pm_restore_regs()
690 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]); in radeon_pm_restore_regs()
691 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]); in radeon_pm_restore_regs()
692 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]); in radeon_pm_restore_regs()
693 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]); in radeon_pm_restore_regs()
694 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]); in radeon_pm_restore_regs()
695 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]); in radeon_pm_restore_regs()
696 OUTPLL(MCLK_MISC, rinfo->save_regs[7]); in radeon_pm_restore_regs()
698 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]); in radeon_pm_restore_regs()
717 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]); in radeon_pm_restore_regs()
749 OUTPLL(pllPIXCLKS_CNTL, in radeon_pm_program_v2clk()
753 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c); in radeon_pm_program_v2clk()
754 OUTPLL(pllP2PLL_CNTL, 0x0000bf00); in radeon_pm_program_v2clk()
756 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c); in radeon_pm_program_v2clk()
758 OUTPLL(pllP2PLL_CNTL, 0x0000a700); in radeon_pm_program_v2clk()
761 OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W); in radeon_pm_program_v2clk()
763 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP); in radeon_pm_program_v2clk()
766 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET); in radeon_pm_program_v2clk()
769 OUTPLL(pllPIXCLKS_CNTL, in radeon_pm_program_v2clk()
793 OUTPLL(PLL_PWRMGT_CNTL, reg); in radeon_pm_low_current()
869 OUTPLL( pllSCLK_CNTL, sclk_cntl); in radeon_pm_setup_for_suspend()
876 OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl); in radeon_pm_setup_for_suspend()
886 OUTPLL( pllMCLK_CNTL, mclk_cntl); in radeon_pm_setup_for_suspend()
893 OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl); in radeon_pm_setup_for_suspend()
905 OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl); in radeon_pm_setup_for_suspend()
920 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl); in radeon_pm_setup_for_suspend()
942 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl); in radeon_pm_setup_for_suspend()
950 OUTPLL( pllMCLK_MISC, tmp); in radeon_pm_setup_for_suspend()
977 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl); in radeon_pm_setup_for_suspend()
987 OUTPLL( pllPLL_PWRMGT_CNTL, tmp); in radeon_pm_setup_for_suspend()
1042 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl); in radeon_pm_setup_for_suspend()
1043 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl); in radeon_pm_setup_for_suspend()
1044 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl); in radeon_pm_setup_for_suspend()
1159 OUTPLL(pllMDLL_CKO, cko); in radeon_pm_enable_dll()
1160 OUTPLL(pllMDLL_RDCKA, cka); in radeon_pm_enable_dll()
1161 OUTPLL(pllMDLL_RDCKB, ckb); in radeon_pm_enable_dll()
1166 OUTPLL(pllMDLL_CKO, cko); in radeon_pm_enable_dll()
1169 OUTPLL(pllMDLL_CKO, cko); in radeon_pm_enable_dll()
1173 OUTPLL(pllMDLL_RDCKA, cka); in radeon_pm_enable_dll()
1176 OUTPLL(pllMDLL_RDCKA, cka); in radeon_pm_enable_dll()
1180 OUTPLL(pllMDLL_RDCKB, ckb); in radeon_pm_enable_dll()
1183 OUTPLL(pllMDLL_RDCKB, ckb); in radeon_pm_enable_dll()
1230 OUTPLL(pllMDLL_RDCKA, dll_value); in radeon_pm_enable_dll_m10()
1234 OUTPLL(pllMDLL_RDCKA, dll_value); in radeon_pm_enable_dll_m10()
1458 OUTPLL(pllPPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1460 OUTPLL(pllP2PLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1462 OUTPLL(pllSPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1464 OUTPLL(pllMPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1473 OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK); in radeon_pm_start_mclk_sclk()
1485 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); in radeon_pm_start_mclk_sclk()
1489 OUTPLL(pllSPLL_CNTL, tmp & ~1); in radeon_pm_start_mclk_sclk()
1496 OUTPLL(pllSPLL_CNTL, tmp & ~0x2); in radeon_pm_start_mclk_sclk()
1505 OUTPLL(pllSCLK_CNTL, tmp); in radeon_pm_start_mclk_sclk()
1521 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); in radeon_pm_start_mclk_sclk()
1524 OUTPLL(pllMPLL_CNTL, tmp & ~0x2); in radeon_pm_start_mclk_sclk()
1531 OUTPLL(pllMPLL_CNTL, tmp & ~0x1); in radeon_pm_start_mclk_sclk()
1539 OUTPLL(pllMCLK_CNTL, tmp); in radeon_pm_start_mclk_sclk()
1560 OUTPLL(pllSSPLL_CNTL, 0xbf03); in radeon_pm_m10_disable_spread_spectrum()
1563 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3); in radeon_pm_m10_disable_spread_spectrum()
1587 OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3); in radeon_pm_m10_enable_lvds_spread_spectrum()
1590 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1591 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1593 OUTPLL(pllSSPLL_CNTL, tmp & ~0x2); in radeon_pm_m10_enable_lvds_spread_spectrum()
1596 OUTPLL(pllSSPLL_CNTL, tmp & ~0x1); in radeon_pm_m10_enable_lvds_spread_spectrum()
1599 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1615 OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1616 OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1626 OUTPLL(pllSS_TST_CNTL, tmp); in radeon_pm_m10_enable_lvds_spread_spectrum()
1639 OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80); in radeon_pm_restore_pixel_pll()
1644 OUTPLL(pllPPLL_REF_DIV, tmp); in radeon_pm_restore_pixel_pll()
1659 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]); in radeon_pm_restore_pixel_pll()
1662 OUTPLL(pllPPLL_CNTL, tmp & ~0x2); in radeon_pm_restore_pixel_pll()
1666 OUTPLL(pllPPLL_CNTL, tmp & ~0x1); in radeon_pm_restore_pixel_pll()
1670 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); in radeon_pm_restore_pixel_pll()
1674 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); in radeon_pm_restore_pixel_pll()
1772 OUTPLL(pllCLK_PWRMGT_CNTL, tmp); in radeon_reinitialize_M10()
1796 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]); in radeon_reinitialize_M10()
1805 OUTPLL(pllMCLK_CNTL, tmp); in radeon_reinitialize_M10()
1837 OUTPLL(pllSCLK_CNTL, tmp); in radeon_reinitialize_M10()
1839 OUTPLL(pllVCLK_ECP_CNTL, 0); in radeon_reinitialize_M10()
1840 OUTPLL(pllPIXCLKS_CNTL, 0); in radeon_reinitialize_M10()
1841 OUTPLL(pllMCLK_MISC, in radeon_reinitialize_M10()
1848 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]); in radeon_reinitialize_M10()
1849 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]); in radeon_reinitialize_M10()
1850 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]); in radeon_reinitialize_M10()
1853 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3); in radeon_reinitialize_M10()
1854 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3); in radeon_reinitialize_M10()
1855 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03); in radeon_reinitialize_M10()
1856 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M10()
1862 OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff); in radeon_reinitialize_M10()
1868 OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]); in radeon_reinitialize_M10()
1871 OUTPLL(pllHTOTAL_CNTL, 0); in radeon_reinitialize_M10()
1872 OUTPLL(pllHTOTAL2_CNTL, 0); in radeon_reinitialize_M10()
1876 OUTPLL(pllSCLK_CNTL2, tmp); in radeon_reinitialize_M10()
1882 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_reinitialize_M10()
2013 OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]); in radeon_reinitialize_M9P()
2026 OUTPLL(pllCLK_PWRMGT_CNTL, tmp); in radeon_reinitialize_M9P()
2035 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]); in radeon_reinitialize_M9P()
2045 OUTPLL(pllMCLK_CNTL, tmp); in radeon_reinitialize_M9P()
2063 OUTPLL(pllSCLK_CNTL, tmp); in radeon_reinitialize_M9P()
2066 OUTPLL(pllVCLK_ECP_CNTL, 0); in radeon_reinitialize_M9P()
2067 OUTPLL(pllPIXCLKS_CNTL, 0); in radeon_reinitialize_M9P()
2070 OUTPLL(pllMCLK_MISC, in radeon_reinitialize_M9P()
2077 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]); in radeon_reinitialize_M9P()
2078 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]); in radeon_reinitialize_M9P()
2079 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]); in radeon_reinitialize_M9P()
2082 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3); in radeon_reinitialize_M9P()
2083 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3); in radeon_reinitialize_M9P()
2086 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03); in radeon_reinitialize_M9P()
2087 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M9P()
2090 OUTPLL(pllMDLL_CKO, 0x9c009c); in radeon_reinitialize_M9P()
2091 OUTPLL(pllMDLL_RDCKA, 0x08830883); in radeon_reinitialize_M9P()
2092 OUTPLL(pllMDLL_RDCKB, 0x08830883); in radeon_reinitialize_M9P()
2099 OUTPLL(PLL_PWRMGT_CNTL, tmp); in radeon_reinitialize_M9P()
2102 OUTPLL(pllHTOTAL_CNTL, 0); in radeon_reinitialize_M9P()
2103 OUTPLL(pllHTOTAL2_CNTL, 0); in radeon_reinitialize_M9P()
2152 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_reinitialize_M9P()
2157 OUTPLL(pllSCLK_MORE_CNTL, tmp); in radeon_reinitialize_M9P()
2170 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */); in radeon_reinitialize_M9P()
2171 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */); in radeon_reinitialize_M9P()
2174 OUTPLL(pllSSPLL_CNTL, tmp); in radeon_reinitialize_M9P()
2177 OUTPLL(pllSSPLL_CNTL, tmp); in radeon_reinitialize_M9P()
2180 OUTPLL(pllSSPLL_CNTL, tmp); in radeon_reinitialize_M9P()
2183 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/ in radeon_reinitialize_M9P()
2187 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div); in radeon_reinitialize_M9P()
2188 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]); in radeon_reinitialize_M9P()
2246 OUTPLL(pllVCLK_ECP_CNTL, tmp);
2248 OUTPLL(pllPIXCLKS_CNTL, tmp);
2250 OUTPLL(MCLK_CNTL, 0xaa3f0000);
2251 OUTPLL(SCLK_CNTL, 0xffff0000);
2252 OUTPLL(pllMPLL_AUX_CNTL, 6);
2253 OUTPLL(pllSPLL_AUX_CNTL, 1);
2254 OUTPLL(MDLL_CKO, 0x9f009f);
2255 OUTPLL(MDLL_RDCKA, 0x830083);
2256 OUTPLL(pllMDLL_RDCKB, 0x830083);
2257 OUTPLL(PPLL_CNTL, 0xa433);
2258 OUTPLL(P2PLL_CNTL, 0xa433);
2259 OUTPLL(MPLL_CNTL, 0x0400a403);
2260 OUTPLL(SPLL_CNTL, 0x0400a433);
2263 OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2265 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2275 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2278 OUTPLL(MPLL_CNTL, tmp & ~0x2);
2281 OUTPLL(MPLL_CNTL, tmp & ~0x1);
2284 OUTPLL(MCLK_CNTL, 0xaa3f1212);
2298 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2301 OUTPLL(SPLL_CNTL, tmp & ~0x1);
2304 OUTPLL(SPLL_CNTL, tmp & ~0x2);
2308 OUTPLL(SCLK_CNTL, tmp | 2);
2316 OUTPLL(pllMDLL_CKO, cko);
2319 OUTPLL(pllMDLL_CKO, cko);
2323 OUTPLL(pllMDLL_RDCKA, cka);
2326 OUTPLL(pllMDLL_RDCKA, cka);
2330 OUTPLL(pllMDLL_RDCKB, ckb);
2333 OUTPLL(pllMDLL_RDCKB, ckb);
2347 OUTPLL(pllHTOTAL_CNTL, 0);
2348 OUTPLL(pllHTOTAL2_CNTL, 0);
2378 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2379 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2380 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2384 OUTPLL(MCLK_MISC, tmp);
2387 OUTPLL(SCLK_CNTL, tmp);
2395 OUTPLL(VCLK_ECP_CNTL, tmp);
2398 OUTPLL(PPLL_CNTL, tmp);
2443 OUTPLL(PPLL_REF_DIV, tmp);
2457 OUTPLL(PPLL_DIV_0, 0x48090);
2460 OUTPLL(PPLL_CNTL, tmp & ~0x2);
2463 OUTPLL(PPLL_CNTL, tmp & ~0x1);
2467 OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2471 OUTPLL(VCLK_ECP_CNTL, tmp);
2573 OUTPLL( pllMDLL_CKO, tmp ); in radeon_set_suspend()