Lines Matching refs:BIT1
734 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
744 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
747 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
754 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
755 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
787 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
794 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
801 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
856 BIT0 + BIT1 + BIT4); in set_dvi_output_path()
860 BIT0 + BIT1 + BIT4); in set_dvi_output_path()
878 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in set_dvi_output_path()
970 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
1055 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
1070 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); in load_fix_bit_crtc_reg()
1572 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); in viafb_set_vclock()
1573 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); in viafb_set_vclock()
2748 p_gfx_dpa_setting->DVP0DataDri_S, BIT1); in viafb_set_dpa_gfx()