257 			rmh.cmd[0] |= IO_NUM_REG_GENCLK;  in pcxhr_get_clock_reg()
258 			rmh.cmd[1]  = pllreg & MASK_DSP_WORD;  in pcxhr_get_clock_reg()
259 			rmh.cmd[2]  = pllreg >> 24;  in pcxhr_get_clock_reg()
318 		rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;  in pcxhr_sub_set_clock()
320 			rmh.cmd[1]  = 1;  in pcxhr_sub_set_clock()
328 		rmh.cmd[0] |= IO_NUM_SPEED_RATIO;  in pcxhr_sub_set_clock()
329 		rmh.cmd[1] = speed;  in pcxhr_sub_set_clock()
348 		rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;  in pcxhr_sub_set_clock()
350 			rmh.cmd[1]  = 1;  in pcxhr_sub_set_clock()
387 		rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos  */  in pcxhr_set_clock()
389 			rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;  in pcxhr_set_clock()
391 			rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;  in pcxhr_set_clock()
392 		rmh.cmd[2] = rate;  in pcxhr_set_clock()
434 	rmh.cmd[0] |= IO_NUM_REG_STATUS;  in pcxhr_sub_get_external_clock()
436 		rmh.cmd[1]  = reg;  in pcxhr_sub_get_external_clock()
443 	rmh.cmd[1]  = REG_STATUS_CURRENT;  in pcxhr_sub_get_external_clock()
588 			rmh.cmd[0] |= 1<<10;  in pcxhr_set_format()
590 			rmh.cmd[0] |= 1<<12;  in pcxhr_set_format()
592 	rmh.cmd[1] = 0;  in pcxhr_set_format()
596 		rmh.cmd[1] = stream->channels;  in pcxhr_set_format()
599 			rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03;  in pcxhr_set_format()
603 	rmh.cmd[rmh.cmd_len++] = header >> 8;  in pcxhr_set_format()
604 	rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16;  in pcxhr_set_format()
634 	rmh.cmd[1] = subs->runtime->dma_bytes * 8;  in pcxhr_update_r_buffer()
636 	rmh.cmd[2] = subs->runtime->dma_addr >> 24;  in pcxhr_update_r_buffer()
638 	rmh.cmd[2] |= 1<<19;  in pcxhr_update_r_buffer()
640 	rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;  in pcxhr_update_r_buffer()
813 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)  in pcxhr_trigger()  argument
818 	switch (cmd) {  in pcxhr_trigger()
877 		rmh.cmd[0] |= mgr->granularity;  in pcxhr_hardware_timer()
1278 		rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;  in pcxhr_proc_info()