Lines Matching defs:ccsr_ssi
16 struct ccsr_ssi { struct
17 __be32 stx0; /* 0x.0000 - SSI Transmit Data Register 0 */
18 __be32 stx1; /* 0x.0004 - SSI Transmit Data Register 1 */
19 __be32 srx0; /* 0x.0008 - SSI Receive Data Register 0 */
20 __be32 srx1; /* 0x.000C - SSI Receive Data Register 1 */
21 __be32 scr; /* 0x.0010 - SSI Control Register */
22 __be32 sisr; /* 0x.0014 - SSI Interrupt Status Register Mixed */
23 __be32 sier; /* 0x.0018 - SSI Interrupt Enable Register */
24 __be32 stcr; /* 0x.001C - SSI Transmit Configuration Register */
25 __be32 srcr; /* 0x.0020 - SSI Receive Configuration Register */
26 __be32 stccr; /* 0x.0024 - SSI Transmit Clock Control Register */
27 __be32 srccr; /* 0x.0028 - SSI Receive Clock Control Register */
28 __be32 sfcsr; /* 0x.002C - SSI FIFO Control/Status Register */
29 __be32 str; /* 0x.0030 - SSI Test Register */
30 __be32 sor; /* 0x.0034 - SSI Option Register */
31 __be32 sacnt; /* 0x.0038 - SSI AC97 Control Register */
32 __be32 sacadd; /* 0x.003C - SSI AC97 Command Address Register */
33 __be32 sacdat; /* 0x.0040 - SSI AC97 Command Data Register */
34 __be32 satag; /* 0x.0044 - SSI AC97 Tag Register */
35 __be32 stmsk; /* 0x.0048 - SSI Transmit Time Slot Mask Register */
36 __be32 srmsk; /* 0x.004C - SSI Receive Time Slot Mask Register */
37 __be32 saccst; /* 0x.0050 - SSI AC97 Channel Status Register */
38 __be32 saccen; /* 0x.0054 - SSI AC97 Channel Enable Register */
39 __be32 saccdis; /* 0x.0058 - SSI AC97 Channel Disable Register */