1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This software may be redistributed and/or modified under
6 * the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * File: via-velocity.h
16 *
17 * Purpose: Header file to define driver's private structures.
18 *
19 * Author: Chuang Liang-Shing, AJ Jiang
20 *
21 * Date: Jan 24, 2003
22 */
23
24
25 #ifndef VELOCITY_H
26 #define VELOCITY_H
27
28 #define VELOCITY_TX_CSUM_SUPPORT
29
30 #define VELOCITY_NAME "via-velocity"
31 #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
32 #define VELOCITY_VERSION "1.14"
33
34 #define VELOCITY_IO_SIZE 256
35
36 #define PKT_BUF_SZ 1540
37
38 #define MAX_UNITS 8
39 #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
40
41 #define REV_ID_VT6110 (0)
42
43 #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0)
44 #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0)
45 #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
46
47 #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x))
48 #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x))
49 #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x))
50
51 #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0)
52 #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0)
53 #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
54
55 #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
56 #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
57 #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0)
58
59 #define VAR_USED(p) do {(p)=(p);} while (0)
60
61 /*
62 * Purpose: Structures for MAX RX/TX descriptors.
63 */
64
65
66 #define B_OWNED_BY_CHIP 1
67 #define B_OWNED_BY_HOST 0
68
69 /*
70 * Bits in the RSR0 register
71 */
72
73 #define RSR_DETAG cpu_to_le16(0x0080)
74 #define RSR_SNTAG cpu_to_le16(0x0040)
75 #define RSR_RXER cpu_to_le16(0x0020)
76 #define RSR_RL cpu_to_le16(0x0010)
77 #define RSR_CE cpu_to_le16(0x0008)
78 #define RSR_FAE cpu_to_le16(0x0004)
79 #define RSR_CRC cpu_to_le16(0x0002)
80 #define RSR_VIDM cpu_to_le16(0x0001)
81
82 /*
83 * Bits in the RSR1 register
84 */
85
86 #define RSR_RXOK cpu_to_le16(0x8000) // rx OK
87 #define RSR_PFT cpu_to_le16(0x4000) // Perfect filtering address match
88 #define RSR_MAR cpu_to_le16(0x2000) // MAC accept multicast address packet
89 #define RSR_BAR cpu_to_le16(0x1000) // MAC accept broadcast address packet
90 #define RSR_PHY cpu_to_le16(0x0800) // MAC accept physical address packet
91 #define RSR_VTAG cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator
92 #define RSR_STP cpu_to_le16(0x0200) // start of packet
93 #define RSR_EDP cpu_to_le16(0x0100) // end of packet
94
95 /*
96 * Bits in the CSM register
97 */
98
99 #define CSM_IPOK 0x40 //IP Checkusm validatiaon ok
100 #define CSM_TUPOK 0x20 //TCP/UDP Checkusm validatiaon ok
101 #define CSM_FRAG 0x10 //Fragment IP datagram
102 #define CSM_IPKT 0x04 //Received an IP packet
103 #define CSM_TCPKT 0x02 //Received a TCP packet
104 #define CSM_UDPKT 0x01 //Received a UDP packet
105
106 /*
107 * Bits in the TSR0 register
108 */
109
110 #define TSR0_ABT cpu_to_le16(0x0080) // Tx abort because of excessive collision
111 #define TSR0_OWT cpu_to_le16(0x0040) // Jumbo frame Tx abort
112 #define TSR0_OWC cpu_to_le16(0x0020) // Out of window collision
113 #define TSR0_COLS cpu_to_le16(0x0010) // experience collision in this transmit event
114 #define TSR0_NCR3 cpu_to_le16(0x0008) // collision retry counter[3]
115 #define TSR0_NCR2 cpu_to_le16(0x0004) // collision retry counter[2]
116 #define TSR0_NCR1 cpu_to_le16(0x0002) // collision retry counter[1]
117 #define TSR0_NCR0 cpu_to_le16(0x0001) // collision retry counter[0]
118 #define TSR0_TERR cpu_to_le16(0x8000) //
119 #define TSR0_FDX cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode
120 #define TSR0_GMII cpu_to_le16(0x2000) // current transaction is serviced by GMII mode
121 #define TSR0_LNKFL cpu_to_le16(0x1000) // packet serviced during link down
122 #define TSR0_SHDN cpu_to_le16(0x0400) // shutdown case
123 #define TSR0_CRS cpu_to_le16(0x0200) // carrier sense lost
124 #define TSR0_CDH cpu_to_le16(0x0100) // AQE test fail (CD heartbeat)
125
126 //
127 // Bits in the TCR0 register
128 //
129 #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete
130 #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme
131 #define TCR0_VETAG 0x20 // enable VLAN tag
132 #define TCR0_IPCK 0x10 // request IP checksum calculation.
133 #define TCR0_UDPCK 0x08 // request UDP checksum calculation.
134 #define TCR0_TCPCK 0x04 // request TCP checksum calculation.
135 #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side
136 #define TCR0_CRC 0x01 // disable CRC generation
137
138 #define TCPLS_NORMAL 3
139 #define TCPLS_START 2
140 #define TCPLS_END 1
141 #define TCPLS_MED 0
142
143
144 // max transmit or receive buffer size
145 #define CB_RX_BUF_SIZE 2048UL // max buffer size
146 // NOTE: must be multiple of 4
147
148 #define CB_MAX_RD_NUM 512 // MAX # of RD
149 #define CB_MAX_TD_NUM 256 // MAX # of TD
150
151 #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119
152 #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
153
154 #define CB_INIT_RD_NUM 128 // init # of RD, for setup default
155 #define CB_INIT_TD_NUM 64 // init # of TD, for setup default
156
157 // for 3119
158 #define CB_TD_RING_NUM 4 // # of TD rings.
159 #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx)
160
161
162 /*
163 * If collisions excess 15 times , tx will abort, and
164 * if tx fifo underflow, tx will fail
165 * we should try to resend it
166 */
167
168 #define CB_MAX_TX_ABORT_RETRY 3
169
170 /*
171 * Receive descriptor
172 */
173
174 struct rdesc0 {
175 __le16 RSR; /* Receive status */
176 __le16 len; /* bits 0--13; bit 15 - owner */
177 };
178
179 struct rdesc1 {
180 __le16 PQTAG;
181 u8 CSM;
182 u8 IPKT;
183 };
184
185 enum {
186 RX_INTEN = __constant_cpu_to_le16(0x8000)
187 };
188
189 struct rx_desc {
190 struct rdesc0 rdesc0;
191 struct rdesc1 rdesc1;
192 __le32 pa_low; /* Low 32 bit PCI address */
193 __le16 pa_high; /* Next 16 bit PCI address (48 total) */
194 __le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */
195 } __attribute__ ((__packed__));
196
197 /*
198 * Transmit descriptor
199 */
200
201 struct tdesc0 {
202 __le16 TSR; /* Transmit status register */
203 __le16 len; /* bits 0--13 - size of frame, bit 15 - owner */
204 };
205
206 struct tdesc1 {
207 __le16 vlan;
208 u8 TCR;
209 u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */
210 } __attribute__ ((__packed__));
211
212 enum {
213 TD_QUEUE = __constant_cpu_to_le16(0x8000)
214 };
215
216 struct td_buf {
217 __le32 pa_low;
218 __le16 pa_high;
219 __le16 size; /* bits 0--13 - size, bit 15 - queue */
220 } __attribute__ ((__packed__));
221
222 struct tx_desc {
223 struct tdesc0 tdesc0;
224 struct tdesc1 tdesc1;
225 struct td_buf td_buf[7];
226 };
227
228 struct velocity_rd_info {
229 struct sk_buff *skb;
230 dma_addr_t skb_dma;
231 };
232
233 /*
234 * Used to track transmit side buffers.
235 */
236
237 struct velocity_td_info {
238 struct sk_buff *skb;
239 int nskb_dma;
240 dma_addr_t skb_dma[7];
241 };
242
243 enum velocity_owner {
244 OWNED_BY_HOST = 0,
245 OWNED_BY_NIC = __constant_cpu_to_le16(0x8000)
246 };
247
248
249 /*
250 * MAC registers and macros.
251 */
252
253
254 #define MCAM_SIZE 64
255 #define VCAM_SIZE 64
256 #define TX_QUEUE_NO 4
257
258 #define MAX_HW_MIB_COUNTER 32
259 #define VELOCITY_MIN_MTU (64)
260 #define VELOCITY_MAX_MTU (9000)
261
262 /*
263 * Registers in the MAC
264 */
265
266 #define MAC_REG_PAR 0x00 // physical address
267 #define MAC_REG_RCR 0x06
268 #define MAC_REG_TCR 0x07
269 #define MAC_REG_CR0_SET 0x08
270 #define MAC_REG_CR1_SET 0x09
271 #define MAC_REG_CR2_SET 0x0A
272 #define MAC_REG_CR3_SET 0x0B
273 #define MAC_REG_CR0_CLR 0x0C
274 #define MAC_REG_CR1_CLR 0x0D
275 #define MAC_REG_CR2_CLR 0x0E
276 #define MAC_REG_CR3_CLR 0x0F
277 #define MAC_REG_MAR 0x10
278 #define MAC_REG_CAM 0x10
279 #define MAC_REG_DEC_BASE_HI 0x18
280 #define MAC_REG_DBF_BASE_HI 0x1C
281 #define MAC_REG_ISR_CTL 0x20
282 #define MAC_REG_ISR_HOTMR 0x20
283 #define MAC_REG_ISR_TSUPTHR 0x20
284 #define MAC_REG_ISR_RSUPTHR 0x20
285 #define MAC_REG_ISR_CTL1 0x21
286 #define MAC_REG_TXE_SR 0x22
287 #define MAC_REG_RXE_SR 0x23
288 #define MAC_REG_ISR 0x24
289 #define MAC_REG_ISR0 0x24
290 #define MAC_REG_ISR1 0x25
291 #define MAC_REG_ISR2 0x26
292 #define MAC_REG_ISR3 0x27
293 #define MAC_REG_IMR 0x28
294 #define MAC_REG_IMR0 0x28
295 #define MAC_REG_IMR1 0x29
296 #define MAC_REG_IMR2 0x2A
297 #define MAC_REG_IMR3 0x2B
298 #define MAC_REG_TDCSR_SET 0x30
299 #define MAC_REG_RDCSR_SET 0x32
300 #define MAC_REG_TDCSR_CLR 0x34
301 #define MAC_REG_RDCSR_CLR 0x36
302 #define MAC_REG_RDBASE_LO 0x38
303 #define MAC_REG_RDINDX 0x3C
304 #define MAC_REG_TDBASE_LO 0x40
305 #define MAC_REG_RDCSIZE 0x50
306 #define MAC_REG_TDCSIZE 0x52
307 #define MAC_REG_TDINDX 0x54
308 #define MAC_REG_TDIDX0 0x54
309 #define MAC_REG_TDIDX1 0x56
310 #define MAC_REG_TDIDX2 0x58
311 #define MAC_REG_TDIDX3 0x5A
312 #define MAC_REG_PAUSE_TIMER 0x5C
313 #define MAC_REG_RBRDU 0x5E
314 #define MAC_REG_FIFO_TEST0 0x60
315 #define MAC_REG_FIFO_TEST1 0x64
316 #define MAC_REG_CAMADDR 0x68
317 #define MAC_REG_CAMCR 0x69
318 #define MAC_REG_GFTEST 0x6A
319 #define MAC_REG_FTSTCMD 0x6B
320 #define MAC_REG_MIICFG 0x6C
321 #define MAC_REG_MIISR 0x6D
322 #define MAC_REG_PHYSR0 0x6E
323 #define MAC_REG_PHYSR1 0x6F
324 #define MAC_REG_MIICR 0x70
325 #define MAC_REG_MIIADR 0x71
326 #define MAC_REG_MIIDATA 0x72
327 #define MAC_REG_SOFT_TIMER0 0x74
328 #define MAC_REG_SOFT_TIMER1 0x76
329 #define MAC_REG_CFGA 0x78
330 #define MAC_REG_CFGB 0x79
331 #define MAC_REG_CFGC 0x7A
332 #define MAC_REG_CFGD 0x7B
333 #define MAC_REG_DCFG0 0x7C
334 #define MAC_REG_DCFG1 0x7D
335 #define MAC_REG_MCFG0 0x7E
336 #define MAC_REG_MCFG1 0x7F
337
338 #define MAC_REG_TBIST 0x80
339 #define MAC_REG_RBIST 0x81
340 #define MAC_REG_PMCC 0x82
341 #define MAC_REG_STICKHW 0x83
342 #define MAC_REG_MIBCR 0x84
343 #define MAC_REG_EERSV 0x85
344 #define MAC_REG_REVID 0x86
345 #define MAC_REG_MIBREAD 0x88
346 #define MAC_REG_BPMA 0x8C
347 #define MAC_REG_EEWR_DATA 0x8C
348 #define MAC_REG_BPMD_WR 0x8F
349 #define MAC_REG_BPCMD 0x90
350 #define MAC_REG_BPMD_RD 0x91
351 #define MAC_REG_EECHKSUM 0x92
352 #define MAC_REG_EECSR 0x93
353 #define MAC_REG_EERD_DATA 0x94
354 #define MAC_REG_EADDR 0x96
355 #define MAC_REG_EMBCMD 0x97
356 #define MAC_REG_JMPSR0 0x98
357 #define MAC_REG_JMPSR1 0x99
358 #define MAC_REG_JMPSR2 0x9A
359 #define MAC_REG_JMPSR3 0x9B
360 #define MAC_REG_CHIPGSR 0x9C
361 #define MAC_REG_TESTCFG 0x9D
362 #define MAC_REG_DEBUG 0x9E
363 #define MAC_REG_CHIPGCR 0x9F
364 #define MAC_REG_WOLCR0_SET 0xA0
365 #define MAC_REG_WOLCR1_SET 0xA1
366 #define MAC_REG_PWCFG_SET 0xA2
367 #define MAC_REG_WOLCFG_SET 0xA3
368 #define MAC_REG_WOLCR0_CLR 0xA4
369 #define MAC_REG_WOLCR1_CLR 0xA5
370 #define MAC_REG_PWCFG_CLR 0xA6
371 #define MAC_REG_WOLCFG_CLR 0xA7
372 #define MAC_REG_WOLSR0_SET 0xA8
373 #define MAC_REG_WOLSR1_SET 0xA9
374 #define MAC_REG_WOLSR0_CLR 0xAC
375 #define MAC_REG_WOLSR1_CLR 0xAD
376 #define MAC_REG_PATRN_CRC0 0xB0
377 #define MAC_REG_PATRN_CRC1 0xB2
378 #define MAC_REG_PATRN_CRC2 0xB4
379 #define MAC_REG_PATRN_CRC3 0xB6
380 #define MAC_REG_PATRN_CRC4 0xB8
381 #define MAC_REG_PATRN_CRC5 0xBA
382 #define MAC_REG_PATRN_CRC6 0xBC
383 #define MAC_REG_PATRN_CRC7 0xBE
384 #define MAC_REG_BYTEMSK0_0 0xC0
385 #define MAC_REG_BYTEMSK0_1 0xC4
386 #define MAC_REG_BYTEMSK0_2 0xC8
387 #define MAC_REG_BYTEMSK0_3 0xCC
388 #define MAC_REG_BYTEMSK1_0 0xD0
389 #define MAC_REG_BYTEMSK1_1 0xD4
390 #define MAC_REG_BYTEMSK1_2 0xD8
391 #define MAC_REG_BYTEMSK1_3 0xDC
392 #define MAC_REG_BYTEMSK2_0 0xE0
393 #define MAC_REG_BYTEMSK2_1 0xE4
394 #define MAC_REG_BYTEMSK2_2 0xE8
395 #define MAC_REG_BYTEMSK2_3 0xEC
396 #define MAC_REG_BYTEMSK3_0 0xF0
397 #define MAC_REG_BYTEMSK3_1 0xF4
398 #define MAC_REG_BYTEMSK3_2 0xF8
399 #define MAC_REG_BYTEMSK3_3 0xFC
400
401 /*
402 * Bits in the RCR register
403 */
404
405 #define RCR_AS 0x80
406 #define RCR_AP 0x40
407 #define RCR_AL 0x20
408 #define RCR_PROM 0x10
409 #define RCR_AB 0x08
410 #define RCR_AM 0x04
411 #define RCR_AR 0x02
412 #define RCR_SEP 0x01
413
414 /*
415 * Bits in the TCR register
416 */
417
418 #define TCR_TB2BDIS 0x80
419 #define TCR_COLTMC1 0x08
420 #define TCR_COLTMC0 0x04
421 #define TCR_LB1 0x02 /* loopback[1] */
422 #define TCR_LB0 0x01 /* loopback[0] */
423
424 /*
425 * Bits in the CR0 register
426 */
427
428 #define CR0_TXON 0x00000008UL
429 #define CR0_RXON 0x00000004UL
430 #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */
431 #define CR0_STRT 0x00000001UL /* start MAC */
432 #define CR0_SFRST 0x00008000UL /* software reset */
433 #define CR0_TM1EN 0x00004000UL
434 #define CR0_TM0EN 0x00002000UL
435 #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */
436 #define CR0_DISAU 0x00000100UL
437 #define CR0_XONEN 0x00800000UL
438 #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */
439 #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */
440 #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */
441 #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */
442 #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */
443 #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */
444 #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */
445 #define CR0_GSPRST 0x80000000UL
446 #define CR0_FORSRST 0x40000000UL
447 #define CR0_FPHYRST 0x20000000UL
448 #define CR0_DIAG 0x10000000UL
449 #define CR0_INTPCTL 0x04000000UL
450 #define CR0_GINTMSK1 0x02000000UL
451 #define CR0_GINTMSK0 0x01000000UL
452
453 /*
454 * Bits in the CR1 register
455 */
456
457 #define CR1_SFRST 0x80 /* software reset */
458 #define CR1_TM1EN 0x40
459 #define CR1_TM0EN 0x20
460 #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
461 #define CR1_DISAU 0x01
462
463 /*
464 * Bits in the CR2 register
465 */
466
467 #define CR2_XONEN 0x80
468 #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */
469 #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */
470 #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */
471 #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */
472 #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */
473 #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */
474 #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */
475
476 /*
477 * Bits in the CR3 register
478 */
479
480 #define CR3_GSPRST 0x80
481 #define CR3_FORSRST 0x40
482 #define CR3_FPHYRST 0x20
483 #define CR3_DIAG 0x10
484 #define CR3_INTPCTL 0x04
485 #define CR3_GINTMSK1 0x02
486 #define CR3_GINTMSK0 0x01
487
488 #define ISRCTL_UDPINT 0x8000
489 #define ISRCTL_TSUPDIS 0x4000
490 #define ISRCTL_RSUPDIS 0x2000
491 #define ISRCTL_PMSK1 0x1000
492 #define ISRCTL_PMSK0 0x0800
493 #define ISRCTL_INTPD 0x0400
494 #define ISRCTL_HCRLD 0x0200
495 #define ISRCTL_SCRLD 0x0100
496
497 /*
498 * Bits in the ISR_CTL1 register
499 */
500
501 #define ISRCTL1_UDPINT 0x80
502 #define ISRCTL1_TSUPDIS 0x40
503 #define ISRCTL1_RSUPDIS 0x20
504 #define ISRCTL1_PMSK1 0x10
505 #define ISRCTL1_PMSK0 0x08
506 #define ISRCTL1_INTPD 0x04
507 #define ISRCTL1_HCRLD 0x02
508 #define ISRCTL1_SCRLD 0x01
509
510 /*
511 * Bits in the TXE_SR register
512 */
513
514 #define TXESR_TFDBS 0x08
515 #define TXESR_TDWBS 0x04
516 #define TXESR_TDRBS 0x02
517 #define TXESR_TDSTR 0x01
518
519 /*
520 * Bits in the RXE_SR register
521 */
522
523 #define RXESR_RFDBS 0x08
524 #define RXESR_RDWBS 0x04
525 #define RXESR_RDRBS 0x02
526 #define RXESR_RDSTR 0x01
527
528 /*
529 * Bits in the ISR register
530 */
531
532 #define ISR_ISR3 0x80000000UL
533 #define ISR_ISR2 0x40000000UL
534 #define ISR_ISR1 0x20000000UL
535 #define ISR_ISR0 0x10000000UL
536 #define ISR_TXSTLI 0x02000000UL
537 #define ISR_RXSTLI 0x01000000UL
538 #define ISR_HFLD 0x00800000UL
539 #define ISR_UDPI 0x00400000UL
540 #define ISR_MIBFI 0x00200000UL
541 #define ISR_SHDNI 0x00100000UL
542 #define ISR_PHYI 0x00080000UL
543 #define ISR_PWEI 0x00040000UL
544 #define ISR_TMR1I 0x00020000UL
545 #define ISR_TMR0I 0x00010000UL
546 #define ISR_SRCI 0x00008000UL
547 #define ISR_LSTPEI 0x00004000UL
548 #define ISR_LSTEI 0x00002000UL
549 #define ISR_OVFI 0x00001000UL
550 #define ISR_FLONI 0x00000800UL
551 #define ISR_RACEI 0x00000400UL
552 #define ISR_TXWB1I 0x00000200UL
553 #define ISR_TXWB0I 0x00000100UL
554 #define ISR_PTX3I 0x00000080UL
555 #define ISR_PTX2I 0x00000040UL
556 #define ISR_PTX1I 0x00000020UL
557 #define ISR_PTX0I 0x00000010UL
558 #define ISR_PTXI 0x00000008UL
559 #define ISR_PRXI 0x00000004UL
560 #define ISR_PPTXI 0x00000002UL
561 #define ISR_PPRXI 0x00000001UL
562
563 /*
564 * Bits in the IMR register
565 */
566
567 #define IMR_TXSTLM 0x02000000UL
568 #define IMR_UDPIM 0x00400000UL
569 #define IMR_MIBFIM 0x00200000UL
570 #define IMR_SHDNIM 0x00100000UL
571 #define IMR_PHYIM 0x00080000UL
572 #define IMR_PWEIM 0x00040000UL
573 #define IMR_TMR1IM 0x00020000UL
574 #define IMR_TMR0IM 0x00010000UL
575
576 #define IMR_SRCIM 0x00008000UL
577 #define IMR_LSTPEIM 0x00004000UL
578 #define IMR_LSTEIM 0x00002000UL
579 #define IMR_OVFIM 0x00001000UL
580 #define IMR_FLONIM 0x00000800UL
581 #define IMR_RACEIM 0x00000400UL
582 #define IMR_TXWB1IM 0x00000200UL
583 #define IMR_TXWB0IM 0x00000100UL
584
585 #define IMR_PTX3IM 0x00000080UL
586 #define IMR_PTX2IM 0x00000040UL
587 #define IMR_PTX1IM 0x00000020UL
588 #define IMR_PTX0IM 0x00000010UL
589 #define IMR_PTXIM 0x00000008UL
590 #define IMR_PRXIM 0x00000004UL
591 #define IMR_PPTXIM 0x00000002UL
592 #define IMR_PPRXIM 0x00000001UL
593
594 /* 0x0013FB0FUL = initial value of IMR */
595
596 #define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\
597 IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\
598 IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
599 IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM)
600
601 /*
602 * Bits in the TDCSR0/1, RDCSR0 register
603 */
604
605 #define TRDCSR_DEAD 0x0008
606 #define TRDCSR_WAK 0x0004
607 #define TRDCSR_ACT 0x0002
608 #define TRDCSR_RUN 0x0001
609
610 /*
611 * Bits in the CAMADDR register
612 */
613
614 #define CAMADDR_CAMEN 0x80
615 #define CAMADDR_VCAMSL 0x40
616
617 /*
618 * Bits in the CAMCR register
619 */
620
621 #define CAMCR_PS1 0x80
622 #define CAMCR_PS0 0x40
623 #define CAMCR_AITRPKT 0x20
624 #define CAMCR_AITR16 0x10
625 #define CAMCR_CAMRD 0x08
626 #define CAMCR_CAMWR 0x04
627 #define CAMCR_PS_CAM_MASK 0x40
628 #define CAMCR_PS_CAM_DATA 0x80
629 #define CAMCR_PS_MAR 0x00
630
631 /*
632 * Bits in the MIICFG register
633 */
634
635 #define MIICFG_MPO1 0x80
636 #define MIICFG_MPO0 0x40
637 #define MIICFG_MFDC 0x20
638
639 /*
640 * Bits in the MIISR register
641 */
642
643 #define MIISR_MIDLE 0x80
644
645 /*
646 * Bits in the PHYSR0 register
647 */
648
649 #define PHYSR0_PHYRST 0x80
650 #define PHYSR0_LINKGD 0x40
651 #define PHYSR0_FDPX 0x10
652 #define PHYSR0_SPDG 0x08
653 #define PHYSR0_SPD10 0x04
654 #define PHYSR0_RXFLC 0x02
655 #define PHYSR0_TXFLC 0x01
656
657 /*
658 * Bits in the PHYSR1 register
659 */
660
661 #define PHYSR1_PHYTBI 0x01
662
663 /*
664 * Bits in the MIICR register
665 */
666
667 #define MIICR_MAUTO 0x80
668 #define MIICR_RCMD 0x40
669 #define MIICR_WCMD 0x20
670 #define MIICR_MDPM 0x10
671 #define MIICR_MOUT 0x08
672 #define MIICR_MDO 0x04
673 #define MIICR_MDI 0x02
674 #define MIICR_MDC 0x01
675
676 /*
677 * Bits in the MIIADR register
678 */
679
680 #define MIIADR_SWMPL 0x80
681
682 /*
683 * Bits in the CFGA register
684 */
685
686 #define CFGA_PMHCTG 0x08
687 #define CFGA_GPIO1PD 0x04
688 #define CFGA_ABSHDN 0x02
689 #define CFGA_PACPI 0x01
690
691 /*
692 * Bits in the CFGB register
693 */
694
695 #define CFGB_GTCKOPT 0x80
696 #define CFGB_MIIOPT 0x40
697 #define CFGB_CRSEOPT 0x20
698 #define CFGB_OFSET 0x10
699 #define CFGB_CRANDOM 0x08
700 #define CFGB_CAP 0x04
701 #define CFGB_MBA 0x02
702 #define CFGB_BAKOPT 0x01
703
704 /*
705 * Bits in the CFGC register
706 */
707
708 #define CFGC_EELOAD 0x80
709 #define CFGC_BROPT 0x40
710 #define CFGC_DLYEN 0x20
711 #define CFGC_DTSEL 0x10
712 #define CFGC_BTSEL 0x08
713 #define CFGC_BPS2 0x04 /* bootrom select[2] */
714 #define CFGC_BPS1 0x02 /* bootrom select[1] */
715 #define CFGC_BPS0 0x01 /* bootrom select[0] */
716
717 /*
718 * Bits in the CFGD register
719 */
720
721 #define CFGD_IODIS 0x80
722 #define CFGD_MSLVDACEN 0x40
723 #define CFGD_CFGDACEN 0x20
724 #define CFGD_PCI64EN 0x10
725 #define CFGD_HTMRL4 0x08
726
727 /*
728 * Bits in the DCFG1 register
729 */
730
731 #define DCFG_XMWI 0x8000
732 #define DCFG_XMRM 0x4000
733 #define DCFG_XMRL 0x2000
734 #define DCFG_PERDIS 0x1000
735 #define DCFG_MRWAIT 0x0400
736 #define DCFG_MWWAIT 0x0200
737 #define DCFG_LATMEN 0x0100
738
739 /*
740 * Bits in the MCFG0 register
741 */
742
743 #define MCFG_RXARB 0x0080
744 #define MCFG_RFT1 0x0020
745 #define MCFG_RFT0 0x0010
746 #define MCFG_LOWTHOPT 0x0008
747 #define MCFG_PQEN 0x0004
748 #define MCFG_RTGOPT 0x0002
749 #define MCFG_VIDFR 0x0001
750
751 /*
752 * Bits in the MCFG1 register
753 */
754
755 #define MCFG_TXARB 0x8000
756 #define MCFG_TXQBK1 0x0800
757 #define MCFG_TXQBK0 0x0400
758 #define MCFG_TXQNOBK 0x0200
759 #define MCFG_SNAPOPT 0x0100
760
761 /*
762 * Bits in the PMCC register
763 */
764
765 #define PMCC_DSI 0x80
766 #define PMCC_D2_DIS 0x40
767 #define PMCC_D1_DIS 0x20
768 #define PMCC_D3C_EN 0x10
769 #define PMCC_D3H_EN 0x08
770 #define PMCC_D2_EN 0x04
771 #define PMCC_D1_EN 0x02
772 #define PMCC_D0_EN 0x01
773
774 /*
775 * Bits in STICKHW
776 */
777
778 #define STICKHW_SWPTAG 0x10
779 #define STICKHW_WOLSR 0x08
780 #define STICKHW_WOLEN 0x04
781 #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */
782 #define STICKHW_DS0 0x01 /* suspend well DS write port */
783
784 /*
785 * Bits in the MIBCR register
786 */
787
788 #define MIBCR_MIBISTOK 0x80
789 #define MIBCR_MIBISTGO 0x40
790 #define MIBCR_MIBINC 0x20
791 #define MIBCR_MIBHI 0x10
792 #define MIBCR_MIBFRZ 0x08
793 #define MIBCR_MIBFLSH 0x04
794 #define MIBCR_MPTRINI 0x02
795 #define MIBCR_MIBCLR 0x01
796
797 /*
798 * Bits in the EERSV register
799 */
800
801 #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */
802
803 #define EERSV_BOOT_MASK ((u8) 0x06)
804 #define EERSV_BOOT_INT19 ((u8) 0x00)
805 #define EERSV_BOOT_INT18 ((u8) 0x02)
806 #define EERSV_BOOT_LOCAL ((u8) 0x04)
807 #define EERSV_BOOT_BEV ((u8) 0x06)
808
809
810 /*
811 * Bits in BPCMD
812 */
813
814 #define BPCMD_BPDNE 0x80
815 #define BPCMD_EBPWR 0x02
816 #define BPCMD_EBPRD 0x01
817
818 /*
819 * Bits in the EECSR register
820 */
821
822 #define EECSR_EMBP 0x40 /* eeprom embeded programming */
823 #define EECSR_RELOAD 0x20 /* eeprom content reload */
824 #define EECSR_DPM 0x10 /* eeprom direct programming */
825 #define EECSR_ECS 0x08 /* eeprom CS pin */
826 #define EECSR_ECK 0x04 /* eeprom CK pin */
827 #define EECSR_EDI 0x02 /* eeprom DI pin */
828 #define EECSR_EDO 0x01 /* eeprom DO pin */
829
830 /*
831 * Bits in the EMBCMD register
832 */
833
834 #define EMBCMD_EDONE 0x80
835 #define EMBCMD_EWDIS 0x08
836 #define EMBCMD_EWEN 0x04
837 #define EMBCMD_EWR 0x02
838 #define EMBCMD_ERD 0x01
839
840 /*
841 * Bits in TESTCFG register
842 */
843
844 #define TESTCFG_HBDIS 0x80
845
846 /*
847 * Bits in CHIPGCR register
848 */
849
850 #define CHIPGCR_FCGMII 0x80
851 #define CHIPGCR_FCFDX 0x40
852 #define CHIPGCR_FCRESV 0x20
853 #define CHIPGCR_FCMODE 0x10
854 #define CHIPGCR_LPSOPT 0x08
855 #define CHIPGCR_TM1US 0x04
856 #define CHIPGCR_TM0US 0x02
857 #define CHIPGCR_PHYINTEN 0x01
858
859 /*
860 * Bits in WOLCR0
861 */
862
863 #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */
864 #define WOLCR_MSWOLEN6 0x0040
865 #define WOLCR_MSWOLEN5 0x0020
866 #define WOLCR_MSWOLEN4 0x0010
867 #define WOLCR_MSWOLEN3 0x0008
868 #define WOLCR_MSWOLEN2 0x0004
869 #define WOLCR_MSWOLEN1 0x0002
870 #define WOLCR_MSWOLEN0 0x0001
871 #define WOLCR_ARP_EN 0x0001
872
873 /*
874 * Bits in WOLCR1
875 */
876
877 #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */
878 #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */
879 #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */
880 #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */
881
882
883 /*
884 * Bits in PWCFG
885 */
886
887 #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */
888 #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */
889 #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */
890 #define PWCFG_LEGCY_WOL 0x10
891 #define PWCFG_PMCSR_PME_SR 0x08
892 #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */
893 #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */
894 #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */
895
896 /*
897 * Bits in WOLCFG
898 */
899
900 #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */
901 #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */
902 #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */
903 #define WOLCFG_SMIIACC 0x08 /* ?? */
904 #define WOLCFG_SGENWH 0x02
905 #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII
906 to report status change */
907 /*
908 * Bits in WOLSR1
909 */
910
911 #define WOLSR_LINKOFF_INT 0x0800
912 #define WOLSR_LINKON_INT 0x0400
913 #define WOLSR_MAGIC_INT 0x0200
914 #define WOLSR_UNICAST_INT 0x0100
915
916 /*
917 * Ethernet address filter type
918 */
919
920 #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */
921 #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */
922 #define PKT_TYPE_MULTICAST 0x0002
923 #define PKT_TYPE_ALL_MULTICAST 0x0004
924 #define PKT_TYPE_BROADCAST 0x0008
925 #define PKT_TYPE_PROMISCUOUS 0x0020
926 #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */
927 #define PKT_TYPE_RUNT 0x4000
928 #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */
929
930 /*
931 * Loopback mode
932 */
933
934 #define MAC_LB_NONE 0x00
935 #define MAC_LB_INTERNAL 0x01
936 #define MAC_LB_EXTERNAL 0x02
937
938 /*
939 * Enabled mask value of irq
940 */
941
942 #if defined(_SIM)
943 #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR
944 set IMR0 to 0x0F according to spec */
945
946 #else
947 #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR
948 ignore MIBFI,RACEI to
949 reduce intr. frequency
950 NOTE.... do not enable NoBuf int mask at driver driver
951 when (1) NoBuf -> RxThreshold = SF
952 (2) OK -> RxThreshold = original value
953 */
954 #endif
955
956 /*
957 * Revision id
958 */
959
960 #define REV_ID_VT3119_A0 0x00
961 #define REV_ID_VT3119_A1 0x01
962 #define REV_ID_VT3216_A0 0x10
963
964 /*
965 * Max time out delay time
966 */
967
968 #define W_MAX_TIMEOUT 0x0FFFU
969
970
971 /*
972 * MAC registers as a structure. Cannot be directly accessed this
973 * way but generates offsets for readl/writel() calls
974 */
975
976 struct mac_regs {
977 volatile u8 PAR[6]; /* 0x00 */
978 volatile u8 RCR;
979 volatile u8 TCR;
980
981 volatile __le32 CR0Set; /* 0x08 */
982 volatile __le32 CR0Clr; /* 0x0C */
983
984 volatile u8 MARCAM[8]; /* 0x10 */
985
986 volatile __le32 DecBaseHi; /* 0x18 */
987 volatile __le16 DbfBaseHi; /* 0x1C */
988 volatile __le16 reserved_1E;
989
990 volatile __le16 ISRCTL; /* 0x20 */
991 volatile u8 TXESR;
992 volatile u8 RXESR;
993
994 volatile __le32 ISR; /* 0x24 */
995 volatile __le32 IMR;
996
997 volatile __le32 TDStatusPort; /* 0x2C */
998
999 volatile __le16 TDCSRSet; /* 0x30 */
1000 volatile u8 RDCSRSet;
1001 volatile u8 reserved_33;
1002 volatile __le16 TDCSRClr;
1003 volatile u8 RDCSRClr;
1004 volatile u8 reserved_37;
1005
1006 volatile __le32 RDBaseLo; /* 0x38 */
1007 volatile __le16 RDIdx; /* 0x3C */
1008 volatile __le16 reserved_3E;
1009
1010 volatile __le32 TDBaseLo[4]; /* 0x40 */
1011
1012 volatile __le16 RDCSize; /* 0x50 */
1013 volatile __le16 TDCSize; /* 0x52 */
1014 volatile __le16 TDIdx[4]; /* 0x54 */
1015 volatile __le16 tx_pause_timer; /* 0x5C */
1016 volatile __le16 RBRDU; /* 0x5E */
1017
1018 volatile __le32 FIFOTest0; /* 0x60 */
1019 volatile __le32 FIFOTest1; /* 0x64 */
1020
1021 volatile u8 CAMADDR; /* 0x68 */
1022 volatile u8 CAMCR; /* 0x69 */
1023 volatile u8 GFTEST; /* 0x6A */
1024 volatile u8 FTSTCMD; /* 0x6B */
1025
1026 volatile u8 MIICFG; /* 0x6C */
1027 volatile u8 MIISR;
1028 volatile u8 PHYSR0;
1029 volatile u8 PHYSR1;
1030 volatile u8 MIICR;
1031 volatile u8 MIIADR;
1032 volatile __le16 MIIDATA;
1033
1034 volatile __le16 SoftTimer0; /* 0x74 */
1035 volatile __le16 SoftTimer1;
1036
1037 volatile u8 CFGA; /* 0x78 */
1038 volatile u8 CFGB;
1039 volatile u8 CFGC;
1040 volatile u8 CFGD;
1041
1042 volatile __le16 DCFG; /* 0x7C */
1043 volatile __le16 MCFG;
1044
1045 volatile u8 TBIST; /* 0x80 */
1046 volatile u8 RBIST;
1047 volatile u8 PMCPORT;
1048 volatile u8 STICKHW;
1049
1050 volatile u8 MIBCR; /* 0x84 */
1051 volatile u8 reserved_85;
1052 volatile u8 rev_id;
1053 volatile u8 PORSTS;
1054
1055 volatile __le32 MIBData; /* 0x88 */
1056
1057 volatile __le16 EEWrData;
1058
1059 volatile u8 reserved_8E;
1060 volatile u8 BPMDWr;
1061 volatile u8 BPCMD;
1062 volatile u8 BPMDRd;
1063
1064 volatile u8 EECHKSUM; /* 0x92 */
1065 volatile u8 EECSR;
1066
1067 volatile __le16 EERdData; /* 0x94 */
1068 volatile u8 EADDR;
1069 volatile u8 EMBCMD;
1070
1071
1072 volatile u8 JMPSR0; /* 0x98 */
1073 volatile u8 JMPSR1;
1074 volatile u8 JMPSR2;
1075 volatile u8 JMPSR3;
1076 volatile u8 CHIPGSR; /* 0x9C */
1077 volatile u8 TESTCFG;
1078 volatile u8 DEBUG;
1079 volatile u8 CHIPGCR;
1080
1081 volatile __le16 WOLCRSet; /* 0xA0 */
1082 volatile u8 PWCFGSet;
1083 volatile u8 WOLCFGSet;
1084
1085 volatile __le16 WOLCRClr; /* 0xA4 */
1086 volatile u8 PWCFGCLR;
1087 volatile u8 WOLCFGClr;
1088
1089 volatile __le16 WOLSRSet; /* 0xA8 */
1090 volatile __le16 reserved_AA;
1091
1092 volatile __le16 WOLSRClr; /* 0xAC */
1093 volatile __le16 reserved_AE;
1094
1095 volatile __le16 PatternCRC[8]; /* 0xB0 */
1096 volatile __le32 ByteMask[4][4]; /* 0xC0 */
1097 } __attribute__ ((__packed__));
1098
1099
1100 enum hw_mib {
1101 HW_MIB_ifRxAllPkts = 0,
1102 HW_MIB_ifRxOkPkts,
1103 HW_MIB_ifTxOkPkts,
1104 HW_MIB_ifRxErrorPkts,
1105 HW_MIB_ifRxRuntOkPkt,
1106 HW_MIB_ifRxRuntErrPkt,
1107 HW_MIB_ifRx64Pkts,
1108 HW_MIB_ifTx64Pkts,
1109 HW_MIB_ifRx65To127Pkts,
1110 HW_MIB_ifTx65To127Pkts,
1111 HW_MIB_ifRx128To255Pkts,
1112 HW_MIB_ifTx128To255Pkts,
1113 HW_MIB_ifRx256To511Pkts,
1114 HW_MIB_ifTx256To511Pkts,
1115 HW_MIB_ifRx512To1023Pkts,
1116 HW_MIB_ifTx512To1023Pkts,
1117 HW_MIB_ifRx1024To1518Pkts,
1118 HW_MIB_ifTx1024To1518Pkts,
1119 HW_MIB_ifTxEtherCollisions,
1120 HW_MIB_ifRxPktCRCE,
1121 HW_MIB_ifRxJumboPkts,
1122 HW_MIB_ifTxJumboPkts,
1123 HW_MIB_ifRxMacControlFrames,
1124 HW_MIB_ifTxMacControlFrames,
1125 HW_MIB_ifRxPktFAE,
1126 HW_MIB_ifRxLongOkPkt,
1127 HW_MIB_ifRxLongPktErrPkt,
1128 HW_MIB_ifTXSQEErrors,
1129 HW_MIB_ifRxNobuf,
1130 HW_MIB_ifRxSymbolErrors,
1131 HW_MIB_ifInRangeLengthErrors,
1132 HW_MIB_ifLateCollisions,
1133 HW_MIB_SIZE
1134 };
1135
1136 enum chip_type {
1137 CHIP_TYPE_VT6110 = 1,
1138 };
1139
1140 struct velocity_info_tbl {
1141 enum chip_type chip_id;
1142 const char *name;
1143 int txqueue;
1144 u32 flags;
1145 };
1146
1147 #define mac_hw_mibs_init(regs) {\
1148 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1149 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
1150 do {}\
1151 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
1152 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1153 }
1154
1155 #define mac_read_isr(regs) readl(&((regs)->ISR))
1156 #define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
1157 #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
1158
1159 #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
1160 #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
1161 #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
1162
1163 #define mac_set_dma_length(regs, n) {\
1164 BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
1165 }
1166
1167 #define mac_set_rx_thresh(regs, n) {\
1168 BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
1169 }
1170
1171 #define mac_rx_queue_run(regs) {\
1172 writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
1173 }
1174
1175 #define mac_rx_queue_wake(regs) {\
1176 writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
1177 }
1178
1179 #define mac_tx_queue_run(regs, n) {\
1180 writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
1181 }
1182
1183 #define mac_tx_queue_wake(regs, n) {\
1184 writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
1185 }
1186
mac_eeprom_reload(struct mac_regs __iomem * regs)1187 static inline void mac_eeprom_reload(struct mac_regs __iomem * regs) {
1188 int i=0;
1189
1190 BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR));
1191 do {
1192 udelay(10);
1193 if (i++>0x1000)
1194 break;
1195 } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR)));
1196 }
1197
1198 /*
1199 * Header for WOL definitions. Used to compute hashes
1200 */
1201
1202 typedef u8 MCAM_ADDR[ETH_ALEN];
1203
1204 struct arp_packet {
1205 u8 dest_mac[ETH_ALEN];
1206 u8 src_mac[ETH_ALEN];
1207 __be16 type;
1208 __be16 ar_hrd;
1209 __be16 ar_pro;
1210 u8 ar_hln;
1211 u8 ar_pln;
1212 __be16 ar_op;
1213 u8 ar_sha[ETH_ALEN];
1214 u8 ar_sip[4];
1215 u8 ar_tha[ETH_ALEN];
1216 u8 ar_tip[4];
1217 } __attribute__ ((__packed__));
1218
1219 struct _magic_packet {
1220 u8 dest_mac[6];
1221 u8 src_mac[6];
1222 __be16 type;
1223 u8 MAC[16][6];
1224 u8 password[6];
1225 } __attribute__ ((__packed__));
1226
1227 /*
1228 * Store for chip context when saving and restoring status. Not
1229 * all fields are saved/restored currently.
1230 */
1231
1232 struct velocity_context {
1233 u8 mac_reg[256];
1234 MCAM_ADDR cam_addr[MCAM_SIZE];
1235 u16 vcam[VCAM_SIZE];
1236 u32 cammask[2];
1237 u32 patcrc[2];
1238 u32 pattern[8];
1239 };
1240
1241
1242 /*
1243 * MII registers.
1244 */
1245
1246
1247 /*
1248 * Registers in the MII (offset unit is WORD)
1249 */
1250
1251 #define MII_REG_BMCR 0x00 // physical address
1252 #define MII_REG_BMSR 0x01 //
1253 #define MII_REG_PHYID1 0x02 // OUI
1254 #define MII_REG_PHYID2 0x03 // OUI + Module ID + REV ID
1255 #define MII_REG_ANAR 0x04 //
1256 #define MII_REG_ANLPAR 0x05 //
1257 #define MII_REG_G1000CR 0x09 //
1258 #define MII_REG_G1000SR 0x0A //
1259 #define MII_REG_MODCFG 0x10 //
1260 #define MII_REG_TCSR 0x16 //
1261 #define MII_REG_PLED 0x1B //
1262 // NS, MYSON only
1263 #define MII_REG_PCR 0x17 //
1264 // ESI only
1265 #define MII_REG_PCSR 0x17 //
1266 #define MII_REG_AUXCR 0x1C //
1267
1268 // Marvell 88E1000/88E1000S
1269 #define MII_REG_PSCR 0x10 // PHY specific control register
1270
1271 //
1272 // Bits in the BMCR register
1273 //
1274 #define BMCR_RESET 0x8000 //
1275 #define BMCR_LBK 0x4000 //
1276 #define BMCR_SPEED100 0x2000 //
1277 #define BMCR_AUTO 0x1000 //
1278 #define BMCR_PD 0x0800 //
1279 #define BMCR_ISO 0x0400 //
1280 #define BMCR_REAUTO 0x0200 //
1281 #define BMCR_FDX 0x0100 //
1282 #define BMCR_SPEED1G 0x0040 //
1283 //
1284 // Bits in the BMSR register
1285 //
1286 #define BMSR_AUTOCM 0x0020 //
1287 #define BMSR_LNK 0x0004 //
1288
1289 //
1290 // Bits in the ANAR register
1291 //
1292 #define ANAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1293 #define ANAR_PAUSE 0x0400 // Symmetric PAUSE Support
1294 #define ANAR_T4 0x0200 //
1295 #define ANAR_TXFD 0x0100 //
1296 #define ANAR_TX 0x0080 //
1297 #define ANAR_10FD 0x0040 //
1298 #define ANAR_10 0x0020 //
1299 //
1300 // Bits in the ANLPAR register
1301 //
1302 #define ANLPAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1303 #define ANLPAR_PAUSE 0x0400 // Symmetric PAUSE Support
1304 #define ANLPAR_T4 0x0200 //
1305 #define ANLPAR_TXFD 0x0100 //
1306 #define ANLPAR_TX 0x0080 //
1307 #define ANLPAR_10FD 0x0040 //
1308 #define ANLPAR_10 0x0020 //
1309
1310 //
1311 // Bits in the G1000CR register
1312 //
1313 #define G1000CR_1000FD 0x0200 // PHY is 1000-T Full-duplex capable
1314 #define G1000CR_1000 0x0100 // PHY is 1000-T Half-duplex capable
1315
1316 //
1317 // Bits in the G1000SR register
1318 //
1319 #define G1000SR_1000FD 0x0800 // LP PHY is 1000-T Full-duplex capable
1320 #define G1000SR_1000 0x0400 // LP PHY is 1000-T Half-duplex capable
1321
1322 #define TCSR_ECHODIS 0x2000 //
1323 #define AUXCR_MDPPS 0x0004 //
1324
1325 // Bits in the PLED register
1326 #define PLED_LALBE 0x0004 //
1327
1328 // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
1329 #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit
1330
1331 #define PHYID_CICADA_CS8201 0x000FC410UL
1332 #define PHYID_VT3216_32BIT 0x000FC610UL
1333 #define PHYID_VT3216_64BIT 0x000FC600UL
1334 #define PHYID_MARVELL_1000 0x01410C50UL
1335 #define PHYID_MARVELL_1000S 0x01410C40UL
1336
1337 #define PHYID_REV_ID_MASK 0x0000000FUL
1338
1339 #define PHYID_GET_PHY_REV_ID(i) ((i) & PHYID_REV_ID_MASK)
1340 #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK)
1341
1342 #define MII_REG_BITS_ON(x,i,p) do {\
1343 u16 w;\
1344 velocity_mii_read((p),(i),&(w));\
1345 (w)|=(x);\
1346 velocity_mii_write((p),(i),(w));\
1347 } while (0)
1348
1349 #define MII_REG_BITS_OFF(x,i,p) do {\
1350 u16 w;\
1351 velocity_mii_read((p),(i),&(w));\
1352 (w)&=(~(x));\
1353 velocity_mii_write((p),(i),(w));\
1354 } while (0)
1355
1356 #define MII_REG_BITS_IS_ON(x,i,p) ({\
1357 u16 w;\
1358 velocity_mii_read((p),(i),&(w));\
1359 ((int) ((w) & (x)));})
1360
1361 #define MII_GET_PHY_ID(p) ({\
1362 u32 id;\
1363 velocity_mii_read((p),MII_REG_PHYID2,(u16 *) &id);\
1364 velocity_mii_read((p),MII_REG_PHYID1,((u16 *) &id)+1);\
1365 (id);})
1366
1367 /*
1368 * Inline debug routine
1369 */
1370
1371
1372 enum velocity_msg_level {
1373 MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation.
1374 MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified.
1375 MSG_LEVEL_INFO = 2, //Normal message.
1376 MSG_LEVEL_VERBOSE = 3, //Will report all trival errors.
1377 MSG_LEVEL_DEBUG = 4 //Only for debug purpose.
1378 };
1379
1380 #ifdef VELOCITY_DEBUG
1381 #define ASSERT(x) { \
1382 if (!(x)) { \
1383 printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
1384 __func__, __LINE__);\
1385 BUG(); \
1386 }\
1387 }
1388 #define VELOCITY_DBG(p,args...) printk(p, ##args)
1389 #else
1390 #define ASSERT(x)
1391 #define VELOCITY_DBG(x)
1392 #endif
1393
1394 #define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printk( p ,##args);} while (0)
1395
1396 #define VELOCITY_PRT_CAMMASK(p,t) {\
1397 int i;\
1398 if ((t)==VELOCITY_MULTICAST_CAM) {\
1399 for (i=0;i<(MCAM_SIZE/8);i++)\
1400 printk("%02X",(p)->mCAMmask[i]);\
1401 }\
1402 else {\
1403 for (i=0;i<(VCAM_SIZE/8);i++)\
1404 printk("%02X",(p)->vCAMmask[i]);\
1405 }\
1406 printk("\n");\
1407 }
1408
1409
1410
1411 #define VELOCITY_WOL_MAGIC 0x00000000UL
1412 #define VELOCITY_WOL_PHY 0x00000001UL
1413 #define VELOCITY_WOL_ARP 0x00000002UL
1414 #define VELOCITY_WOL_UCAST 0x00000004UL
1415 #define VELOCITY_WOL_BCAST 0x00000010UL
1416 #define VELOCITY_WOL_MCAST 0x00000020UL
1417 #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL
1418
1419 /*
1420 * Flags for options
1421 */
1422
1423 #define VELOCITY_FLAGS_TAGGING 0x00000001UL
1424 #define VELOCITY_FLAGS_TX_CSUM 0x00000002UL
1425 #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL
1426 #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL
1427 #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL
1428
1429 #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL
1430
1431 /*
1432 * Flags for driver status
1433 */
1434
1435 #define VELOCITY_FLAGS_OPENED 0x00010000UL
1436 #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL
1437 #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL
1438 #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL
1439
1440 /*
1441 * Flags for MII status
1442 */
1443
1444 #define VELOCITY_LINK_FAIL 0x00000001UL
1445 #define VELOCITY_SPEED_10 0x00000002UL
1446 #define VELOCITY_SPEED_100 0x00000004UL
1447 #define VELOCITY_SPEED_1000 0x00000008UL
1448 #define VELOCITY_DUPLEX_FULL 0x00000010UL
1449 #define VELOCITY_AUTONEG_ENABLE 0x00000020UL
1450 #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL
1451
1452 /*
1453 * For velocity_set_media_duplex
1454 */
1455
1456 #define VELOCITY_LINK_CHANGE 0x00000001UL
1457
1458 enum speed_opt {
1459 SPD_DPX_AUTO = 0,
1460 SPD_DPX_100_HALF = 1,
1461 SPD_DPX_100_FULL = 2,
1462 SPD_DPX_10_HALF = 3,
1463 SPD_DPX_10_FULL = 4
1464 };
1465
1466 enum velocity_init_type {
1467 VELOCITY_INIT_COLD = 0,
1468 VELOCITY_INIT_RESET,
1469 VELOCITY_INIT_WOL
1470 };
1471
1472 enum velocity_flow_cntl_type {
1473 FLOW_CNTL_DEFAULT = 1,
1474 FLOW_CNTL_TX,
1475 FLOW_CNTL_RX,
1476 FLOW_CNTL_TX_RX,
1477 FLOW_CNTL_DISABLE,
1478 };
1479
1480 struct velocity_opt {
1481 int numrx; /* Number of RX descriptors */
1482 int numtx; /* Number of TX descriptors */
1483 enum speed_opt spd_dpx; /* Media link mode */
1484
1485 int DMA_length; /* DMA length */
1486 int rx_thresh; /* RX_THRESH */
1487 int flow_cntl;
1488 int wol_opts; /* Wake on lan options */
1489 int td_int_count;
1490 int int_works;
1491 int rx_bandwidth_hi;
1492 int rx_bandwidth_lo;
1493 int rx_bandwidth_en;
1494 u32 flags;
1495 };
1496
1497 #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->tx.used[(q)]))
1498
1499 #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx])
1500
1501 struct velocity_info {
1502 struct list_head list;
1503
1504 struct pci_dev *pdev;
1505 struct net_device *dev;
1506 struct net_device_stats stats;
1507
1508 struct vlan_group *vlgrp;
1509 u8 ip_addr[4];
1510 enum chip_type chip_id;
1511
1512 struct mac_regs __iomem * mac_regs;
1513 unsigned long memaddr;
1514 unsigned long ioaddr;
1515
1516 struct tx_info {
1517 int numq;
1518
1519 /* FIXME: the locality of the data seems rather poor. */
1520 int used[TX_QUEUE_NO];
1521 int curr[TX_QUEUE_NO];
1522 int tail[TX_QUEUE_NO];
1523 struct tx_desc *rings[TX_QUEUE_NO];
1524 struct velocity_td_info *infos[TX_QUEUE_NO];
1525 dma_addr_t pool_dma[TX_QUEUE_NO];
1526 } tx;
1527
1528 struct rx_info {
1529 int buf_sz;
1530
1531 int dirty;
1532 int curr;
1533 u32 filled;
1534 struct rx_desc *ring;
1535 struct velocity_rd_info *info; /* It's an array */
1536 dma_addr_t pool_dma;
1537 } rx;
1538
1539 u32 mib_counter[MAX_HW_MIB_COUNTER];
1540 struct velocity_opt options;
1541
1542 u32 int_mask;
1543
1544 u32 flags;
1545
1546 u32 mii_status;
1547 u32 phy_id;
1548 int multicast_limit;
1549
1550 u8 vCAMmask[(VCAM_SIZE / 8)];
1551 u8 mCAMmask[(MCAM_SIZE / 8)];
1552
1553 spinlock_t lock;
1554
1555 int wol_opts;
1556 u8 wol_passwd[6];
1557
1558 struct velocity_context context;
1559
1560 u32 ticks;
1561
1562 u8 rev_id;
1563 };
1564
1565 /**
1566 * velocity_get_ip - find an IP address for the device
1567 * @vptr: Velocity to query
1568 *
1569 * Dig out an IP address for this interface so that we can
1570 * configure wakeup with WOL for ARP. If there are multiple IP
1571 * addresses on this chain then we use the first - multi-IP WOL is not
1572 * supported.
1573 *
1574 * CHECK ME: locking
1575 */
1576
velocity_get_ip(struct velocity_info * vptr)1577 static inline int velocity_get_ip(struct velocity_info *vptr)
1578 {
1579 struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr;
1580 struct in_ifaddr *ifa;
1581
1582 if (in_dev != NULL) {
1583 ifa = (struct in_ifaddr *) in_dev->ifa_list;
1584 if (ifa != NULL) {
1585 memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
1586 return 0;
1587 }
1588 }
1589 return -ENOENT;
1590 }
1591
1592 /**
1593 * velocity_update_hw_mibs - fetch MIB counters from chip
1594 * @vptr: velocity to update
1595 *
1596 * The velocity hardware keeps certain counters in the hardware
1597 * side. We need to read these when the user asks for statistics
1598 * or when they overflow (causing an interrupt). The read of the
1599 * statistic clears it, so we keep running master counters in user
1600 * space.
1601 */
1602
velocity_update_hw_mibs(struct velocity_info * vptr)1603 static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
1604 {
1605 u32 tmp;
1606 int i;
1607 BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
1608
1609 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
1610
1611 BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
1612 for (i = 0; i < HW_MIB_SIZE; i++) {
1613 tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
1614 vptr->mib_counter[i] += tmp;
1615 }
1616 }
1617
1618 /**
1619 * init_flow_control_register - set up flow control
1620 * @vptr: velocity to configure
1621 *
1622 * Configure the flow control registers for this velocity device.
1623 */
1624
init_flow_control_register(struct velocity_info * vptr)1625 static inline void init_flow_control_register(struct velocity_info *vptr)
1626 {
1627 struct mac_regs __iomem * regs = vptr->mac_regs;
1628
1629 /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
1630 depend on RD=64, and Turn on XNOEN in FlowCR1 */
1631 writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), ®s->CR0Set);
1632 writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), ®s->CR0Clr);
1633
1634 /* Set TxPauseTimer to 0xFFFF */
1635 writew(0xFFFF, ®s->tx_pause_timer);
1636
1637 /* Initialize RBRDU to Rx buffer count. */
1638 writew(vptr->options.numrx, ®s->RBRDU);
1639 }
1640
1641
1642 #endif
1643