1 /* 2 * File: include/asm-blackfin/mach-bf548/defBF54x_base.h 3 * Based on: 4 * Author: 5 * 6 * Created: 7 * Description: 8 * 9 * Rev: 10 * 11 * Modified: 12 * 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2, or (at your option) 18 * any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; see the file COPYING. 27 * If not, write to the Free Software Foundation, 28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 */ 30 31 #ifndef _DEF_BF54X_H 32 #define _DEF_BF54X_H 33 34 35 /* ************************************************************** */ 36 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ 37 /* ************************************************************** */ 38 39 /* PLL Registers */ 40 41 #define PLL_CTL 0xffc00000 /* PLL Control Register */ 42 #define PLL_DIV 0xffc00004 /* PLL Divisor Register */ 43 #define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */ 44 #define PLL_STAT 0xffc0000c /* PLL Status Register */ 45 #define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */ 46 47 /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ 48 49 #define CHIPID 0xffc00014 50 /* CHIPID Masks */ 51 #define CHIPID_VERSION 0xF0000000 52 #define CHIPID_FAMILY 0x0FFFF000 53 #define CHIPID_MANUFACTURE 0x00000FFE 54 55 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ 56 57 #define SWRST 0xffc00100 /* Software Reset Register */ 58 #define SYSCR 0xffc00104 /* System Configuration register */ 59 60 /* SIC Registers */ 61 62 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ 63 #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ 64 #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ 65 #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */ 66 #define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */ 67 #define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */ 68 #define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */ 69 #define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */ 70 #define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */ 71 #define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */ 72 #define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */ 73 #define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */ 74 #define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */ 75 #define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */ 76 #define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */ 77 #define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */ 78 #define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */ 79 #define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */ 80 #define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */ 81 #define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */ 82 #define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */ 83 84 /* Watchdog Timer Registers */ 85 86 #define WDOG_CTL 0xffc00200 /* Watchdog Control Register */ 87 #define WDOG_CNT 0xffc00204 /* Watchdog Count Register */ 88 #define WDOG_STAT 0xffc00208 /* Watchdog Status Register */ 89 90 /* RTC Registers */ 91 92 #define RTC_STAT 0xffc00300 /* RTC Status Register */ 93 #define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */ 94 #define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */ 95 #define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */ 96 #define RTC_ALARM 0xffc00310 /* RTC Alarm Register */ 97 #define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */ 98 99 /* UART0 Registers */ 100 101 #define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */ 102 #define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */ 103 #define UART0_GCTL 0xffc00408 /* Global Control Register */ 104 #define UART0_LCR 0xffc0040c /* Line Control Register */ 105 #define UART0_MCR 0xffc00410 /* Modem Control Register */ 106 #define UART0_LSR 0xffc00414 /* Line Status Register */ 107 #define UART0_MSR 0xffc00418 /* Modem Status Register */ 108 #define UART0_SCR 0xffc0041c /* Scratch Register */ 109 #define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */ 110 #define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */ 111 #define UART0_THR 0xffc00428 /* Transmit Hold Register */ 112 #define UART0_RBR 0xffc0042c /* Receive Buffer Register */ 113 114 /* SPI0 Registers */ 115 116 #define SPI0_REGBASE 0xffc00500 117 #define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ 118 #define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ 119 #define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ 120 #define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */ 121 #define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */ 122 #define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */ 123 #define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */ 124 125 /* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */ 126 127 /* Two Wire Interface Registers (TWI0) */ 128 129 #define TWI0_REGBASE 0xffc00700 130 #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ 131 #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ 132 #define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ 133 #define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ 134 #define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ 135 #define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */ 136 #define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ 137 #define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ 138 #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ 139 #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ 140 #define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */ 141 #define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ 142 #define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ 143 #define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ 144 #define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */ 145 #define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */ 146 147 /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */ 148 149 /* SPORT1 Registers */ 150 151 #define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */ 152 #define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */ 153 #define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */ 154 #define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */ 155 #define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */ 156 #define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */ 157 #define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */ 158 #define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */ 159 #define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */ 160 #define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */ 161 #define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */ 162 #define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */ 163 #define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */ 164 #define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */ 165 #define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */ 166 #define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */ 167 #define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */ 168 #define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */ 169 #define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */ 170 #define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */ 171 #define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */ 172 #define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */ 173 174 /* Asynchronous Memory Control Registers */ 175 176 #define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */ 177 #define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */ 178 #define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */ 179 #define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */ 180 #define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */ 181 #define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */ 182 #define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */ 183 184 /* DDR Memory Control Registers */ 185 186 #define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */ 187 #define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */ 188 #define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */ 189 #define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */ 190 #define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */ 191 #define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */ 192 #define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */ 193 #define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */ 194 195 /* DDR BankRead and Write Count Registers */ 196 197 #define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */ 198 #define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */ 199 #define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */ 200 #define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */ 201 #define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */ 202 #define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */ 203 #define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */ 204 #define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */ 205 #define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */ 206 #define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */ 207 #define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */ 208 #define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */ 209 #define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */ 210 #define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */ 211 #define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */ 212 #define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */ 213 #define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */ 214 #define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */ 215 #define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */ 216 #define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */ 217 #define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */ 218 #define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */ 219 #define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */ 220 #define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */ 221 #define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */ 222 223 /* DMAC0 Registers */ 224 225 #define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */ 226 #define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */ 227 228 /* DMA Channel 0 Registers */ 229 230 #define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */ 231 #define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */ 232 #define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */ 233 #define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */ 234 #define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */ 235 #define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */ 236 #define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */ 237 #define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */ 238 #define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */ 239 #define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */ 240 #define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */ 241 #define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */ 242 #define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */ 243 244 /* DMA Channel 1 Registers */ 245 246 #define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */ 247 #define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */ 248 #define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */ 249 #define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */ 250 #define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */ 251 #define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */ 252 #define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */ 253 #define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */ 254 #define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */ 255 #define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */ 256 #define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */ 257 #define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */ 258 #define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */ 259 260 /* DMA Channel 2 Registers */ 261 262 #define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */ 263 #define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */ 264 #define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */ 265 #define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */ 266 #define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */ 267 #define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */ 268 #define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */ 269 #define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */ 270 #define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */ 271 #define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */ 272 #define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */ 273 #define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */ 274 #define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */ 275 276 /* DMA Channel 3 Registers */ 277 278 #define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */ 279 #define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */ 280 #define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */ 281 #define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */ 282 #define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */ 283 #define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */ 284 #define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */ 285 #define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */ 286 #define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */ 287 #define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */ 288 #define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */ 289 #define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */ 290 #define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */ 291 292 /* DMA Channel 4 Registers */ 293 294 #define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */ 295 #define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */ 296 #define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */ 297 #define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */ 298 #define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */ 299 #define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */ 300 #define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */ 301 #define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */ 302 #define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */ 303 #define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */ 304 #define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */ 305 #define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */ 306 #define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */ 307 308 /* DMA Channel 5 Registers */ 309 310 #define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */ 311 #define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */ 312 #define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */ 313 #define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */ 314 #define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */ 315 #define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */ 316 #define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */ 317 #define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */ 318 #define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */ 319 #define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */ 320 #define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */ 321 #define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */ 322 #define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */ 323 324 /* DMA Channel 6 Registers */ 325 326 #define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */ 327 #define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */ 328 #define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */ 329 #define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */ 330 #define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */ 331 #define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */ 332 #define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */ 333 #define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */ 334 #define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */ 335 #define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */ 336 #define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */ 337 #define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */ 338 #define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */ 339 340 /* DMA Channel 7 Registers */ 341 342 #define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */ 343 #define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */ 344 #define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */ 345 #define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */ 346 #define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */ 347 #define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */ 348 #define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */ 349 #define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */ 350 #define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */ 351 #define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */ 352 #define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */ 353 #define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */ 354 #define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */ 355 356 /* DMA Channel 8 Registers */ 357 358 #define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */ 359 #define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */ 360 #define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */ 361 #define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */ 362 #define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */ 363 #define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */ 364 #define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */ 365 #define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */ 366 #define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */ 367 #define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */ 368 #define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */ 369 #define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */ 370 #define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */ 371 372 /* DMA Channel 9 Registers */ 373 374 #define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */ 375 #define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */ 376 #define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */ 377 #define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */ 378 #define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */ 379 #define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */ 380 #define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */ 381 #define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */ 382 #define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */ 383 #define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */ 384 #define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */ 385 #define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */ 386 #define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */ 387 388 /* DMA Channel 10 Registers */ 389 390 #define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */ 391 #define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */ 392 #define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */ 393 #define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */ 394 #define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */ 395 #define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */ 396 #define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */ 397 #define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */ 398 #define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */ 399 #define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */ 400 #define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */ 401 #define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */ 402 #define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */ 403 404 /* DMA Channel 11 Registers */ 405 406 #define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */ 407 #define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */ 408 #define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */ 409 #define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */ 410 #define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */ 411 #define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */ 412 #define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */ 413 #define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */ 414 #define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */ 415 #define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */ 416 #define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */ 417 #define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */ 418 #define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */ 419 420 /* MDMA Stream 0 Registers */ 421 422 #define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ 423 #define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */ 424 #define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */ 425 #define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */ 426 #define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */ 427 #define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */ 428 #define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */ 429 #define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ 430 #define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */ 431 #define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */ 432 #define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */ 433 #define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */ 434 #define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */ 435 #define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ 436 #define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */ 437 #define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */ 438 #define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */ 439 #define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */ 440 #define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */ 441 #define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */ 442 #define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ 443 #define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */ 444 #define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */ 445 #define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */ 446 #define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */ 447 #define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */ 448 449 /* MDMA Stream 1 Registers */ 450 451 #define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ 452 #define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */ 453 #define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */ 454 #define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */ 455 #define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */ 456 #define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */ 457 #define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */ 458 #define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ 459 #define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */ 460 #define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */ 461 #define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */ 462 #define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */ 463 #define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */ 464 #define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ 465 #define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */ 466 #define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */ 467 #define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */ 468 #define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */ 469 #define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */ 470 #define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */ 471 #define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ 472 #define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */ 473 #define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */ 474 #define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */ 475 #define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */ 476 #define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */ 477 478 /* UART3 Registers */ 479 480 #define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */ 481 #define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */ 482 #define UART3_GCTL 0xffc03108 /* Global Control Register */ 483 #define UART3_LCR 0xffc0310c /* Line Control Register */ 484 #define UART3_MCR 0xffc03110 /* Modem Control Register */ 485 #define UART3_LSR 0xffc03114 /* Line Status Register */ 486 #define UART3_MSR 0xffc03118 /* Modem Status Register */ 487 #define UART3_SCR 0xffc0311c /* Scratch Register */ 488 #define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */ 489 #define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */ 490 #define UART3_THR 0xffc03128 /* Transmit Hold Register */ 491 #define UART3_RBR 0xffc0312c /* Receive Buffer Register */ 492 493 /* EPPI1 Registers */ 494 495 #define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */ 496 #define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */ 497 #define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */ 498 #define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */ 499 #define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */ 500 #define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */ 501 #define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */ 502 #define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */ 503 #define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */ 504 #define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ 505 #define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ 506 #define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ 507 #define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ 508 #define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */ 509 510 /* Port Interrupt 0 Registers (32-bit) */ 511 512 #define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */ 513 #define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */ 514 #define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */ 515 #define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */ 516 #define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */ 517 #define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */ 518 #define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */ 519 #define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */ 520 #define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */ 521 #define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */ 522 523 /* Port Interrupt 1 Registers (32-bit) */ 524 525 #define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */ 526 #define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */ 527 #define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */ 528 #define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */ 529 #define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */ 530 #define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */ 531 #define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */ 532 #define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */ 533 #define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */ 534 #define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */ 535 536 /* Port Interrupt 2 Registers (32-bit) */ 537 538 #define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */ 539 #define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */ 540 #define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */ 541 #define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */ 542 #define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */ 543 #define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */ 544 #define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */ 545 #define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */ 546 #define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */ 547 #define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */ 548 549 /* Port Interrupt 3 Registers (32-bit) */ 550 551 #define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */ 552 #define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */ 553 #define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */ 554 #define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */ 555 #define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */ 556 #define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */ 557 #define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */ 558 #define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */ 559 #define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */ 560 #define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */ 561 562 /* Port A Registers */ 563 564 #define PORTA_FER 0xffc014c0 /* Function Enable Register */ 565 #define PORTA 0xffc014c4 /* GPIO Data Register */ 566 #define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */ 567 #define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */ 568 #define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */ 569 #define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */ 570 #define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */ 571 #define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */ 572 573 /* Port B Registers */ 574 575 #define PORTB_FER 0xffc014e0 /* Function Enable Register */ 576 #define PORTB 0xffc014e4 /* GPIO Data Register */ 577 #define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */ 578 #define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */ 579 #define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */ 580 #define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */ 581 #define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */ 582 #define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */ 583 584 /* Port C Registers */ 585 586 #define PORTC_FER 0xffc01500 /* Function Enable Register */ 587 #define PORTC 0xffc01504 /* GPIO Data Register */ 588 #define PORTC_SET 0xffc01508 /* GPIO Data Set Register */ 589 #define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */ 590 #define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */ 591 #define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */ 592 #define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */ 593 #define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */ 594 595 /* Port D Registers */ 596 597 #define PORTD_FER 0xffc01520 /* Function Enable Register */ 598 #define PORTD 0xffc01524 /* GPIO Data Register */ 599 #define PORTD_SET 0xffc01528 /* GPIO Data Set Register */ 600 #define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */ 601 #define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */ 602 #define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */ 603 #define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */ 604 #define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */ 605 606 /* Port E Registers */ 607 608 #define PORTE_FER 0xffc01540 /* Function Enable Register */ 609 #define PORTE 0xffc01544 /* GPIO Data Register */ 610 #define PORTE_SET 0xffc01548 /* GPIO Data Set Register */ 611 #define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */ 612 #define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */ 613 #define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */ 614 #define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */ 615 #define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */ 616 617 /* Port F Registers */ 618 619 #define PORTF_FER 0xffc01560 /* Function Enable Register */ 620 #define PORTF 0xffc01564 /* GPIO Data Register */ 621 #define PORTF_SET 0xffc01568 /* GPIO Data Set Register */ 622 #define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */ 623 #define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */ 624 #define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */ 625 #define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */ 626 #define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */ 627 628 /* Port G Registers */ 629 630 #define PORTG_FER 0xffc01580 /* Function Enable Register */ 631 #define PORTG 0xffc01584 /* GPIO Data Register */ 632 #define PORTG_SET 0xffc01588 /* GPIO Data Set Register */ 633 #define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */ 634 #define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */ 635 #define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */ 636 #define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */ 637 #define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */ 638 639 /* Port H Registers */ 640 641 #define PORTH_FER 0xffc015a0 /* Function Enable Register */ 642 #define PORTH 0xffc015a4 /* GPIO Data Register */ 643 #define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */ 644 #define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */ 645 #define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */ 646 #define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */ 647 #define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */ 648 #define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */ 649 650 /* Port I Registers */ 651 652 #define PORTI_FER 0xffc015c0 /* Function Enable Register */ 653 #define PORTI 0xffc015c4 /* GPIO Data Register */ 654 #define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */ 655 #define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */ 656 #define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */ 657 #define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */ 658 #define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */ 659 #define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */ 660 661 /* Port J Registers */ 662 663 #define PORTJ_FER 0xffc015e0 /* Function Enable Register */ 664 #define PORTJ 0xffc015e4 /* GPIO Data Register */ 665 #define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */ 666 #define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */ 667 #define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */ 668 #define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */ 669 #define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */ 670 #define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */ 671 672 /* PWM Timer Registers */ 673 674 #define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */ 675 #define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */ 676 #define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */ 677 #define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */ 678 #define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */ 679 #define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */ 680 #define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */ 681 #define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */ 682 #define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */ 683 #define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */ 684 #define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */ 685 #define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */ 686 #define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */ 687 #define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */ 688 #define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */ 689 #define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */ 690 #define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */ 691 #define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */ 692 #define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */ 693 #define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */ 694 #define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */ 695 #define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */ 696 #define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */ 697 #define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */ 698 #define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */ 699 #define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */ 700 #define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */ 701 #define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */ 702 #define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */ 703 #define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */ 704 #define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */ 705 #define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */ 706 707 /* Timer Group of 8 */ 708 709 #define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */ 710 #define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */ 711 #define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */ 712 713 /* DMAC1 Registers */ 714 715 #define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ 716 #define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */ 717 718 /* DMA Channel 12 Registers */ 719 720 #define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */ 721 #define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */ 722 #define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */ 723 #define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */ 724 #define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */ 725 #define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */ 726 #define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */ 727 #define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */ 728 #define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */ 729 #define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */ 730 #define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */ 731 #define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */ 732 #define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */ 733 734 /* DMA Channel 13 Registers */ 735 736 #define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */ 737 #define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */ 738 #define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */ 739 #define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */ 740 #define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */ 741 #define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */ 742 #define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */ 743 #define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */ 744 #define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */ 745 #define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */ 746 #define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */ 747 #define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */ 748 #define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */ 749 750 /* DMA Channel 14 Registers */ 751 752 #define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */ 753 #define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */ 754 #define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */ 755 #define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */ 756 #define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */ 757 #define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */ 758 #define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */ 759 #define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */ 760 #define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */ 761 #define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */ 762 #define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */ 763 #define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */ 764 #define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */ 765 766 /* DMA Channel 15 Registers */ 767 768 #define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */ 769 #define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */ 770 #define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */ 771 #define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */ 772 #define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */ 773 #define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */ 774 #define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */ 775 #define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */ 776 #define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */ 777 #define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */ 778 #define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */ 779 #define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */ 780 #define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */ 781 782 /* DMA Channel 16 Registers */ 783 784 #define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */ 785 #define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */ 786 #define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */ 787 #define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */ 788 #define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */ 789 #define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */ 790 #define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */ 791 #define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */ 792 #define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */ 793 #define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */ 794 #define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */ 795 #define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */ 796 #define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */ 797 798 /* DMA Channel 17 Registers */ 799 800 #define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */ 801 #define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */ 802 #define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */ 803 #define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */ 804 #define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */ 805 #define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */ 806 #define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */ 807 #define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */ 808 #define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */ 809 #define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */ 810 #define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */ 811 #define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */ 812 #define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */ 813 814 /* DMA Channel 18 Registers */ 815 816 #define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */ 817 #define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */ 818 #define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */ 819 #define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */ 820 #define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */ 821 #define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */ 822 #define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */ 823 #define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */ 824 #define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */ 825 #define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */ 826 #define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */ 827 #define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */ 828 #define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */ 829 830 /* DMA Channel 19 Registers */ 831 832 #define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */ 833 #define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */ 834 #define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */ 835 #define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */ 836 #define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */ 837 #define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */ 838 #define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */ 839 #define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */ 840 #define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */ 841 #define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */ 842 #define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */ 843 #define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */ 844 #define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */ 845 846 /* DMA Channel 20 Registers */ 847 848 #define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */ 849 #define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */ 850 #define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */ 851 #define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */ 852 #define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */ 853 #define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */ 854 #define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */ 855 #define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */ 856 #define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */ 857 #define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */ 858 #define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */ 859 #define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */ 860 #define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */ 861 862 /* DMA Channel 21 Registers */ 863 864 #define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */ 865 #define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */ 866 #define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */ 867 #define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */ 868 #define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */ 869 #define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */ 870 #define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */ 871 #define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */ 872 #define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */ 873 #define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */ 874 #define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */ 875 #define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */ 876 #define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */ 877 878 /* DMA Channel 22 Registers */ 879 880 #define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */ 881 #define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */ 882 #define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */ 883 #define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */ 884 #define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */ 885 #define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */ 886 #define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */ 887 #define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */ 888 #define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */ 889 #define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */ 890 #define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */ 891 #define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */ 892 #define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */ 893 894 /* DMA Channel 23 Registers */ 895 896 #define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */ 897 #define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */ 898 #define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */ 899 #define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */ 900 #define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */ 901 #define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */ 902 #define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */ 903 #define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */ 904 #define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */ 905 #define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */ 906 #define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */ 907 #define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */ 908 #define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */ 909 910 /* MDMA Stream 2 Registers */ 911 912 #define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ 913 #define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */ 914 #define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */ 915 #define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */ 916 #define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */ 917 #define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */ 918 #define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */ 919 #define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ 920 #define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */ 921 #define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ 922 #define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */ 923 #define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */ 924 #define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */ 925 #define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ 926 #define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */ 927 #define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */ 928 #define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */ 929 #define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */ 930 #define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */ 931 #define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */ 932 #define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ 933 #define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */ 934 #define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */ 935 #define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */ 936 #define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */ 937 #define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */ 938 939 /* MDMA Stream 3 Registers */ 940 941 #define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ 942 #define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */ 943 #define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */ 944 #define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */ 945 #define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */ 946 #define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */ 947 #define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */ 948 #define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ 949 #define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */ 950 #define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */ 951 #define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */ 952 #define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */ 953 #define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */ 954 #define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ 955 #define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */ 956 #define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */ 957 #define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */ 958 #define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */ 959 #define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */ 960 #define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */ 961 #define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ 962 #define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */ 963 #define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */ 964 #define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */ 965 #define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */ 966 #define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */ 967 968 /* UART1 Registers */ 969 970 #define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */ 971 #define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */ 972 #define UART1_GCTL 0xffc02008 /* Global Control Register */ 973 #define UART1_LCR 0xffc0200c /* Line Control Register */ 974 #define UART1_MCR 0xffc02010 /* Modem Control Register */ 975 #define UART1_LSR 0xffc02014 /* Line Status Register */ 976 #define UART1_MSR 0xffc02018 /* Modem Status Register */ 977 #define UART1_SCR 0xffc0201c /* Scratch Register */ 978 #define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */ 979 #define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */ 980 #define UART1_THR 0xffc02028 /* Transmit Hold Register */ 981 #define UART1_RBR 0xffc0202c /* Receive Buffer Register */ 982 983 /* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */ 984 985 /* SPI1 Registers */ 986 987 #define SPI1_REGBASE 0xffc02300 988 #define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ 989 #define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */ 990 #define SPI1_STAT 0xffc02308 /* SPI1 Status Register */ 991 #define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */ 992 #define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */ 993 #define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */ 994 #define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */ 995 996 /* SPORT2 Registers */ 997 998 #define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */ 999 #define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */ 1000 #define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */ 1001 #define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */ 1002 #define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */ 1003 #define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */ 1004 #define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */ 1005 #define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */ 1006 #define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */ 1007 #define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */ 1008 #define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */ 1009 #define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */ 1010 #define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */ 1011 #define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */ 1012 #define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */ 1013 #define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */ 1014 #define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */ 1015 #define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */ 1016 #define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */ 1017 #define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */ 1018 #define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */ 1019 #define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */ 1020 1021 /* SPORT3 Registers */ 1022 1023 #define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */ 1024 #define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */ 1025 #define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */ 1026 #define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */ 1027 #define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */ 1028 #define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */ 1029 #define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */ 1030 #define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */ 1031 #define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */ 1032 #define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */ 1033 #define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */ 1034 #define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */ 1035 #define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */ 1036 #define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */ 1037 #define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */ 1038 #define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */ 1039 #define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */ 1040 #define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */ 1041 #define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */ 1042 #define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */ 1043 #define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */ 1044 #define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */ 1045 1046 /* EPPI2 Registers */ 1047 1048 #define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */ 1049 #define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */ 1050 #define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */ 1051 #define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */ 1052 #define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */ 1053 #define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */ 1054 #define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */ 1055 #define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */ 1056 #define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */ 1057 #define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ 1058 #define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ 1059 #define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ 1060 #define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ 1061 #define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */ 1062 1063 /* CAN Controller 0 Config 1 Registers */ 1064 1065 #define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */ 1066 #define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */ 1067 #define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */ 1068 #define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */ 1069 #define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ 1070 #define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */ 1071 #define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */ 1072 #define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */ 1073 #define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ 1074 #define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ 1075 #define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ 1076 #define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ 1077 #define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ 1078 1079 /* CAN Controller 0 Config 2 Registers */ 1080 1081 #define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */ 1082 #define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */ 1083 #define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */ 1084 #define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */ 1085 #define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ 1086 #define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */ 1087 #define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */ 1088 #define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */ 1089 #define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ 1090 #define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ 1091 #define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ 1092 #define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ 1093 #define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ 1094 1095 /* CAN Controller 0 Clock/Interrupt/Counter Registers */ 1096 1097 #define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */ 1098 #define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */ 1099 #define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */ 1100 #define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */ 1101 #define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */ 1102 #define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */ 1103 #define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */ 1104 #define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */ 1105 #define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */ 1106 #define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */ 1107 #define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */ 1108 #define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */ 1109 #define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */ 1110 #define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */ 1111 #define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */ 1112 #define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */ 1113 1114 /* CAN Controller 0 Acceptance Registers */ 1115 1116 #define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ 1117 #define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ 1118 #define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ 1119 #define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ 1120 #define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ 1121 #define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ 1122 #define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ 1123 #define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ 1124 #define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ 1125 #define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ 1126 #define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ 1127 #define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ 1128 #define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ 1129 #define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ 1130 #define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ 1131 #define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ 1132 #define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ 1133 #define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ 1134 #define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ 1135 #define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ 1136 #define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ 1137 #define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ 1138 #define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ 1139 #define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ 1140 #define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ 1141 #define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ 1142 #define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ 1143 #define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ 1144 #define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ 1145 #define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ 1146 #define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ 1147 #define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ 1148 1149 /* CAN Controller 0 Acceptance Registers */ 1150 1151 #define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ 1152 #define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ 1153 #define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ 1154 #define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ 1155 #define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ 1156 #define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ 1157 #define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ 1158 #define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ 1159 #define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ 1160 #define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ 1161 #define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ 1162 #define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ 1163 #define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ 1164 #define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ 1165 #define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ 1166 #define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ 1167 #define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ 1168 #define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ 1169 #define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ 1170 #define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ 1171 #define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ 1172 #define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ 1173 #define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ 1174 #define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ 1175 #define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ 1176 #define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ 1177 #define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ 1178 #define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ 1179 #define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ 1180 #define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ 1181 #define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ 1182 #define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ 1183 1184 /* CAN Controller 0 Mailbox Data Registers */ 1185 1186 #define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ 1187 #define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ 1188 #define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ 1189 #define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */ 1190 #define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */ 1191 #define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ 1192 #define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */ 1193 #define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */ 1194 #define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ 1195 #define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ 1196 #define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ 1197 #define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */ 1198 #define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */ 1199 #define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ 1200 #define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */ 1201 #define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */ 1202 #define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ 1203 #define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ 1204 #define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ 1205 #define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */ 1206 #define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */ 1207 #define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ 1208 #define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */ 1209 #define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */ 1210 #define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ 1211 #define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ 1212 #define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ 1213 #define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */ 1214 #define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */ 1215 #define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ 1216 #define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */ 1217 #define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */ 1218 #define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ 1219 #define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ 1220 #define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ 1221 #define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */ 1222 #define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */ 1223 #define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ 1224 #define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */ 1225 #define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */ 1226 #define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ 1227 #define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ 1228 #define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ 1229 #define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */ 1230 #define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */ 1231 #define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ 1232 #define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */ 1233 #define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */ 1234 #define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ 1235 #define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ 1236 #define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ 1237 #define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */ 1238 #define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */ 1239 #define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ 1240 #define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */ 1241 #define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */ 1242 #define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ 1243 #define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ 1244 #define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ 1245 #define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */ 1246 #define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */ 1247 #define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ 1248 #define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */ 1249 #define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */ 1250 #define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ 1251 #define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ 1252 #define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ 1253 #define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */ 1254 #define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */ 1255 #define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ 1256 #define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */ 1257 #define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */ 1258 #define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ 1259 #define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ 1260 #define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ 1261 #define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */ 1262 #define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */ 1263 #define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ 1264 #define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */ 1265 #define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */ 1266 #define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ 1267 #define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ 1268 #define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ 1269 #define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */ 1270 #define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */ 1271 #define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ 1272 #define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */ 1273 #define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */ 1274 #define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ 1275 #define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ 1276 #define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ 1277 #define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */ 1278 #define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */ 1279 #define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ 1280 #define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */ 1281 #define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */ 1282 #define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ 1283 #define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ 1284 #define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ 1285 #define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */ 1286 #define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */ 1287 #define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ 1288 #define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */ 1289 #define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */ 1290 #define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ 1291 #define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ 1292 #define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ 1293 #define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */ 1294 #define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */ 1295 #define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ 1296 #define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */ 1297 #define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */ 1298 #define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ 1299 #define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ 1300 #define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ 1301 #define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */ 1302 #define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */ 1303 #define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ 1304 #define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */ 1305 #define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */ 1306 #define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ 1307 #define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ 1308 #define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ 1309 #define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */ 1310 #define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */ 1311 #define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ 1312 #define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */ 1313 #define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */ 1314 1315 /* CAN Controller 0 Mailbox Data Registers */ 1316 1317 #define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ 1318 #define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ 1319 #define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ 1320 #define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */ 1321 #define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */ 1322 #define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ 1323 #define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */ 1324 #define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */ 1325 #define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ 1326 #define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ 1327 #define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ 1328 #define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */ 1329 #define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */ 1330 #define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ 1331 #define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */ 1332 #define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */ 1333 #define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ 1334 #define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ 1335 #define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ 1336 #define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */ 1337 #define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */ 1338 #define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ 1339 #define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */ 1340 #define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */ 1341 #define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ 1342 #define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ 1343 #define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ 1344 #define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */ 1345 #define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */ 1346 #define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ 1347 #define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */ 1348 #define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */ 1349 #define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ 1350 #define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ 1351 #define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ 1352 #define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */ 1353 #define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */ 1354 #define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ 1355 #define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */ 1356 #define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */ 1357 #define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ 1358 #define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ 1359 #define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ 1360 #define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */ 1361 #define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */ 1362 #define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ 1363 #define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */ 1364 #define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */ 1365 #define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ 1366 #define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ 1367 #define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ 1368 #define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */ 1369 #define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */ 1370 #define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ 1371 #define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */ 1372 #define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */ 1373 #define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ 1374 #define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ 1375 #define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ 1376 #define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */ 1377 #define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */ 1378 #define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ 1379 #define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */ 1380 #define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */ 1381 #define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ 1382 #define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ 1383 #define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ 1384 #define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */ 1385 #define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */ 1386 #define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ 1387 #define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */ 1388 #define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */ 1389 #define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ 1390 #define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ 1391 #define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ 1392 #define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */ 1393 #define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */ 1394 #define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ 1395 #define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */ 1396 #define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */ 1397 #define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ 1398 #define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ 1399 #define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ 1400 #define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */ 1401 #define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */ 1402 #define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ 1403 #define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */ 1404 #define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */ 1405 #define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ 1406 #define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ 1407 #define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ 1408 #define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */ 1409 #define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */ 1410 #define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ 1411 #define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */ 1412 #define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */ 1413 #define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ 1414 #define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ 1415 #define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ 1416 #define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */ 1417 #define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */ 1418 #define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ 1419 #define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */ 1420 #define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */ 1421 #define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ 1422 #define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ 1423 #define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ 1424 #define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */ 1425 #define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */ 1426 #define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ 1427 #define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */ 1428 #define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */ 1429 #define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ 1430 #define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ 1431 #define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ 1432 #define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */ 1433 #define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */ 1434 #define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ 1435 #define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */ 1436 #define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */ 1437 #define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ 1438 #define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ 1439 #define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ 1440 #define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */ 1441 #define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */ 1442 #define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ 1443 #define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */ 1444 #define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */ 1445 1446 /* UART3 Registers */ 1447 1448 #define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */ 1449 #define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */ 1450 #define UART3_GCTL 0xffc03108 /* Global Control Register */ 1451 #define UART3_LCR 0xffc0310c /* Line Control Register */ 1452 #define UART3_MCR 0xffc03110 /* Modem Control Register */ 1453 #define UART3_LSR 0xffc03114 /* Line Status Register */ 1454 #define UART3_MSR 0xffc03118 /* Modem Status Register */ 1455 #define UART3_SCR 0xffc0311c /* Scratch Register */ 1456 #define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */ 1457 #define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */ 1458 #define UART3_THR 0xffc03128 /* Transmit Hold Register */ 1459 #define UART3_RBR 0xffc0312c /* Receive Buffer Register */ 1460 1461 /* NFC Registers */ 1462 1463 #define NFC_CTL 0xffc03b00 /* NAND Control Register */ 1464 #define NFC_STAT 0xffc03b04 /* NAND Status Register */ 1465 #define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */ 1466 #define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */ 1467 #define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */ 1468 #define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */ 1469 #define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */ 1470 #define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */ 1471 #define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */ 1472 #define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */ 1473 #define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */ 1474 #define NFC_READ 0xffc03b2c /* NAND Read Data Register */ 1475 #define NFC_ADDR 0xffc03b40 /* NAND Address Register */ 1476 #define NFC_CMD 0xffc03b44 /* NAND Command Register */ 1477 #define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */ 1478 #define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */ 1479 1480 /* Counter Registers */ 1481 1482 #define CNT_CONFIG 0xffc04200 /* Configuration Register */ 1483 #define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */ 1484 #define CNT_STATUS 0xffc04208 /* Status Register */ 1485 #define CNT_COMMAND 0xffc0420c /* Command Register */ 1486 #define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */ 1487 #define CNT_COUNTER 0xffc04214 /* Counter Register */ 1488 #define CNT_MAX 0xffc04218 /* Maximal Count Register */ 1489 #define CNT_MIN 0xffc0421c /* Minimal Count Register */ 1490 1491 /* OTP/FUSE Registers */ 1492 1493 #define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */ 1494 #define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */ 1495 #define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */ 1496 #define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */ 1497 1498 /* Security Registers */ 1499 1500 #define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */ 1501 #define SECURE_CONTROL 0xffc04324 /* Secure Control */ 1502 #define SECURE_STATUS 0xffc04328 /* Secure Status */ 1503 1504 /* DMA Peripheral Mux Register */ 1505 1506 #define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */ 1507 1508 /* OTP Read/Write Data Buffer Registers */ 1509 1510 #define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ 1511 #define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ 1512 #define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ 1513 #define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ 1514 1515 /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */ 1516 1517 /* ********************************************************** */ 1518 /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ 1519 /* and MULTI BIT READ MACROS */ 1520 /* ********************************************************** */ 1521 1522 /* SIC_IMASK Masks */ 1523 #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ 1524 #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ 1525 #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ 1526 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ 1527 1528 /* SIC_IWR Masks */ 1529 #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ 1530 #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ 1531 #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 1532 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 1533 1534 /* Bit masks for SIC_IAR0 */ 1535 1536 #define PLL_WAKEUP 0x1 /* PLL Wakeup */ 1537 1538 /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ 1539 1540 #define DMA0_ERR 0x2 /* DMA Controller 0 Error */ 1541 #define EPPI0_ERR 0x4 /* EPPI0 Error */ 1542 #define SPORT0_ERR 0x8 /* SPORT0 Error */ 1543 #define SPORT1_ERR 0x10 /* SPORT1 Error */ 1544 #define SPI0_ERR 0x20 /* SPI0 Error */ 1545 #define UART0_ERR 0x40 /* UART0 Error */ 1546 #define RTC 0x80 /* Real-Time Clock */ 1547 #define DMA12 0x100 /* DMA Channel 12 */ 1548 #define DMA0 0x200 /* DMA Channel 0 */ 1549 #define DMA1 0x400 /* DMA Channel 1 */ 1550 #define DMA2 0x800 /* DMA Channel 2 */ 1551 #define DMA3 0x1000 /* DMA Channel 3 */ 1552 #define DMA4 0x2000 /* DMA Channel 4 */ 1553 #define DMA6 0x4000 /* DMA Channel 6 */ 1554 #define DMA7 0x8000 /* DMA Channel 7 */ 1555 #define PINT0 0x80000 /* Pin Interrupt 0 */ 1556 #define PINT1 0x100000 /* Pin Interrupt 1 */ 1557 #define MDMA0 0x200000 /* Memory DMA Stream 0 */ 1558 #define MDMA1 0x400000 /* Memory DMA Stream 1 */ 1559 #define WDOG 0x800000 /* Watchdog Timer */ 1560 #define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ 1561 #define SPORT2_ERR 0x2000000 /* SPORT2 Error */ 1562 #define SPORT3_ERR 0x4000000 /* SPORT3 Error */ 1563 #define MXVR_SD 0x8000000 /* MXVR Synchronous Data */ 1564 #define SPI1_ERR 0x10000000 /* SPI1 Error */ 1565 #define SPI2_ERR 0x20000000 /* SPI2 Error */ 1566 #define UART1_ERR 0x40000000 /* UART1 Error */ 1567 #define UART2_ERR 0x80000000 /* UART2 Error */ 1568 1569 /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ 1570 1571 #define CAN0_ERR 0x1 /* CAN0 Error */ 1572 #define DMA18 0x2 /* DMA Channel 18 */ 1573 #define DMA19 0x4 /* DMA Channel 19 */ 1574 #define DMA20 0x8 /* DMA Channel 20 */ 1575 #define DMA21 0x10 /* DMA Channel 21 */ 1576 #define DMA13 0x20 /* DMA Channel 13 */ 1577 #define DMA14 0x40 /* DMA Channel 14 */ 1578 #define DMA5 0x80 /* DMA Channel 5 */ 1579 #define DMA23 0x100 /* DMA Channel 23 */ 1580 #define DMA8 0x200 /* DMA Channel 8 */ 1581 #define DMA9 0x400 /* DMA Channel 9 */ 1582 #define DMA10 0x800 /* DMA Channel 10 */ 1583 #define DMA11 0x1000 /* DMA Channel 11 */ 1584 #define TWI0 0x2000 /* TWI0 */ 1585 #define TWI1 0x4000 /* TWI1 */ 1586 #define CAN0_RX 0x8000 /* CAN0 Receive */ 1587 #define CAN0_TX 0x10000 /* CAN0 Transmit */ 1588 #define MDMA2 0x20000 /* Memory DMA Stream 0 */ 1589 #define MDMA3 0x40000 /* Memory DMA Stream 1 */ 1590 #define MXVR_STAT 0x80000 /* MXVR Status */ 1591 #define MXVR_CM 0x100000 /* MXVR Control Message */ 1592 #define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ 1593 #define EPPI1_ERR 0x400000 /* EPPI1 Error */ 1594 #define EPPI2_ERR 0x800000 /* EPPI2 Error */ 1595 #define UART3_ERR 0x1000000 /* UART3 Error */ 1596 #define HOST_ERR 0x2000000 /* Host DMA Port Error */ 1597 #define USB_ERR 0x4000000 /* USB Error */ 1598 #define PIXC_ERR 0x8000000 /* Pixel Compositor Error */ 1599 #define NFC_ERR 0x10000000 /* Nand Flash Controller Error */ 1600 #define ATAPI_ERR 0x20000000 /* ATAPI Error */ 1601 #define CAN1_ERR 0x40000000 /* CAN1 Error */ 1602 #define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ 1603 #define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ 1604 #define DMAR0 0x80000000 /* DMAR0 Block */ 1605 #define DMAR1 0x80000000 /* DMAR1 Block */ 1606 1607 /* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ 1608 1609 #define DMA15 0x1 /* DMA Channel 15 */ 1610 #define DMA16 0x2 /* DMA Channel 16 */ 1611 #define DMA17 0x4 /* DMA Channel 17 */ 1612 #define DMA22 0x8 /* DMA Channel 22 */ 1613 #define CNT 0x10 /* Counter */ 1614 #define KEY 0x20 /* Keypad */ 1615 #define CAN1_RX 0x40 /* CAN1 Receive */ 1616 #define CAN1_TX 0x80 /* CAN1 Transmit */ 1617 #define SDH_INT_MASK0 0x100 /* SDH Mask 0 */ 1618 #define SDH_INT_MASK1 0x200 /* SDH Mask 1 */ 1619 #define USB_EINT 0x400 /* USB Exception */ 1620 #define USB_INT0 0x800 /* USB Interrupt 0 */ 1621 #define USB_INT1 0x1000 /* USB Interrupt 1 */ 1622 #define USB_INT2 0x2000 /* USB Interrupt 2 */ 1623 #define USB_DMAINT 0x4000 /* USB DMA */ 1624 #define OTPSEC 0x8000 /* OTP Access Complete */ 1625 #define TIMER0 0x400000 /* Timer 0 */ 1626 #define TIMER1 0x800000 /* Timer 1 */ 1627 #define TIMER2 0x1000000 /* Timer 2 */ 1628 #define TIMER3 0x2000000 /* Timer 3 */ 1629 #define TIMER4 0x4000000 /* Timer 4 */ 1630 #define TIMER5 0x8000000 /* Timer 5 */ 1631 #define TIMER6 0x10000000 /* Timer 6 */ 1632 #define TIMER7 0x20000000 /* Timer 7 */ 1633 #define PINT2 0x40000000 /* Pin Interrupt 2 */ 1634 #define PINT3 0x80000000 /* Pin Interrupt 3 */ 1635 1636 /* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ 1637 1638 #define DMAEN 0x1 /* DMA Channel Enable */ 1639 #define WNR 0x2 /* DMA Direction */ 1640 #define WDSIZE_8 0x0 /* Transfer Word Size = 8 */ 1641 #define WDSIZE_16 0x4 /* Transfer Word Size = 16 */ 1642 #define WDSIZE_32 0x8 /* Transfer Word Size = 32 */ 1643 #define DMA2D 0x10 /* DMA Mode */ 1644 #define RESTART 0x20 /* Work Unit Transitions */ 1645 #define DI_SEL 0x40 /* Data Interrupt Timing Select */ 1646 #define DI_EN 0x80 /* Data Interrupt Enable */ 1647 1648 #define NDSIZE 0xf00 /* Flex Descriptor Size */ 1649 #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ 1650 #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ 1651 #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ 1652 #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ 1653 #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ 1654 #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ 1655 #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ 1656 #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ 1657 #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ 1658 #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ 1659 1660 #define DMAFLOW 0xf000 /* Next Operation */ 1661 #define DMAFLOW_STOP 0x0000 /* Stop Mode */ 1662 #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ 1663 #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ 1664 #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ 1665 #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ 1666 1667 /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ 1668 1669 #define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ 1670 #define DMA_ERR 0x2 /* DMA Error Interrupt Status */ 1671 #define DFETCH 0x4 /* DMA Descriptor Fetch */ 1672 #define DMA_RUN 0x8 /* DMA Channel Running */ 1673 1674 /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ 1675 1676 #define CTYPE 0x40 /* DMA Channel Type */ 1677 #define PMAP 0xf000 /* Peripheral Mapped To This Channel */ 1678 1679 /* Bit masks for DMACx_TCPER */ 1680 1681 #define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */ 1682 #define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */ 1683 #define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */ 1684 #define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */ 1685 1686 /* Bit masks for DMACx_TCCNT */ 1687 1688 #define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */ 1689 #define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */ 1690 #define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */ 1691 #define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */ 1692 1693 /* Bit masks for DMAC1_PERIMUX */ 1694 1695 #define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ 1696 1697 /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ 1698 /* EBIU_AMGCTL Masks */ 1699 #define AMCKEN 0x0001 /* Enable CLKOUT */ 1700 #define AMBEN_NONE 0x0000 /* All Banks Disabled */ 1701 #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ 1702 #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ 1703 #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ 1704 #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ 1705 1706 1707 /* Bit masks for EBIU_AMBCTL0 */ 1708 1709 #define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ 1710 #define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ 1711 #define B0TT 0xc /* Bank 0 transition time */ 1712 #define B0ST 0x30 /* Bank 0 Setup time */ 1713 #define B0HT 0xc0 /* Bank 0 Hold time */ 1714 #define B0RAT 0xf00 /* Bank 0 Read access time */ 1715 #define B0WAT 0xf000 /* Bank 0 write access time */ 1716 #define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ 1717 #define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ 1718 #define B1TT 0xc0000 /* Bank 1 transition time */ 1719 #define B1ST 0x300000 /* Bank 1 Setup time */ 1720 #define B1HT 0xc00000 /* Bank 1 Hold time */ 1721 #define B1RAT 0xf000000 /* Bank 1 Read access time */ 1722 #define B1WAT 0xf0000000 /* Bank 1 write access time */ 1723 1724 /* Bit masks for EBIU_AMBCTL1 */ 1725 1726 #define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ 1727 #define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ 1728 #define B2TT 0xc /* Bank 2 transition time */ 1729 #define B2ST 0x30 /* Bank 2 Setup time */ 1730 #define B2HT 0xc0 /* Bank 2 Hold time */ 1731 #define B2RAT 0xf00 /* Bank 2 Read access time */ 1732 #define B2WAT 0xf000 /* Bank 2 write access time */ 1733 #define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ 1734 #define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ 1735 #define B3TT 0xc0000 /* Bank 3 transition time */ 1736 #define B3ST 0x300000 /* Bank 3 Setup time */ 1737 #define B3HT 0xc00000 /* Bank 3 Hold time */ 1738 #define B3RAT 0xf000000 /* Bank 3 Read access time */ 1739 #define B3WAT 0xf0000000 /* Bank 3 write access time */ 1740 1741 /* Bit masks for EBIU_MBSCTL */ 1742 1743 #define AMSB0CTL 0x3 /* Async Memory Bank 0 select */ 1744 #define AMSB1CTL 0xc /* Async Memory Bank 1 select */ 1745 #define AMSB2CTL 0x30 /* Async Memory Bank 2 select */ 1746 #define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */ 1747 1748 /* Bit masks for EBIU_MODE */ 1749 1750 #define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */ 1751 #define B1MODE 0xc /* Async Memory Bank 1 Access Mode */ 1752 #define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */ 1753 #define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */ 1754 1755 /* Bit masks for EBIU_FCTL */ 1756 1757 #define TESTSETLOCK 0x1 /* Test set lock */ 1758 #define BCLK 0x6 /* Burst clock frequency */ 1759 #define PGWS 0x38 /* Page wait states */ 1760 #define PGSZ 0x40 /* Page size */ 1761 #define RDDL 0x380 /* Read data delay */ 1762 1763 /* Bit masks for EBIU_ARBSTAT */ 1764 1765 #define ARBSTAT 0x1 /* Arbitration status */ 1766 #define BGSTAT 0x2 /* Bus grant status */ 1767 1768 /* Bit masks for EBIU_DDRCTL0 */ 1769 1770 #define TREFI 0x3fff /* Refresh Interval */ 1771 #define TRFC 0x3c000 /* Auto-refresh command period */ 1772 #define TRP 0x3c0000 /* Pre charge-to-active command period */ 1773 #define TRAS 0x3c00000 /* Min Active-to-pre charge time */ 1774 #define TRC 0x3c000000 /* Active-to-active time */ 1775 #define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */ 1776 #define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */ 1777 #define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */ 1778 #define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */ 1779 #define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */ 1780 1781 /* Bit masks for EBIU_DDRCTL1 */ 1782 1783 #define TRCD 0xf /* Active-to-Read/write delay */ 1784 #define TMRD 0xf0 /* Mode register set to active */ 1785 #define TWR 0x300 /* Write Recovery time */ 1786 #define DDRDATWIDTH 0x3000 /* DDR data width */ 1787 #define EXTBANKS 0xc000 /* External banks */ 1788 #define DDRDEVWIDTH 0x30000 /* DDR device width */ 1789 #define DDRDEVSIZE 0xc0000 /* DDR device size */ 1790 #define TWTR 0xf0000000 /* Write-to-read delay */ 1791 #define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */ 1792 #define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */ 1793 #define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */ 1794 #define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */ 1795 #define DDR_DATWIDTH 0x2000 /* DDR data width */ 1796 #define EXTBANK_1 0 /* 1 external bank */ 1797 #define EXTBANK_2 0x4000 /* 2 external banks */ 1798 #define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */ 1799 #define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */ 1800 #define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */ 1801 #define DEVSZ_512 0 /* DDR External Bank Size = 512MB */ 1802 #define DEVWD_4 0 /* DDR Device Width = 4 Bits */ 1803 #define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */ 1804 #define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */ 1805 1806 /* Bit masks for EBIU_DDRCTL2 */ 1807 1808 #define BURSTLENGTH 0x7 /* Burst length */ 1809 #define CASLATENCY 0x70 /* CAS latency */ 1810 #define DLLRESET 0x100 /* DLL Reset */ 1811 #define REGE 0x1000 /* Register mode enable */ 1812 #define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */ 1813 #define CL_2 0x20 /* DDR CAS Latency = 2 cycles */ 1814 #define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */ 1815 #define CL_3 0x30 /* DDR CAS Latency = 3 cycles */ 1816 1817 /* Bit masks for EBIU_DDRCTL3 */ 1818 1819 #define PASR 0x7 /* Partial array self-refresh */ 1820 1821 /* Bit masks for EBIU_DDRQUE */ 1822 1823 #define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */ 1824 #define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */ 1825 #define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ 1826 #define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ 1827 #define DEB1_URGENT 0x1000 /* DEB1 Urgent */ 1828 #define DEB2_URGENT 0x2000 /* DEB2 Urgent */ 1829 #define DEB3_URGENT 0x4000 /* DEB3 Urgent */ 1830 1831 /* Bit masks for EBIU_ERRMST */ 1832 1833 #define DEB1_ERROR 0x1 /* DEB1 Error */ 1834 #define DEB2_ERROR 0x2 /* DEB2 Error */ 1835 #define DEB3_ERROR 0x4 /* DEB3 Error */ 1836 #define CORE_ERROR 0x8 /* Core error */ 1837 #define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ 1838 #define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ 1839 #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ 1840 #define CORE_MERROR 0x80 /* Core Error (2nd) */ 1841 1842 /* Bit masks for EBIU_ERRADD */ 1843 1844 #define ERROR_ADDRESS 0xffffffff /* Error Address */ 1845 1846 /* Bit masks for EBIU_RSTCTL */ 1847 1848 #define DDRSRESET 0x1 /* DDR soft reset */ 1849 #define PFTCHSRESET 0x4 /* DDR prefetch reset */ 1850 #define SRREQ 0x8 /* Self-refresh request */ 1851 #define SRACK 0x10 /* Self-refresh acknowledge */ 1852 #define MDDRENABLE 0x20 /* Mobile DDR enable */ 1853 1854 /* Bit masks for EBIU_DDRBRC0 */ 1855 1856 #define BRC0 0xffffffff /* Count */ 1857 1858 /* Bit masks for EBIU_DDRBRC1 */ 1859 1860 #define BRC1 0xffffffff /* Count */ 1861 1862 /* Bit masks for EBIU_DDRBRC2 */ 1863 1864 #define BRC2 0xffffffff /* Count */ 1865 1866 /* Bit masks for EBIU_DDRBRC3 */ 1867 1868 #define BRC3 0xffffffff /* Count */ 1869 1870 /* Bit masks for EBIU_DDRBRC4 */ 1871 1872 #define BRC4 0xffffffff /* Count */ 1873 1874 /* Bit masks for EBIU_DDRBRC5 */ 1875 1876 #define BRC5 0xffffffff /* Count */ 1877 1878 /* Bit masks for EBIU_DDRBRC6 */ 1879 1880 #define BRC6 0xffffffff /* Count */ 1881 1882 /* Bit masks for EBIU_DDRBRC7 */ 1883 1884 #define BRC7 0xffffffff /* Count */ 1885 1886 /* Bit masks for EBIU_DDRBWC0 */ 1887 1888 #define BWC0 0xffffffff /* Count */ 1889 1890 /* Bit masks for EBIU_DDRBWC1 */ 1891 1892 #define BWC1 0xffffffff /* Count */ 1893 1894 /* Bit masks for EBIU_DDRBWC2 */ 1895 1896 #define BWC2 0xffffffff /* Count */ 1897 1898 /* Bit masks for EBIU_DDRBWC3 */ 1899 1900 #define BWC3 0xffffffff /* Count */ 1901 1902 /* Bit masks for EBIU_DDRBWC4 */ 1903 1904 #define BWC4 0xffffffff /* Count */ 1905 1906 /* Bit masks for EBIU_DDRBWC5 */ 1907 1908 #define BWC5 0xffffffff /* Count */ 1909 1910 /* Bit masks for EBIU_DDRBWC6 */ 1911 1912 #define BWC6 0xffffffff /* Count */ 1913 1914 /* Bit masks for EBIU_DDRBWC7 */ 1915 1916 #define BWC7 0xffffffff /* Count */ 1917 1918 /* Bit masks for EBIU_DDRACCT */ 1919 1920 #define ACCT 0xffffffff /* Count */ 1921 1922 /* Bit masks for EBIU_DDRTACT */ 1923 1924 #define TECT 0xffffffff /* Count */ 1925 1926 /* Bit masks for EBIU_DDRARCT */ 1927 1928 #define ARCT 0xffffffff /* Count */ 1929 1930 /* Bit masks for EBIU_DDRGC0 */ 1931 1932 #define GC0 0xffffffff /* Count */ 1933 1934 /* Bit masks for EBIU_DDRGC1 */ 1935 1936 #define GC1 0xffffffff /* Count */ 1937 1938 /* Bit masks for EBIU_DDRGC2 */ 1939 1940 #define GC2 0xffffffff /* Count */ 1941 1942 /* Bit masks for EBIU_DDRGC3 */ 1943 1944 #define GC3 0xffffffff /* Count */ 1945 1946 /* Bit masks for EBIU_DDRMCEN */ 1947 1948 #define B0WCENABLE 0x1 /* Bank 0 write count enable */ 1949 #define B1WCENABLE 0x2 /* Bank 1 write count enable */ 1950 #define B2WCENABLE 0x4 /* Bank 2 write count enable */ 1951 #define B3WCENABLE 0x8 /* Bank 3 write count enable */ 1952 #define B4WCENABLE 0x10 /* Bank 4 write count enable */ 1953 #define B5WCENABLE 0x20 /* Bank 5 write count enable */ 1954 #define B6WCENABLE 0x40 /* Bank 6 write count enable */ 1955 #define B7WCENABLE 0x80 /* Bank 7 write count enable */ 1956 #define B0RCENABLE 0x100 /* Bank 0 read count enable */ 1957 #define B1RCENABLE 0x200 /* Bank 1 read count enable */ 1958 #define B2RCENABLE 0x400 /* Bank 2 read count enable */ 1959 #define B3RCENABLE 0x800 /* Bank 3 read count enable */ 1960 #define B4RCENABLE 0x1000 /* Bank 4 read count enable */ 1961 #define B5RCENABLE 0x2000 /* Bank 5 read count enable */ 1962 #define B6RCENABLE 0x4000 /* Bank 6 read count enable */ 1963 #define B7RCENABLE 0x8000 /* Bank 7 read count enable */ 1964 #define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ 1965 #define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ 1966 #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ 1967 #define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ 1968 #define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ 1969 #define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ 1970 #define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ 1971 #define GCCONTROL 0x3000000 /* DDR Grant Count Control */ 1972 1973 /* Bit masks for EBIU_DDRMCCL */ 1974 1975 #define CB0WCOUNT 0x1 /* Clear write count 0 */ 1976 #define CB1WCOUNT 0x2 /* Clear write count 1 */ 1977 #define CB2WCOUNT 0x4 /* Clear write count 2 */ 1978 #define CB3WCOUNT 0x8 /* Clear write count 3 */ 1979 #define CB4WCOUNT 0x10 /* Clear write count 4 */ 1980 #define CB5WCOUNT 0x20 /* Clear write count 5 */ 1981 #define CB6WCOUNT 0x40 /* Clear write count 6 */ 1982 #define CB7WCOUNT 0x80 /* Clear write count 7 */ 1983 #define CBRCOUNT 0x100 /* Clear read count 0 */ 1984 #define CB1RCOUNT 0x200 /* Clear read count 1 */ 1985 #define CB2RCOUNT 0x400 /* Clear read count 2 */ 1986 #define CB3RCOUNT 0x800 /* Clear read count 3 */ 1987 #define CB4RCOUNT 0x1000 /* Clear read count 4 */ 1988 #define CB5RCOUNT 0x2000 /* Clear read count 5 */ 1989 #define CB6RCOUNT 0x4000 /* Clear read count 6 */ 1990 #define CB7RCOUNT 0x8000 /* Clear read count 7 */ 1991 #define CRACOUNT 0x10000 /* Clear row activation count */ 1992 #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ 1993 #define CARCOUNT 0x40000 /* Clear auto-refresh count */ 1994 #define CG0COUNT 0x100000 /* Clear grant count 0 */ 1995 #define CG1COUNT 0x200000 /* Clear grant count 1 */ 1996 #define CG2COUNT 0x400000 /* Clear grant count 2 */ 1997 #define CG3COUNT 0x800000 /* Clear grant count 3 */ 1998 1999 /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ 2000 2001 #define Px0 0x1 /* GPIO 0 */ 2002 #define Px1 0x2 /* GPIO 1 */ 2003 #define Px2 0x4 /* GPIO 2 */ 2004 #define Px3 0x8 /* GPIO 3 */ 2005 #define Px4 0x10 /* GPIO 4 */ 2006 #define Px5 0x20 /* GPIO 5 */ 2007 #define Px6 0x40 /* GPIO 6 */ 2008 #define Px7 0x80 /* GPIO 7 */ 2009 #define Px8 0x100 /* GPIO 8 */ 2010 #define Px9 0x200 /* GPIO 9 */ 2011 #define Px10 0x400 /* GPIO 10 */ 2012 #define Px11 0x800 /* GPIO 11 */ 2013 #define Px12 0x1000 /* GPIO 12 */ 2014 #define Px13 0x2000 /* GPIO 13 */ 2015 #define Px14 0x4000 /* GPIO 14 */ 2016 #define Px15 0x8000 /* GPIO 15 */ 2017 2018 /* Bit masks for PORTA_MUX - PORTJ_MUX */ 2019 2020 #define PxM0 0x3 /* GPIO Mux 0 */ 2021 #define PxM1 0xc /* GPIO Mux 1 */ 2022 #define PxM2 0x30 /* GPIO Mux 2 */ 2023 #define PxM3 0xc0 /* GPIO Mux 3 */ 2024 #define PxM4 0x300 /* GPIO Mux 4 */ 2025 #define PxM5 0xc00 /* GPIO Mux 5 */ 2026 #define PxM6 0x3000 /* GPIO Mux 6 */ 2027 #define PxM7 0xc000 /* GPIO Mux 7 */ 2028 #define PxM8 0x30000 /* GPIO Mux 8 */ 2029 #define PxM9 0xc0000 /* GPIO Mux 9 */ 2030 #define PxM10 0x300000 /* GPIO Mux 10 */ 2031 #define PxM11 0xc00000 /* GPIO Mux 11 */ 2032 #define PxM12 0x3000000 /* GPIO Mux 12 */ 2033 #define PxM13 0xc000000 /* GPIO Mux 13 */ 2034 #define PxM14 0x30000000 /* GPIO Mux 14 */ 2035 #define PxM15 0xc0000000 /* GPIO Mux 15 */ 2036 2037 2038 /* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ 2039 2040 #define IB0 0x1 /* Interrupt Bit 0 */ 2041 #define IB1 0x2 /* Interrupt Bit 1 */ 2042 #define IB2 0x4 /* Interrupt Bit 2 */ 2043 #define IB3 0x8 /* Interrupt Bit 3 */ 2044 #define IB4 0x10 /* Interrupt Bit 4 */ 2045 #define IB5 0x20 /* Interrupt Bit 5 */ 2046 #define IB6 0x40 /* Interrupt Bit 6 */ 2047 #define IB7 0x80 /* Interrupt Bit 7 */ 2048 #define IB8 0x100 /* Interrupt Bit 8 */ 2049 #define IB9 0x200 /* Interrupt Bit 9 */ 2050 #define IB10 0x400 /* Interrupt Bit 10 */ 2051 #define IB11 0x800 /* Interrupt Bit 11 */ 2052 #define IB12 0x1000 /* Interrupt Bit 12 */ 2053 #define IB13 0x2000 /* Interrupt Bit 13 */ 2054 #define IB14 0x4000 /* Interrupt Bit 14 */ 2055 #define IB15 0x8000 /* Interrupt Bit 15 */ 2056 2057 /* Bit masks for TIMERx_CONFIG */ 2058 2059 #define TMODE 0x3 /* Timer Mode */ 2060 #define PULSE_HI 0x4 /* Pulse Polarity */ 2061 #define PERIOD_CNT 0x8 /* Period Count */ 2062 #define IRQ_ENA 0x10 /* Interrupt Request Enable */ 2063 #define TIN_SEL 0x20 /* Timer Input Select */ 2064 #define OUT_DIS 0x40 /* Output Pad Disable */ 2065 #define CLK_SEL 0x80 /* Timer Clock Select */ 2066 #define TOGGLE_HI 0x100 /* Toggle Mode */ 2067 #define EMU_RUN 0x200 /* Emulation Behavior Select */ 2068 #define ERR_TYP 0xc000 /* Error Type */ 2069 2070 /* Bit masks for TIMER_ENABLE0 */ 2071 2072 #define TIMEN0 0x1 /* Timer 0 Enable */ 2073 #define TIMEN1 0x2 /* Timer 1 Enable */ 2074 #define TIMEN2 0x4 /* Timer 2 Enable */ 2075 #define TIMEN3 0x8 /* Timer 3 Enable */ 2076 #define TIMEN4 0x10 /* Timer 4 Enable */ 2077 #define TIMEN5 0x20 /* Timer 5 Enable */ 2078 #define TIMEN6 0x40 /* Timer 6 Enable */ 2079 #define TIMEN7 0x80 /* Timer 7 Enable */ 2080 2081 /* Bit masks for TIMER_DISABLE0 */ 2082 2083 #define TIMDIS0 0x1 /* Timer 0 Disable */ 2084 #define TIMDIS1 0x2 /* Timer 1 Disable */ 2085 #define TIMDIS2 0x4 /* Timer 2 Disable */ 2086 #define TIMDIS3 0x8 /* Timer 3 Disable */ 2087 #define TIMDIS4 0x10 /* Timer 4 Disable */ 2088 #define TIMDIS5 0x20 /* Timer 5 Disable */ 2089 #define TIMDIS6 0x40 /* Timer 6 Disable */ 2090 #define TIMDIS7 0x80 /* Timer 7 Disable */ 2091 2092 /* Bit masks for TIMER_STATUS0 */ 2093 2094 #define TIMIL0 0x1 /* Timer 0 Interrupt */ 2095 #define TIMIL1 0x2 /* Timer 1 Interrupt */ 2096 #define TIMIL2 0x4 /* Timer 2 Interrupt */ 2097 #define TIMIL3 0x8 /* Timer 3 Interrupt */ 2098 #define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ 2099 #define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ 2100 #define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ 2101 #define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ 2102 #define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ 2103 #define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ 2104 #define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ 2105 #define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ 2106 #define TIMIL4 0x10000 /* Timer 4 Interrupt */ 2107 #define TIMIL5 0x20000 /* Timer 5 Interrupt */ 2108 #define TIMIL6 0x40000 /* Timer 6 Interrupt */ 2109 #define TIMIL7 0x80000 /* Timer 7 Interrupt */ 2110 #define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ 2111 #define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ 2112 #define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ 2113 #define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ 2114 #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ 2115 #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ 2116 #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ 2117 #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ 2118 2119 /* Bit masks for WDOG_CTL */ 2120 2121 #define WDEV 0x6 /* Watchdog Event */ 2122 #define WDEN 0xff0 /* Watchdog Enable */ 2123 #define WDRO 0x8000 /* Watchdog Rolled Over */ 2124 2125 /* Bit masks for CNT_CONFIG */ 2126 2127 #define CNTE 0x1 /* Counter Enable */ 2128 #define DEBE 0x2 /* Debounce Enable */ 2129 #define CDGINV 0x10 /* CDG Pin Polarity Invert */ 2130 #define CUDINV 0x20 /* CUD Pin Polarity Invert */ 2131 #define CZMINV 0x40 /* CZM Pin Polarity Invert */ 2132 #define CNTMODE 0x700 /* Counter Operating Mode */ 2133 #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ 2134 #define BNDMODE 0x3000 /* Boundary register Mode */ 2135 #define INPDIS 0x8000 /* CUG and CDG Input Disable */ 2136 2137 /* Bit masks for CNT_IMASK */ 2138 2139 #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ 2140 #define UCIE 0x2 /* Up count Interrupt Enable */ 2141 #define DCIE 0x4 /* Down count Interrupt Enable */ 2142 #define MINCIE 0x8 /* Min Count Interrupt Enable */ 2143 #define MAXCIE 0x10 /* Max Count Interrupt Enable */ 2144 #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ 2145 #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ 2146 #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ 2147 #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ 2148 #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ 2149 #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ 2150 2151 /* Bit masks for CNT_STATUS */ 2152 2153 #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ 2154 #define UCII 0x2 /* Up count Interrupt Identifier */ 2155 #define DCII 0x4 /* Down count Interrupt Identifier */ 2156 #define MINCII 0x8 /* Min Count Interrupt Identifier */ 2157 #define MAXCII 0x10 /* Max Count Interrupt Identifier */ 2158 #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ 2159 #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ 2160 #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ 2161 #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ 2162 #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ 2163 #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ 2164 2165 /* Bit masks for CNT_COMMAND */ 2166 2167 #define W1LCNT 0xf /* Load Counter Register */ 2168 #define W1LMIN 0xf0 /* Load Min Register */ 2169 #define W1LMAX 0xf00 /* Load Max Register */ 2170 #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ 2171 2172 /* Bit masks for CNT_DEBOUNCE */ 2173 2174 #define DPRESCALE 0xf /* Load Counter Register */ 2175 2176 /* Bit masks for RTC_STAT */ 2177 2178 #define SECONDS 0x3f /* Seconds */ 2179 #define MINUTES 0xfc0 /* Minutes */ 2180 #define HOURS 0x1f000 /* Hours */ 2181 #define DAY_COUNTER 0xfffe0000 /* Day Counter */ 2182 2183 /* Bit masks for RTC_ICTL */ 2184 2185 #define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ 2186 #define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ 2187 #define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ 2188 #define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ 2189 #define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ 2190 #define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ 2191 #define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ 2192 #define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ 2193 2194 /* Bit masks for RTC_ISTAT */ 2195 2196 #define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ 2197 #define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ 2198 #define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ 2199 #define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ 2200 #define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ 2201 #define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ 2202 #define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ 2203 #define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ 2204 #define WRITE_COMPLETE 0x8000 /* Write Complete */ 2205 2206 /* Bit masks for RTC_SWCNT */ 2207 2208 #define STOPWATCH_COUNT 0xffff /* Stopwatch Count */ 2209 2210 /* Bit masks for RTC_ALARM */ 2211 2212 #define SECONDS 0x3f /* Seconds */ 2213 #define MINUTES 0xfc0 /* Minutes */ 2214 #define HOURS 0x1f000 /* Hours */ 2215 #define DAY 0xfffe0000 /* Day */ 2216 2217 /* Bit masks for RTC_PREN */ 2218 2219 #define PREN 0x1 /* Prescaler Enable */ 2220 2221 /* Bit masks for OTP_CONTROL */ 2222 2223 #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ 2224 #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ 2225 #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ 2226 #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ 2227 #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ 2228 #define FWREN 0x8000 /* OTP/Fuse Write Enable */ 2229 2230 /* Bit masks for OTP_BEN */ 2231 2232 #define FBEN 0xffff /* OTP/Fuse Byte Enable */ 2233 2234 /* Bit masks for OTP_STATUS */ 2235 2236 #define FCOMP 0x1 /* OTP/Fuse Access Complete */ 2237 #define FERROR 0x2 /* OTP/Fuse Access Error */ 2238 #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ 2239 #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ 2240 #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ 2241 2242 /* Bit masks for OTP_TIMING */ 2243 2244 #define USECDIV 0xff /* Micro Second Divider */ 2245 #define READACC 0x7f00 /* Read Access Time */ 2246 #define CPUMPRL 0x38000 /* Charge Pump Release Time */ 2247 #define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ 2248 #define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ 2249 #define PGMTIME 0xff000000 /* Program Time */ 2250 2251 /* Bit masks for SECURE_SYSSWT */ 2252 2253 #define EMUDABL 0x1 /* Emulation Disable. */ 2254 #define RSTDABL 0x2 /* Reset Disable */ 2255 #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ 2256 #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ 2257 #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ 2258 #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ 2259 #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ 2260 #define EMUOVR 0x4000 /* Emulation Override */ 2261 #define OTPSEN 0x8000 /* OTP Secrets Enable. */ 2262 #define L2DABL 0x70000 /* L2 Memory Disable. */ 2263 2264 /* Bit masks for SECURE_CONTROL */ 2265 2266 #define SECURE0 0x1 /* SECURE 0 */ 2267 #define SECURE1 0x2 /* SECURE 1 */ 2268 #define SECURE2 0x4 /* SECURE 2 */ 2269 #define SECURE3 0x8 /* SECURE 3 */ 2270 2271 /* Bit masks for SECURE_STATUS */ 2272 2273 #define SECMODE 0x3 /* Secured Mode Control State */ 2274 #define NMI 0x4 /* Non Maskable Interrupt */ 2275 #define AFVALID 0x8 /* Authentication Firmware Valid */ 2276 #define AFEXIT 0x10 /* Authentication Firmware Exit */ 2277 #define SECSTAT 0xe0 /* Secure Status */ 2278 2279 /* Bit masks for PLL_DIV */ 2280 2281 #define CSEL 0x30 /* Core Select */ 2282 #define SSEL 0xf /* System Select */ 2283 #define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ 2284 #define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ 2285 #define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ 2286 #define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ 2287 2288 /* Bit masks for PLL_CTL */ 2289 2290 #define MSEL 0x7e00 /* Multiplier Select */ 2291 #define BYPASS 0x100 /* PLL Bypass Enable */ 2292 #define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ 2293 #define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ 2294 #define PDWN 0x20 /* Power Down */ 2295 #define STOPCK 0x8 /* Stop Clock */ 2296 #define PLL_OFF 0x2 /* Disable PLL */ 2297 #define DF 0x1 /* Divide Frequency */ 2298 2299 /* SWRST Masks */ 2300 #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 2301 #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 2302 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ 2303 #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ 2304 #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 2305 2306 /* Bit masks for PLL_STAT */ 2307 2308 #define PLL_LOCKED 0x20 /* PLL Locked Status */ 2309 #define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ 2310 #define FULL_ON 0x2 /* Full-On Mode */ 2311 #define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ 2312 #define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ 2313 #define CANWS 0x800 /* CAN Wake-Up Status */ 2314 #define USBWS 0x2000 /* USB Wake-Up Status */ 2315 #define KPADWS 0x4000 /* Keypad Wake-Up Status */ 2316 #define ROTWS 0x8000 /* Rotary Wake-Up Status */ 2317 #define GPWS 0x1000 /* General-Purpose Wake-Up Status */ 2318 2319 /* Bit masks for VR_CTL */ 2320 2321 #define FREQ 0x3 /* Regulator Switching Frequency */ 2322 #define GAIN 0xc /* Voltage Output Level Gain */ 2323 #define VLEV 0xf0 /* Internal Voltage Level */ 2324 #define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ 2325 #define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ 2326 #define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ 2327 #define GPWE 0x400 /* General-Purpose Wake-Up Enable */ 2328 #define USBWE 0x800 /* USB Wake-Up Enable */ 2329 #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ 2330 #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ 2331 2332 #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ 2333 #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ 2334 #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ 2335 2336 #define GAIN_5 0x0000 /* GAIN = 5*/ 2337 #define GAIN_10 0x0004 /* GAIN = 1*/ 2338 #define GAIN_20 0x0008 /* GAIN = 2*/ 2339 #define GAIN_50 0x000C /* GAIN = 5*/ 2340 2341 #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 2342 #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 2343 #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 2344 #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 2345 #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ 2346 #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 2347 #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 2348 #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 2349 #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ 2350 #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 2351 2352 /* Bit masks for NFC_CTL */ 2353 2354 #define WR_DLY 0xf /* Write Strobe Delay */ 2355 #define RD_DLY 0xf0 /* Read Strobe Delay */ 2356 #define NWIDTH 0x100 /* NAND Data Width */ 2357 #define PG_SIZE 0x200 /* Page Size */ 2358 2359 /* Bit masks for NFC_STAT */ 2360 2361 #define NBUSY 0x1 /* Not Busy */ 2362 #define WB_FULL 0x2 /* Write Buffer Full */ 2363 #define PG_WR_STAT 0x4 /* Page Write Pending */ 2364 #define PG_RD_STAT 0x8 /* Page Read Pending */ 2365 #define WB_EMPTY 0x10 /* Write Buffer Empty */ 2366 2367 /* Bit masks for NFC_IRQSTAT */ 2368 2369 #define NBUSYIRQ 0x1 /* Not Busy IRQ */ 2370 #define WB_OVF 0x2 /* Write Buffer Overflow */ 2371 #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ 2372 #define RD_RDY 0x8 /* Read Data Ready */ 2373 #define WR_DONE 0x10 /* Page Write Done */ 2374 2375 /* Bit masks for NFC_IRQMASK */ 2376 2377 #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ 2378 #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ 2379 #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ 2380 #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ 2381 #define MASK_WRDONE 0x10 /* Mask Write Done */ 2382 2383 /* Bit masks for NFC_RST */ 2384 2385 #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ 2386 2387 /* Bit masks for NFC_PGCTL */ 2388 2389 #define PG_RD_START 0x1 /* Page Read Start */ 2390 #define PG_WR_START 0x2 /* Page Write Start */ 2391 2392 /* Bit masks for NFC_ECC0 */ 2393 2394 #define ECC0 0x7ff /* Parity Calculation Result0 */ 2395 2396 /* Bit masks for NFC_ECC1 */ 2397 2398 #define ECC1 0x7ff /* Parity Calculation Result1 */ 2399 2400 /* Bit masks for NFC_ECC2 */ 2401 2402 #define ECC2 0x7ff /* Parity Calculation Result2 */ 2403 2404 /* Bit masks for NFC_ECC3 */ 2405 2406 #define ECC3 0x7ff /* Parity Calculation Result3 */ 2407 2408 /* Bit masks for NFC_COUNT */ 2409 2410 #define ECCCNT 0x3ff /* Transfer Count */ 2411 2412 /* Bit masks for CAN0_CONTROL */ 2413 2414 #define SRS 0x1 /* Software Reset */ 2415 #define DNM 0x2 /* DeviceNet Mode */ 2416 #define ABO 0x4 /* Auto Bus On */ 2417 #define WBA 0x10 /* Wakeup On CAN Bus Activity */ 2418 #define SMR 0x20 /* Sleep Mode Request */ 2419 #define CSR 0x40 /* CAN Suspend Mode Request */ 2420 #define CCR 0x80 /* CAN Configuration Mode Request */ 2421 2422 /* Bit masks for CAN0_STATUS */ 2423 2424 #define WT 0x1 /* CAN Transmit Warning Flag */ 2425 #define WR 0x2 /* CAN Receive Warning Flag */ 2426 #define EP 0x4 /* CAN Error Passive Mode */ 2427 #define EBO 0x8 /* CAN Error Bus Off Mode */ 2428 #define CSA 0x40 /* CAN Suspend Mode Acknowledge */ 2429 #define CCA 0x80 /* CAN Configuration Mode Acknowledge */ 2430 #define MBPTR 0x1f00 /* Mailbox Pointer */ 2431 #define TRM 0x4000 /* Transmit Mode Status */ 2432 #define REC 0x8000 /* Receive Mode Status */ 2433 2434 /* Bit masks for CAN0_DEBUG */ 2435 2436 #define DEC 0x1 /* Disable Transmit/Receive Error Counters */ 2437 #define DRI 0x2 /* Disable CANRX Input Pin */ 2438 #define DTO 0x4 /* Disable CANTX Output Pin */ 2439 #define DIL 0x8 /* Disable Internal Loop */ 2440 #define MAA 0x10 /* Mode Auto-Acknowledge */ 2441 #define MRB 0x20 /* Mode Read Back */ 2442 #define CDE 0x8000 /* CAN Debug Mode Enable */ 2443 2444 /* Bit masks for CAN0_CLOCK */ 2445 2446 #define BRP 0x3ff /* CAN Bit Rate Prescaler */ 2447 2448 /* Bit masks for CAN0_TIMING */ 2449 2450 #define SJW 0x300 /* Synchronization Jump Width */ 2451 #define SAM 0x80 /* Sampling */ 2452 #define TSEG2 0x70 /* Time Segment 2 */ 2453 #define TSEG1 0xf /* Time Segment 1 */ 2454 2455 /* Bit masks for CAN0_INTR */ 2456 2457 #define CANRX 0x80 /* Serial Input From Transceiver */ 2458 #define CANTX 0x40 /* Serial Output To Transceiver */ 2459 #define SMACK 0x8 /* Sleep Mode Acknowledge */ 2460 #define GIRQ 0x4 /* Global Interrupt Request Status */ 2461 #define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ 2462 #define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ 2463 2464 /* Bit masks for CAN0_GIM */ 2465 2466 #define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ 2467 #define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ 2468 #define EPIM 0x4 /* Error Passive Interrupt Mask */ 2469 #define BOIM 0x8 /* Bus Off Interrupt Mask */ 2470 #define WUIM 0x10 /* Wakeup Interrupt Mask */ 2471 #define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ 2472 #define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ 2473 #define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ 2474 #define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ 2475 #define ADIM 0x400 /* Access Denied Interrupt Mask */ 2476 2477 /* Bit masks for CAN0_GIS */ 2478 2479 #define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ 2480 #define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ 2481 #define EPIS 0x4 /* Error Passive Interrupt Status */ 2482 #define BOIS 0x8 /* Bus Off Interrupt Status */ 2483 #define WUIS 0x10 /* Wakeup Interrupt Status */ 2484 #define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ 2485 #define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ 2486 #define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ 2487 #define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ 2488 #define ADIS 0x400 /* Access Denied Interrupt Status */ 2489 2490 /* Bit masks for CAN0_GIF */ 2491 2492 #define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ 2493 #define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ 2494 #define EPIF 0x4 /* Error Passive Interrupt Flag */ 2495 #define BOIF 0x8 /* Bus Off Interrupt Flag */ 2496 #define WUIF 0x10 /* Wakeup Interrupt Flag */ 2497 #define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ 2498 #define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ 2499 #define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ 2500 #define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ 2501 #define ADIF 0x400 /* Access Denied Interrupt Flag */ 2502 2503 /* Bit masks for CAN0_MBTD */ 2504 2505 #define TDR 0x80 /* Temporary Disable Request */ 2506 #define TDA 0x40 /* Temporary Disable Acknowledge */ 2507 #define TDPTR 0x1f /* Temporary Disable Pointer */ 2508 2509 /* Bit masks for CAN0_UCCNF */ 2510 2511 #define UCCNF 0xf /* Universal Counter Configuration */ 2512 #define UCRC 0x20 /* Universal Counter Reload/Clear */ 2513 #define UCCT 0x40 /* Universal Counter CAN Trigger */ 2514 #define UCE 0x80 /* Universal Counter Enable */ 2515 2516 /* Bit masks for CAN0_UCCNT */ 2517 2518 #define UCCNT 0xffff /* Universal Counter Count Value */ 2519 2520 /* Bit masks for CAN0_UCRC */ 2521 2522 #define UCVAL 0xffff /* Universal Counter Reload/Capture Value */ 2523 2524 /* Bit masks for CAN0_CEC */ 2525 2526 #define RXECNT 0xff /* Receive Error Counter */ 2527 #define TXECNT 0xff00 /* Transmit Error Counter */ 2528 2529 /* Bit masks for CAN0_ESR */ 2530 2531 #define FER 0x80 /* Form Error */ 2532 #define BEF 0x40 /* Bit Error Flag */ 2533 #define SA0 0x20 /* Stuck At Dominant */ 2534 #define CRCE 0x10 /* CRC Error */ 2535 #define SER 0x8 /* Stuff Bit Error */ 2536 #define ACKE 0x4 /* Acknowledge Error */ 2537 2538 /* Bit masks for CAN0_EWR */ 2539 2540 #define EWLTEC 0xff00 /* Transmit Error Warning Limit */ 2541 #define EWLREC 0xff /* Receive Error Warning Limit */ 2542 2543 /* Bit masks for CAN0_AMxx_H */ 2544 2545 #define FDF 0x8000 /* Filter On Data Field */ 2546 #define FMD 0x4000 /* Full Mask Data */ 2547 #define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ 2548 #define BASEID 0x1ffc /* Base Identifier */ 2549 #define EXTID_HI 0x3 /* Extended Identifier High Bits */ 2550 2551 /* Bit masks for CAN0_AMxx_L */ 2552 2553 #define EXTID_LO 0xffff /* Extended Identifier Low Bits */ 2554 #define DFM 0xffff /* Data Field Mask */ 2555 2556 /* Bit masks for CAN0_MBxx_ID1 */ 2557 2558 #define AME 0x8000 /* Acceptance Mask Enable */ 2559 #define RTR 0x4000 /* Remote Transmission Request */ 2560 #define IDE 0x2000 /* Identifier Extension */ 2561 #define BASEID 0x1ffc /* Base Identifier */ 2562 #define EXTID_HI 0x3 /* Extended Identifier High Bits */ 2563 2564 /* Bit masks for CAN0_MBxx_ID0 */ 2565 2566 #define EXTID_LO 0xffff /* Extended Identifier Low Bits */ 2567 #define DFM 0xffff /* Data Field Mask */ 2568 2569 /* Bit masks for CAN0_MBxx_TIMESTAMP */ 2570 2571 #define TSV 0xffff /* Time Stamp Value */ 2572 2573 /* Bit masks for CAN0_MBxx_LENGTH */ 2574 2575 #define DLC 0xf /* Data Length Code */ 2576 2577 /* Bit masks for CAN0_MBxx_DATA3 */ 2578 2579 #define CAN_BYTE0 0xff00 /* Data Field Byte 0 */ 2580 #define CAN_BYTE1 0xff /* Data Field Byte 1 */ 2581 2582 /* Bit masks for CAN0_MBxx_DATA2 */ 2583 2584 #define CAN_BYTE2 0xff00 /* Data Field Byte 2 */ 2585 #define CAN_BYTE3 0xff /* Data Field Byte 3 */ 2586 2587 /* Bit masks for CAN0_MBxx_DATA1 */ 2588 2589 #define CAN_BYTE4 0xff00 /* Data Field Byte 4 */ 2590 #define CAN_BYTE5 0xff /* Data Field Byte 5 */ 2591 2592 /* Bit masks for CAN0_MBxx_DATA0 */ 2593 2594 #define CAN_BYTE6 0xff00 /* Data Field Byte 6 */ 2595 #define CAN_BYTE7 0xff /* Data Field Byte 7 */ 2596 2597 /* Bit masks for CAN0_MC1 */ 2598 2599 #define MC0 0x1 /* Mailbox 0 Enable */ 2600 #define MC1 0x2 /* Mailbox 1 Enable */ 2601 #define MC2 0x4 /* Mailbox 2 Enable */ 2602 #define MC3 0x8 /* Mailbox 3 Enable */ 2603 #define MC4 0x10 /* Mailbox 4 Enable */ 2604 #define MC5 0x20 /* Mailbox 5 Enable */ 2605 #define MC6 0x40 /* Mailbox 6 Enable */ 2606 #define MC7 0x80 /* Mailbox 7 Enable */ 2607 #define MC8 0x100 /* Mailbox 8 Enable */ 2608 #define MC9 0x200 /* Mailbox 9 Enable */ 2609 #define MC10 0x400 /* Mailbox 10 Enable */ 2610 #define MC11 0x800 /* Mailbox 11 Enable */ 2611 #define MC12 0x1000 /* Mailbox 12 Enable */ 2612 #define MC13 0x2000 /* Mailbox 13 Enable */ 2613 #define MC14 0x4000 /* Mailbox 14 Enable */ 2614 #define MC15 0x8000 /* Mailbox 15 Enable */ 2615 2616 /* Bit masks for CAN0_MC2 */ 2617 2618 #define MC16 0x1 /* Mailbox 16 Enable */ 2619 #define MC17 0x2 /* Mailbox 17 Enable */ 2620 #define MC18 0x4 /* Mailbox 18 Enable */ 2621 #define MC19 0x8 /* Mailbox 19 Enable */ 2622 #define MC20 0x10 /* Mailbox 20 Enable */ 2623 #define MC21 0x20 /* Mailbox 21 Enable */ 2624 #define MC22 0x40 /* Mailbox 22 Enable */ 2625 #define MC23 0x80 /* Mailbox 23 Enable */ 2626 #define MC24 0x100 /* Mailbox 24 Enable */ 2627 #define MC25 0x200 /* Mailbox 25 Enable */ 2628 #define MC26 0x400 /* Mailbox 26 Enable */ 2629 #define MC27 0x800 /* Mailbox 27 Enable */ 2630 #define MC28 0x1000 /* Mailbox 28 Enable */ 2631 #define MC29 0x2000 /* Mailbox 29 Enable */ 2632 #define MC30 0x4000 /* Mailbox 30 Enable */ 2633 #define MC31 0x8000 /* Mailbox 31 Enable */ 2634 2635 /* Bit masks for CAN0_MD1 */ 2636 2637 #define MD0 0x1 /* Mailbox 0 Receive Enable */ 2638 #define MD1 0x2 /* Mailbox 1 Receive Enable */ 2639 #define MD2 0x4 /* Mailbox 2 Receive Enable */ 2640 #define MD3 0x8 /* Mailbox 3 Receive Enable */ 2641 #define MD4 0x10 /* Mailbox 4 Receive Enable */ 2642 #define MD5 0x20 /* Mailbox 5 Receive Enable */ 2643 #define MD6 0x40 /* Mailbox 6 Receive Enable */ 2644 #define MD7 0x80 /* Mailbox 7 Receive Enable */ 2645 #define MD8 0x100 /* Mailbox 8 Receive Enable */ 2646 #define MD9 0x200 /* Mailbox 9 Receive Enable */ 2647 #define MD10 0x400 /* Mailbox 10 Receive Enable */ 2648 #define MD11 0x800 /* Mailbox 11 Receive Enable */ 2649 #define MD12 0x1000 /* Mailbox 12 Receive Enable */ 2650 #define MD13 0x2000 /* Mailbox 13 Receive Enable */ 2651 #define MD14 0x4000 /* Mailbox 14 Receive Enable */ 2652 #define MD15 0x8000 /* Mailbox 15 Receive Enable */ 2653 2654 /* Bit masks for CAN0_MD2 */ 2655 2656 #define MD16 0x1 /* Mailbox 16 Receive Enable */ 2657 #define MD17 0x2 /* Mailbox 17 Receive Enable */ 2658 #define MD18 0x4 /* Mailbox 18 Receive Enable */ 2659 #define MD19 0x8 /* Mailbox 19 Receive Enable */ 2660 #define MD20 0x10 /* Mailbox 20 Receive Enable */ 2661 #define MD21 0x20 /* Mailbox 21 Receive Enable */ 2662 #define MD22 0x40 /* Mailbox 22 Receive Enable */ 2663 #define MD23 0x80 /* Mailbox 23 Receive Enable */ 2664 #define MD24 0x100 /* Mailbox 24 Receive Enable */ 2665 #define MD25 0x200 /* Mailbox 25 Receive Enable */ 2666 #define MD26 0x400 /* Mailbox 26 Receive Enable */ 2667 #define MD27 0x800 /* Mailbox 27 Receive Enable */ 2668 #define MD28 0x1000 /* Mailbox 28 Receive Enable */ 2669 #define MD29 0x2000 /* Mailbox 29 Receive Enable */ 2670 #define MD30 0x4000 /* Mailbox 30 Receive Enable */ 2671 #define MD31 0x8000 /* Mailbox 31 Receive Enable */ 2672 2673 /* Bit masks for CAN0_RMP1 */ 2674 2675 #define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ 2676 #define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ 2677 #define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ 2678 #define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ 2679 #define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ 2680 #define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ 2681 #define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ 2682 #define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ 2683 #define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ 2684 #define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ 2685 #define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ 2686 #define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ 2687 #define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ 2688 #define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ 2689 #define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ 2690 #define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ 2691 2692 /* Bit masks for CAN0_RMP2 */ 2693 2694 #define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ 2695 #define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ 2696 #define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ 2697 #define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ 2698 #define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ 2699 #define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ 2700 #define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ 2701 #define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ 2702 #define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ 2703 #define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ 2704 #define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ 2705 #define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ 2706 #define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ 2707 #define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ 2708 #define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ 2709 #define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ 2710 2711 /* Bit masks for CAN0_RML1 */ 2712 2713 #define RML0 0x1 /* Mailbox 0 Receive Message Lost */ 2714 #define RML1 0x2 /* Mailbox 1 Receive Message Lost */ 2715 #define RML2 0x4 /* Mailbox 2 Receive Message Lost */ 2716 #define RML3 0x8 /* Mailbox 3 Receive Message Lost */ 2717 #define RML4 0x10 /* Mailbox 4 Receive Message Lost */ 2718 #define RML5 0x20 /* Mailbox 5 Receive Message Lost */ 2719 #define RML6 0x40 /* Mailbox 6 Receive Message Lost */ 2720 #define RML7 0x80 /* Mailbox 7 Receive Message Lost */ 2721 #define RML8 0x100 /* Mailbox 8 Receive Message Lost */ 2722 #define RML9 0x200 /* Mailbox 9 Receive Message Lost */ 2723 #define RML10 0x400 /* Mailbox 10 Receive Message Lost */ 2724 #define RML11 0x800 /* Mailbox 11 Receive Message Lost */ 2725 #define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ 2726 #define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ 2727 #define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ 2728 #define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ 2729 2730 /* Bit masks for CAN0_RML2 */ 2731 2732 #define RML16 0x1 /* Mailbox 16 Receive Message Lost */ 2733 #define RML17 0x2 /* Mailbox 17 Receive Message Lost */ 2734 #define RML18 0x4 /* Mailbox 18 Receive Message Lost */ 2735 #define RML19 0x8 /* Mailbox 19 Receive Message Lost */ 2736 #define RML20 0x10 /* Mailbox 20 Receive Message Lost */ 2737 #define RML21 0x20 /* Mailbox 21 Receive Message Lost */ 2738 #define RML22 0x40 /* Mailbox 22 Receive Message Lost */ 2739 #define RML23 0x80 /* Mailbox 23 Receive Message Lost */ 2740 #define RML24 0x100 /* Mailbox 24 Receive Message Lost */ 2741 #define RML25 0x200 /* Mailbox 25 Receive Message Lost */ 2742 #define RML26 0x400 /* Mailbox 26 Receive Message Lost */ 2743 #define RML27 0x800 /* Mailbox 27 Receive Message Lost */ 2744 #define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ 2745 #define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ 2746 #define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ 2747 #define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ 2748 2749 /* Bit masks for CAN0_OPSS1 */ 2750 2751 #define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ 2752 #define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ 2753 #define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ 2754 #define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ 2755 #define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ 2756 #define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ 2757 #define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ 2758 #define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ 2759 #define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ 2760 #define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ 2761 #define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ 2762 #define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ 2763 #define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ 2764 #define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ 2765 #define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ 2766 #define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ 2767 2768 /* Bit masks for CAN0_OPSS2 */ 2769 2770 #define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ 2771 #define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ 2772 #define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ 2773 #define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ 2774 #define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ 2775 #define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ 2776 #define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ 2777 #define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ 2778 #define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ 2779 #define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ 2780 #define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ 2781 #define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ 2782 #define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ 2783 #define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ 2784 #define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ 2785 #define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ 2786 2787 /* Bit masks for CAN0_TRS1 */ 2788 2789 #define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ 2790 #define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ 2791 #define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ 2792 #define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ 2793 #define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ 2794 #define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ 2795 #define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ 2796 #define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ 2797 #define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ 2798 #define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ 2799 #define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ 2800 #define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ 2801 #define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ 2802 #define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ 2803 #define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ 2804 #define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ 2805 2806 /* Bit masks for CAN0_TRS2 */ 2807 2808 #define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ 2809 #define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ 2810 #define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ 2811 #define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ 2812 #define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ 2813 #define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ 2814 #define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ 2815 #define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ 2816 #define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ 2817 #define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ 2818 #define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ 2819 #define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ 2820 #define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ 2821 #define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ 2822 #define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ 2823 #define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ 2824 2825 /* Bit masks for CAN0_TRR1 */ 2826 2827 #define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ 2828 #define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ 2829 #define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ 2830 #define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ 2831 #define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ 2832 #define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ 2833 #define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ 2834 #define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ 2835 #define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ 2836 #define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ 2837 #define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ 2838 #define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ 2839 #define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ 2840 #define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ 2841 #define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ 2842 #define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ 2843 2844 /* Bit masks for CAN0_TRR2 */ 2845 2846 #define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ 2847 #define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ 2848 #define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ 2849 #define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ 2850 #define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ 2851 #define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ 2852 #define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ 2853 #define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ 2854 #define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ 2855 #define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ 2856 #define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ 2857 #define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ 2858 #define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ 2859 #define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ 2860 #define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ 2861 #define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ 2862 2863 /* Bit masks for CAN0_AA1 */ 2864 2865 #define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ 2866 #define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ 2867 #define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ 2868 #define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ 2869 #define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ 2870 #define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ 2871 #define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ 2872 #define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ 2873 #define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ 2874 #define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ 2875 #define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ 2876 #define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ 2877 #define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ 2878 #define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ 2879 #define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ 2880 #define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ 2881 2882 /* Bit masks for CAN0_AA2 */ 2883 2884 #define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ 2885 #define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ 2886 #define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ 2887 #define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ 2888 #define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ 2889 #define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ 2890 #define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ 2891 #define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ 2892 #define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ 2893 #define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ 2894 #define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ 2895 #define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ 2896 #define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ 2897 #define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ 2898 #define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ 2899 #define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ 2900 2901 /* Bit masks for CAN0_TA1 */ 2902 2903 #define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ 2904 #define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ 2905 #define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ 2906 #define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ 2907 #define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ 2908 #define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ 2909 #define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ 2910 #define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ 2911 #define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ 2912 #define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ 2913 #define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ 2914 #define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ 2915 #define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ 2916 #define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ 2917 #define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ 2918 #define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ 2919 2920 /* Bit masks for CAN0_TA2 */ 2921 2922 #define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ 2923 #define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ 2924 #define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ 2925 #define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ 2926 #define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ 2927 #define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ 2928 #define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ 2929 #define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ 2930 #define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ 2931 #define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ 2932 #define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ 2933 #define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ 2934 #define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ 2935 #define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ 2936 #define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ 2937 #define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ 2938 2939 /* Bit masks for CAN0_RFH1 */ 2940 2941 #define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ 2942 #define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ 2943 #define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ 2944 #define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ 2945 #define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ 2946 #define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ 2947 #define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ 2948 #define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ 2949 #define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ 2950 #define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ 2951 #define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ 2952 #define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ 2953 #define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ 2954 #define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ 2955 #define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ 2956 #define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ 2957 2958 /* Bit masks for CAN0_RFH2 */ 2959 2960 #define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ 2961 #define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ 2962 #define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ 2963 #define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ 2964 #define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ 2965 #define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ 2966 #define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ 2967 #define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ 2968 #define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ 2969 #define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ 2970 #define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ 2971 #define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ 2972 #define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ 2973 #define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ 2974 #define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ 2975 #define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ 2976 2977 /* Bit masks for CAN0_MBIM1 */ 2978 2979 #define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ 2980 #define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ 2981 #define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ 2982 #define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ 2983 #define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ 2984 #define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ 2985 #define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ 2986 #define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ 2987 #define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ 2988 #define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ 2989 #define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ 2990 #define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ 2991 #define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ 2992 #define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ 2993 #define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ 2994 #define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ 2995 2996 /* Bit masks for CAN0_MBIM2 */ 2997 2998 #define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ 2999 #define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ 3000 #define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ 3001 #define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ 3002 #define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ 3003 #define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ 3004 #define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ 3005 #define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ 3006 #define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ 3007 #define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ 3008 #define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ 3009 #define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ 3010 #define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ 3011 #define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ 3012 #define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ 3013 #define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ 3014 3015 /* Bit masks for CAN0_MBTIF1 */ 3016 3017 #define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ 3018 #define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ 3019 #define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ 3020 #define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ 3021 #define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ 3022 #define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ 3023 #define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ 3024 #define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ 3025 #define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ 3026 #define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ 3027 #define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ 3028 #define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ 3029 #define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ 3030 #define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ 3031 #define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ 3032 #define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ 3033 3034 /* Bit masks for CAN0_MBTIF2 */ 3035 3036 #define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ 3037 #define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ 3038 #define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ 3039 #define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ 3040 #define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ 3041 #define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ 3042 #define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ 3043 #define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ 3044 #define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ 3045 #define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ 3046 #define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ 3047 #define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ 3048 #define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ 3049 #define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ 3050 #define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ 3051 #define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ 3052 3053 /* Bit masks for CAN0_MBRIF1 */ 3054 3055 #define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ 3056 #define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ 3057 #define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ 3058 #define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ 3059 #define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ 3060 #define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ 3061 #define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ 3062 #define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ 3063 #define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ 3064 #define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ 3065 #define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ 3066 #define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ 3067 #define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ 3068 #define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ 3069 #define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ 3070 #define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ 3071 3072 /* Bit masks for CAN0_MBRIF2 */ 3073 3074 #define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ 3075 #define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ 3076 #define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ 3077 #define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ 3078 #define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ 3079 #define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ 3080 #define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ 3081 #define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ 3082 #define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ 3083 #define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ 3084 #define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ 3085 #define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ 3086 #define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ 3087 #define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ 3088 #define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ 3089 #define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ 3090 3091 /* Bit masks for EPPIx_STATUS */ 3092 3093 #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ 3094 #define YFIFO_ERR 0x2 /* Luma FIFO Error */ 3095 #define LTERR_OVR 0x4 /* Line Track Overflow */ 3096 #define LTERR_UNDR 0x8 /* Line Track Underflow */ 3097 #define FTERR_OVR 0x10 /* Frame Track Overflow */ 3098 #define FTERR_UNDR 0x20 /* Frame Track Underflow */ 3099 #define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ 3100 #define DMA1URQ 0x80 /* DMA1 Urgent Request */ 3101 #define DMA0URQ 0x100 /* DMA0 Urgent Request */ 3102 #define ERR_DET 0x4000 /* Preamble Error Detected */ 3103 #define FLD 0x8000 /* Field */ 3104 3105 /* Bit masks for EPPIx_CONTROL */ 3106 3107 #define EPPI_EN 0x1 /* Enable */ 3108 #define EPPI_DIR 0x2 /* Direction */ 3109 #define XFR_TYPE 0xc /* Operating Mode */ 3110 #define FS_CFG 0x30 /* Frame Sync Configuration */ 3111 #define FLD_SEL 0x40 /* Field Select/Trigger */ 3112 #define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ 3113 #define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ 3114 #define ICLKGEN 0x200 /* Internal Clock Generation */ 3115 #define IFSGEN 0x400 /* Internal Frame Sync Generation */ 3116 #define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ 3117 #define POLS 0x6000 /* Frame Sync Polarity */ 3118 #define DLENGTH 0x38000 /* Data Length */ 3119 #define SKIP_EN 0x40000 /* Skip Enable */ 3120 #define SKIP_EO 0x80000 /* Skip Even or Odd */ 3121 #define PACKEN 0x100000 /* Packing/Unpacking Enable */ 3122 #define SWAPEN 0x200000 /* Swap Enable */ 3123 #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ 3124 #define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ 3125 #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ 3126 #define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ 3127 #define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ 3128 #define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ 3129 #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ 3130 3131 #define DLEN_8 (0 << 15) /* 000 - 8 bits */ 3132 #define DLEN_10 (1 << 15) /* 001 - 10 bits */ 3133 #define DLEN_12 (2 << 15) /* 010 - 12 bits */ 3134 #define DLEN_14 (3 << 15) /* 011 - 14 bits */ 3135 #define DLEN_16 (4 << 15) /* 100 - 16 bits */ 3136 #define DLEN_18 (5 << 15) /* 101 - 18 bits */ 3137 #define DLEN_24 (6 << 15) /* 110 - 24 bits */ 3138 3139 3140 /* Bit masks for EPPIx_FS2W_LVB */ 3141 3142 #define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */ 3143 #define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */ 3144 #define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */ 3145 #define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */ 3146 3147 /* Bit masks for EPPIx_FS2W_LAVF */ 3148 3149 #define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */ 3150 #define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */ 3151 3152 /* Bit masks for EPPIx_CLIP */ 3153 3154 #define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */ 3155 #define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */ 3156 #define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ 3157 #define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ 3158 3159 /* Bit masks for SPIx_BAUD */ 3160 3161 #define SPI_BAUD 0xffff /* Baud Rate */ 3162 3163 /* Bit masks for SPIx_CTL */ 3164 3165 #define SPE 0x4000 /* SPI Enable */ 3166 #define WOM 0x2000 /* Write Open Drain Master */ 3167 #define MSTR 0x1000 /* Master Mode */ 3168 #define CPOL 0x800 /* Clock Polarity */ 3169 #define CPHA 0x400 /* Clock Phase */ 3170 #define LSBF 0x200 /* LSB First */ 3171 #define SIZE 0x100 /* Size of Words */ 3172 #define EMISO 0x20 /* Enable MISO Output */ 3173 #define PSSE 0x10 /* Slave-Select Enable */ 3174 #define GM 0x8 /* Get More Data */ 3175 #define SZ 0x4 /* Send Zero */ 3176 #define TIMOD 0x3 /* Transfer Initiation Mode */ 3177 3178 /* Bit masks for SPIx_FLG */ 3179 3180 #define FLS1 0x2 /* Slave Select Enable 1 */ 3181 #define FLS2 0x4 /* Slave Select Enable 2 */ 3182 #define FLS3 0x8 /* Slave Select Enable 3 */ 3183 #define FLG1 0x200 /* Slave Select Value 1 */ 3184 #define FLG2 0x400 /* Slave Select Value 2 */ 3185 #define FLG3 0x800 /* Slave Select Value 3 */ 3186 3187 /* Bit masks for SPIx_STAT */ 3188 3189 #define TXCOL 0x40 /* Transmit Collision Error */ 3190 #define RXS 0x20 /* RDBR Data Buffer Status */ 3191 #define RBSY 0x10 /* Receive Error */ 3192 #define TXS 0x8 /* TDBR Data Buffer Status */ 3193 #define TXE 0x4 /* Transmission Error */ 3194 #define MODF 0x2 /* Mode Fault Error */ 3195 #define SPIF 0x1 /* SPI Finished */ 3196 3197 /* Bit masks for SPIx_TDBR */ 3198 3199 #define TDBR 0xffff /* Transmit Data Buffer */ 3200 3201 /* Bit masks for SPIx_RDBR */ 3202 3203 #define RDBR 0xffff /* Receive Data Buffer */ 3204 3205 /* Bit masks for SPIx_SHADOW */ 3206 3207 #define SHADOW 0xffff /* RDBR Shadow */ 3208 3209 /* ************************************************ */ 3210 /* The TWI bit masks fields are from the ADSP-BF538 */ 3211 /* and they have not been verified as the final */ 3212 /* ones for the Moab processors ... bz 1/19/2007 */ 3213 /* ************************************************ */ 3214 3215 /* Bit masks for TWIx_CONTROL */ 3216 3217 #define PRESCALE 0x7f /* Prescale Value */ 3218 #define TWI_ENA 0x80 /* TWI Enable */ 3219 #define SCCB 0x200 /* Serial Camera Control Bus */ 3220 3221 /* Bit maskes for TWIx_CLKDIV */ 3222 3223 #define CLKLOW 0xff /* Clock Low */ 3224 #define CLKHI 0xff00 /* Clock High */ 3225 3226 /* Bit maskes for TWIx_SLAVE_CTL */ 3227 3228 #define SEN 0x1 /* Slave Enable */ 3229 #define STDVAL 0x4 /* Slave Transmit Data Valid */ 3230 #define NAK 0x8 /* Not Acknowledge */ 3231 #define GEN 0x10 /* General Call Enable */ 3232 3233 /* Bit maskes for TWIx_SLAVE_ADDR */ 3234 3235 #define SADDR 0x7f /* Slave Mode Address */ 3236 3237 /* Bit maskes for TWIx_SLAVE_STAT */ 3238 3239 #define SDIR 0x1 /* Slave Transfer Direction */ 3240 #define GCALL 0x2 /* General Call */ 3241 3242 /* Bit maskes for TWIx_MASTER_CTL */ 3243 3244 #define MEN 0x1 /* Master Mode Enable */ 3245 #define MDIR 0x4 /* Master Transfer Direction */ 3246 #define FAST 0x8 /* Fast Mode */ 3247 #define STOP 0x10 /* Issue Stop Condition */ 3248 #define RSTART 0x20 /* Repeat Start */ 3249 #define DCNT 0x3fc0 /* Data Transfer Count */ 3250 #define SDAOVR 0x4000 /* Serial Data Override */ 3251 #define SCLOVR 0x8000 /* Serial Clock Override */ 3252 3253 /* Bit maskes for TWIx_MASTER_ADDR */ 3254 3255 #define MADDR 0x7f /* Master Mode Address */ 3256 3257 /* Bit maskes for TWIx_MASTER_STAT */ 3258 3259 #define MPROG 0x1 /* Master Transfer in Progress */ 3260 #define LOSTARB 0x2 /* Lost Arbitration */ 3261 #define ANAK 0x4 /* Address Not Acknowledged */ 3262 #define DNAK 0x8 /* Data Not Acknowledged */ 3263 #define BUFRDERR 0x10 /* Buffer Read Error */ 3264 #define BUFWRERR 0x20 /* Buffer Write Error */ 3265 #define SDASEN 0x40 /* Serial Data Sense */ 3266 #define SCLSEN 0x80 /* Serial Clock Sense */ 3267 #define BUSBUSY 0x100 /* Bus Busy */ 3268 3269 /* Bit maskes for TWIx_FIFO_CTL */ 3270 3271 #define XMTFLUSH 0x1 /* Transmit Buffer Flush */ 3272 #define RCVFLUSH 0x2 /* Receive Buffer Flush */ 3273 #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ 3274 #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ 3275 3276 /* Bit maskes for TWIx_FIFO_STAT */ 3277 3278 #define XMTSTAT 0x3 /* Transmit FIFO Status */ 3279 #define RCVSTAT 0xc /* Receive FIFO Status */ 3280 3281 /* Bit maskes for TWIx_INT_MASK */ 3282 3283 #define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ 3284 #define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ 3285 #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ 3286 #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ 3287 #define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ 3288 #define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ 3289 #define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ 3290 #define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ 3291 3292 /* Bit maskes for TWIx_INT_STAT */ 3293 3294 #define SINIT 0x1 /* Slave Transfer Initiated */ 3295 #define SCOMP 0x2 /* Slave Transfer Complete */ 3296 #define SERR 0x4 /* Slave Transfer Error */ 3297 #define SOVF 0x8 /* Slave Overflow */ 3298 #define MCOMP 0x10 /* Master Transfer Complete */ 3299 #define MERR 0x20 /* Master Transfer Error */ 3300 #define XMTSERV 0x40 /* Transmit FIFO Service */ 3301 #define RCVSERV 0x80 /* Receive FIFO Service */ 3302 3303 /* Bit maskes for TWIx_XMT_DATA8 */ 3304 3305 #define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */ 3306 3307 /* Bit maskes for TWIx_XMT_DATA16 */ 3308 3309 #define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */ 3310 3311 /* Bit maskes for TWIx_RCV_DATA8 */ 3312 3313 #define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */ 3314 3315 /* Bit maskes for TWIx_RCV_DATA16 */ 3316 3317 #define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */ 3318 3319 /* Bit masks for SPORTx_TCR1 */ 3320 3321 #define TCKFE 0x4000 /* Clock Falling Edge Select */ 3322 #define LATFS 0x2000 /* Late Transmit Frame Sync */ 3323 #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ 3324 #define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ 3325 #define TFSR 0x400 /* Transmit Frame Sync Required Select */ 3326 #define ITFS 0x200 /* Internal Transmit Frame Sync Select */ 3327 #define TLSBIT 0x10 /* Transmit Bit Order */ 3328 #define TDTYPE 0xc /* Data Formatting Type Select */ 3329 #define ITCLK 0x2 /* Internal Transmit Clock Select */ 3330 #define TSPEN 0x1 /* Transmit Enable */ 3331 3332 /* Bit masks for SPORTx_TCR2 */ 3333 3334 #define TRFST 0x400 /* Left/Right Order */ 3335 #define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ 3336 #define TXSE 0x100 /* TxSEC Enable */ 3337 #define SLEN_T 0x1f /* SPORT Word Length */ 3338 3339 /* Bit masks for SPORTx_RCR1 */ 3340 3341 #define RCKFE 0x4000 /* Clock Falling Edge Select */ 3342 #define LARFS 0x2000 /* Late Receive Frame Sync */ 3343 #define LRFS 0x1000 /* Low Receive Frame Sync Select */ 3344 #define RFSR 0x400 /* Receive Frame Sync Required Select */ 3345 #define IRFS 0x200 /* Internal Receive Frame Sync Select */ 3346 #define RLSBIT 0x10 /* Receive Bit Order */ 3347 #define RDTYPE 0xc /* Data Formatting Type Select */ 3348 #define IRCLK 0x2 /* Internal Receive Clock Select */ 3349 #define RSPEN 0x1 /* Receive Enable */ 3350 3351 /* Bit masks for SPORTx_RCR2 */ 3352 3353 #define RRFST 0x400 /* Left/Right Order */ 3354 #define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ 3355 #define RXSE 0x100 /* RxSEC Enable */ 3356 #define SLEN_R 0x1f /* SPORT Word Length */ 3357 3358 /* Bit masks for SPORTx_STAT */ 3359 3360 #define TXHRE 0x40 /* Transmit Hold Register Empty */ 3361 #define TOVF 0x20 /* Sticky Transmit Overflow Status */ 3362 #define TUVF 0x10 /* Sticky Transmit Underflow Status */ 3363 #define TXF 0x8 /* Transmit FIFO Full Status */ 3364 #define ROVF 0x4 /* Sticky Receive Overflow Status */ 3365 #define RUVF 0x2 /* Sticky Receive Underflow Status */ 3366 #define RXNE 0x1 /* Receive FIFO Not Empty Status */ 3367 3368 /* Bit masks for SPORTx_MCMC1 */ 3369 3370 #define SP_WSIZE 0xf000 /* Window Size */ 3371 #define SP_WOFF 0x3ff /* Windows Offset */ 3372 3373 /* Bit masks for SPORTx_MCMC2 */ 3374 3375 #define MFD 0xf000 /* Multi channel Frame Delay */ 3376 #define FSDR 0x80 /* Frame Sync to Data Relationship */ 3377 #define MCMEN 0x10 /* Multi channel Frame Mode Enable */ 3378 #define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ 3379 #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ 3380 #define MCCRM 0x3 /* 2X Clock Recovery Mode */ 3381 3382 /* Bit masks for SPORTx_CHNL */ 3383 3384 #define CUR_CHNL 0x3ff /* Current Channel Indicator */ 3385 3386 /* Bit masks for UARTx_LCR */ 3387 3388 #if 0 3389 /* conflicts with legacy one in last section */ 3390 #define WLS 0x3 /* Word Length Select */ 3391 #endif 3392 #define STB 0x4 /* Stop Bits */ 3393 #define PEN 0x8 /* Parity Enable */ 3394 #define EPS 0x10 /* Even Parity Select */ 3395 #define STP 0x20 /* Sticky Parity */ 3396 #define SB 0x40 /* Set Break */ 3397 3398 /* Bit masks for UARTx_MCR */ 3399 3400 #define XOFF 0x1 /* Transmitter Off */ 3401 #define MRTS 0x2 /* Manual Request To Send */ 3402 #define RFIT 0x4 /* Receive FIFO IRQ Threshold */ 3403 #define RFRT 0x8 /* Receive FIFO RTS Threshold */ 3404 #define LOOP_ENA 0x10 /* Loopback Mode Enable */ 3405 #define FCPOL 0x20 /* Flow Control Pin Polarity */ 3406 #define ARTS 0x40 /* Automatic Request To Send */ 3407 #define ACTS 0x80 /* Automatic Clear To Send */ 3408 3409 /* Bit masks for UARTx_LSR */ 3410 3411 #define DR 0x1 /* Data Ready */ 3412 #define OE 0x2 /* Overrun Error */ 3413 #define PE 0x4 /* Parity Error */ 3414 #define FE 0x8 /* Framing Error */ 3415 #define BI 0x10 /* Break Interrupt */ 3416 #define THRE 0x20 /* THR Empty */ 3417 #define TEMT 0x40 /* Transmitter Empty */ 3418 #define TFI 0x80 /* Transmission Finished Indicator */ 3419 3420 /* Bit masks for UARTx_MSR */ 3421 3422 #define SCTS 0x1 /* Sticky CTS */ 3423 #define CTS 0x10 /* Clear To Send */ 3424 #define RFCS 0x20 /* Receive FIFO Count Status */ 3425 3426 /* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */ 3427 3428 #define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */ 3429 #define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */ 3430 #define ELSI 0x4 /* Enable Receive Status Interrupt */ 3431 #define EDSSI 0x8 /* Enable Modem Status Interrupt */ 3432 #define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ 3433 #define ETFI 0x20 /* Enable Transmission Finished Interrupt */ 3434 #define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ 3435 3436 /* Bit masks for UARTx_GCTL */ 3437 3438 #define UCEN 0x1 /* UART Enable */ 3439 #define IREN 0x2 /* IrDA Mode Enable */ 3440 #define TPOLC 0x4 /* IrDA TX Polarity Change */ 3441 #define RPOLC 0x8 /* IrDA RX Polarity Change */ 3442 #define FPE 0x10 /* Force Parity Error */ 3443 #define FFE 0x20 /* Force Framing Error */ 3444 #define EDBO 0x40 /* Enable Divide-by-One */ 3445 #define EGLSI 0x80 /* Enable Global LS Interrupt */ 3446 3447 3448 /* ******************************************* */ 3449 /* MULTI BIT MACRO ENUMERATIONS */ 3450 /* ******************************************* */ 3451 3452 /* BCODE bit field options (SYSCFG register) */ 3453 3454 #define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */ 3455 #define BCODE_FULLBOOT 0x0010 /* always perform full boot */ 3456 #define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */ 3457 #define BCODE_NOBOOT 0x0030 /* always perform full boot */ 3458 3459 /* CNT_COMMAND bit field options */ 3460 3461 #define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */ 3462 #define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */ 3463 #define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */ 3464 3465 #define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */ 3466 #define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */ 3467 #define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */ 3468 3469 #define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */ 3470 #define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */ 3471 #define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */ 3472 3473 /* CNT_CONFIG bit field options */ 3474 3475 #define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */ 3476 #define CNTMODE_BINENC 0x0100 /* binary encoder mode */ 3477 #define CNTMODE_UDCNT 0x0200 /* up/down counter mode */ 3478 #define CNTMODE_DIRCNT 0x0400 /* direction counter mode */ 3479 #define CNTMODE_DIRTMR 0x0500 /* direction timer mode */ 3480 3481 #define BNDMODE_COMP 0x0000 /* boundary compare mode */ 3482 #define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */ 3483 #define BNDMODE_CAPT 0x2000 /* boundary capture mode */ 3484 #define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ 3485 3486 /* TMODE in TIMERx_CONFIG bit field options */ 3487 3488 #define PWM_OUT 0x0001 3489 #define WDTH_CAP 0x0002 3490 #define EXT_CLK 0x0003 3491 3492 /* UARTx_LCR bit field options */ 3493 3494 #define WLS_5 0x0000 /* 5 data bits */ 3495 #define WLS_6 0x0001 /* 6 data bits */ 3496 #define WLS_7 0x0002 /* 7 data bits */ 3497 #define WLS_8 0x0003 /* 8 data bits */ 3498 3499 /* PINTx Register Bit Definitions */ 3500 3501 #define PIQ0 0x00000001 3502 #define PIQ1 0x00000002 3503 #define PIQ2 0x00000004 3504 #define PIQ3 0x00000008 3505 3506 #define PIQ4 0x00000010 3507 #define PIQ5 0x00000020 3508 #define PIQ6 0x00000040 3509 #define PIQ7 0x00000080 3510 3511 #define PIQ8 0x00000100 3512 #define PIQ9 0x00000200 3513 #define PIQ10 0x00000400 3514 #define PIQ11 0x00000800 3515 3516 #define PIQ12 0x00001000 3517 #define PIQ13 0x00002000 3518 #define PIQ14 0x00004000 3519 #define PIQ15 0x00008000 3520 3521 #define PIQ16 0x00010000 3522 #define PIQ17 0x00020000 3523 #define PIQ18 0x00040000 3524 #define PIQ19 0x00080000 3525 3526 #define PIQ20 0x00100000 3527 #define PIQ21 0x00200000 3528 #define PIQ22 0x00400000 3529 #define PIQ23 0x00800000 3530 3531 #define PIQ24 0x01000000 3532 #define PIQ25 0x02000000 3533 #define PIQ26 0x04000000 3534 #define PIQ27 0x08000000 3535 3536 #define PIQ28 0x10000000 3537 #define PIQ29 0x20000000 3538 #define PIQ30 0x40000000 3539 #define PIQ31 0x80000000 3540 3541 /* PORT A Bit Definitions for the registers 3542 PORTA, PORTA_SET, PORTA_CLEAR, 3543 PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN, 3544 PORTA_FER registers 3545 */ 3546 3547 #define PA0 0x0001 3548 #define PA1 0x0002 3549 #define PA2 0x0004 3550 #define PA3 0x0008 3551 #define PA4 0x0010 3552 #define PA5 0x0020 3553 #define PA6 0x0040 3554 #define PA7 0x0080 3555 #define PA8 0x0100 3556 #define PA9 0x0200 3557 #define PA10 0x0400 3558 #define PA11 0x0800 3559 #define PA12 0x1000 3560 #define PA13 0x2000 3561 #define PA14 0x4000 3562 #define PA15 0x8000 3563 3564 /* PORT B Bit Definitions for the registers 3565 PORTB, PORTB_SET, PORTB_CLEAR, 3566 PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN, 3567 PORTB_FER registers 3568 */ 3569 3570 #define PB0 0x0001 3571 #define PB1 0x0002 3572 #define PB2 0x0004 3573 #define PB3 0x0008 3574 #define PB4 0x0010 3575 #define PB5 0x0020 3576 #define PB6 0x0040 3577 #define PB7 0x0080 3578 #define PB8 0x0100 3579 #define PB9 0x0200 3580 #define PB10 0x0400 3581 #define PB11 0x0800 3582 #define PB12 0x1000 3583 #define PB13 0x2000 3584 #define PB14 0x4000 3585 3586 3587 /* PORT C Bit Definitions for the registers 3588 PORTC, PORTC_SET, PORTC_CLEAR, 3589 PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN, 3590 PORTC_FER registers 3591 */ 3592 3593 3594 #define PC0 0x0001 3595 #define PC1 0x0002 3596 #define PC2 0x0004 3597 #define PC3 0x0008 3598 #define PC4 0x0010 3599 #define PC5 0x0020 3600 #define PC6 0x0040 3601 #define PC7 0x0080 3602 #define PC8 0x0100 3603 #define PC9 0x0200 3604 #define PC10 0x0400 3605 #define PC11 0x0800 3606 #define PC12 0x1000 3607 #define PC13 0x2000 3608 3609 3610 /* PORT D Bit Definitions for the registers 3611 PORTD, PORTD_SET, PORTD_CLEAR, 3612 PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN, 3613 PORTD_FER registers 3614 */ 3615 3616 #define PD0 0x0001 3617 #define PD1 0x0002 3618 #define PD2 0x0004 3619 #define PD3 0x0008 3620 #define PD4 0x0010 3621 #define PD5 0x0020 3622 #define PD6 0x0040 3623 #define PD7 0x0080 3624 #define PD8 0x0100 3625 #define PD9 0x0200 3626 #define PD10 0x0400 3627 #define PD11 0x0800 3628 #define PD12 0x1000 3629 #define PD13 0x2000 3630 #define PD14 0x4000 3631 #define PD15 0x8000 3632 3633 /* PORT E Bit Definitions for the registers 3634 PORTE, PORTE_SET, PORTE_CLEAR, 3635 PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN, 3636 PORTE_FER registers 3637 */ 3638 3639 3640 #define PE0 0x0001 3641 #define PE1 0x0002 3642 #define PE2 0x0004 3643 #define PE3 0x0008 3644 #define PE4 0x0010 3645 #define PE5 0x0020 3646 #define PE6 0x0040 3647 #define PE7 0x0080 3648 #define PE8 0x0100 3649 #define PE9 0x0200 3650 #define PE10 0x0400 3651 #define PE11 0x0800 3652 #define PE12 0x1000 3653 #define PE13 0x2000 3654 #define PE14 0x4000 3655 #define PE15 0x8000 3656 3657 /* PORT F Bit Definitions for the registers 3658 PORTF, PORTF_SET, PORTF_CLEAR, 3659 PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN, 3660 PORTF_FER registers 3661 */ 3662 3663 3664 #define PF0 0x0001 3665 #define PF1 0x0002 3666 #define PF2 0x0004 3667 #define PF3 0x0008 3668 #define PF4 0x0010 3669 #define PF5 0x0020 3670 #define PF6 0x0040 3671 #define PF7 0x0080 3672 #define PF8 0x0100 3673 #define PF9 0x0200 3674 #define PF10 0x0400 3675 #define PF11 0x0800 3676 #define PF12 0x1000 3677 #define PF13 0x2000 3678 #define PF14 0x4000 3679 #define PF15 0x8000 3680 3681 /* PORT G Bit Definitions for the registers 3682 PORTG, PORTG_SET, PORTG_CLEAR, 3683 PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN, 3684 PORTG_FER registers 3685 */ 3686 3687 3688 #define PG0 0x0001 3689 #define PG1 0x0002 3690 #define PG2 0x0004 3691 #define PG3 0x0008 3692 #define PG4 0x0010 3693 #define PG5 0x0020 3694 #define PG6 0x0040 3695 #define PG7 0x0080 3696 #define PG8 0x0100 3697 #define PG9 0x0200 3698 #define PG10 0x0400 3699 #define PG11 0x0800 3700 #define PG12 0x1000 3701 #define PG13 0x2000 3702 #define PG14 0x4000 3703 #define PG15 0x8000 3704 3705 /* PORT H Bit Definitions for the registers 3706 PORTH, PORTH_SET, PORTH_CLEAR, 3707 PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN, 3708 PORTH_FER registers 3709 */ 3710 3711 3712 #define PH0 0x0001 3713 #define PH1 0x0002 3714 #define PH2 0x0004 3715 #define PH3 0x0008 3716 #define PH4 0x0010 3717 #define PH5 0x0020 3718 #define PH6 0x0040 3719 #define PH7 0x0080 3720 #define PH8 0x0100 3721 #define PH9 0x0200 3722 #define PH10 0x0400 3723 #define PH11 0x0800 3724 #define PH12 0x1000 3725 #define PH13 0x2000 3726 3727 3728 /* PORT I Bit Definitions for the registers 3729 PORTI, PORTI_SET, PORTI_CLEAR, 3730 PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN, 3731 PORTI_FER registers 3732 */ 3733 3734 3735 #define PI0 0x0001 3736 #define PI1 0x0002 3737 #define PI2 0x0004 3738 #define PI3 0x0008 3739 #define PI4 0x0010 3740 #define PI5 0x0020 3741 #define PI6 0x0040 3742 #define PI7 0x0080 3743 #define PI8 0x0100 3744 #define PI9 0x0200 3745 #define PI10 0x0400 3746 #define PI11 0x0800 3747 #define PI12 0x1000 3748 #define PI13 0x2000 3749 #define PI14 0x4000 3750 #define PI15 0x8000 3751 3752 /* PORT J Bit Definitions for the registers 3753 PORTJ, PORTJ_SET, PORTJ_CLEAR, 3754 PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN, 3755 PORTJ_FER registers 3756 */ 3757 3758 3759 #define PJ0 0x0001 3760 #define PJ1 0x0002 3761 #define PJ2 0x0004 3762 #define PJ3 0x0008 3763 #define PJ4 0x0010 3764 #define PJ5 0x0020 3765 #define PJ6 0x0040 3766 #define PJ7 0x0080 3767 #define PJ8 0x0100 3768 #define PJ9 0x0200 3769 #define PJ10 0x0400 3770 #define PJ11 0x0800 3771 #define PJ12 0x1000 3772 #define PJ13 0x2000 3773 3774 3775 /* Port Muxing Bit Fields for PORTx_MUX Registers */ 3776 3777 #define MUX0 0x00000003 3778 #define MUX0_0 0x00000000 3779 #define MUX0_1 0x00000001 3780 #define MUX0_2 0x00000002 3781 #define MUX0_3 0x00000003 3782 3783 #define MUX1 0x0000000C 3784 #define MUX1_0 0x00000000 3785 #define MUX1_1 0x00000004 3786 #define MUX1_2 0x00000008 3787 #define MUX1_3 0x0000000C 3788 3789 #define MUX2 0x00000030 3790 #define MUX2_0 0x00000000 3791 #define MUX2_1 0x00000010 3792 #define MUX2_2 0x00000020 3793 #define MUX2_3 0x00000030 3794 3795 #define MUX3 0x000000C0 3796 #define MUX3_0 0x00000000 3797 #define MUX3_1 0x00000040 3798 #define MUX3_2 0x00000080 3799 #define MUX3_3 0x000000C0 3800 3801 #define MUX4 0x00000300 3802 #define MUX4_0 0x00000000 3803 #define MUX4_1 0x00000100 3804 #define MUX4_2 0x00000200 3805 #define MUX4_3 0x00000300 3806 3807 #define MUX5 0x00000C00 3808 #define MUX5_0 0x00000000 3809 #define MUX5_1 0x00000400 3810 #define MUX5_2 0x00000800 3811 #define MUX5_3 0x00000C00 3812 3813 #define MUX6 0x00003000 3814 #define MUX6_0 0x00000000 3815 #define MUX6_1 0x00001000 3816 #define MUX6_2 0x00002000 3817 #define MUX6_3 0x00003000 3818 3819 #define MUX7 0x0000C000 3820 #define MUX7_0 0x00000000 3821 #define MUX7_1 0x00004000 3822 #define MUX7_2 0x00008000 3823 #define MUX7_3 0x0000C000 3824 3825 #define MUX8 0x00030000 3826 #define MUX8_0 0x00000000 3827 #define MUX8_1 0x00010000 3828 #define MUX8_2 0x00020000 3829 #define MUX8_3 0x00030000 3830 3831 #define MUX9 0x000C0000 3832 #define MUX9_0 0x00000000 3833 #define MUX9_1 0x00040000 3834 #define MUX9_2 0x00080000 3835 #define MUX9_3 0x000C0000 3836 3837 #define MUX10 0x00300000 3838 #define MUX10_0 0x00000000 3839 #define MUX10_1 0x00100000 3840 #define MUX10_2 0x00200000 3841 #define MUX10_3 0x00300000 3842 3843 #define MUX11 0x00C00000 3844 #define MUX11_0 0x00000000 3845 #define MUX11_1 0x00400000 3846 #define MUX11_2 0x00800000 3847 #define MUX11_3 0x00C00000 3848 3849 #define MUX12 0x03000000 3850 #define MUX12_0 0x00000000 3851 #define MUX12_1 0x01000000 3852 #define MUX12_2 0x02000000 3853 #define MUX12_3 0x03000000 3854 3855 #define MUX13 0x0C000000 3856 #define MUX13_0 0x00000000 3857 #define MUX13_1 0x04000000 3858 #define MUX13_2 0x08000000 3859 #define MUX13_3 0x0C000000 3860 3861 #define MUX14 0x30000000 3862 #define MUX14_0 0x00000000 3863 #define MUX14_1 0x10000000 3864 #define MUX14_2 0x20000000 3865 #define MUX14_3 0x30000000 3866 3867 #define MUX15 0xC0000000 3868 #define MUX15_0 0x00000000 3869 #define MUX15_1 0x40000000 3870 #define MUX15_2 0x80000000 3871 #define MUX15_3 0xC0000000 3872 3873 #define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \ 3874 ((((b15)&3) << 30) | \ 3875 (((b14)&3) << 28) | \ 3876 (((b13)&3) << 26) | \ 3877 (((b12)&3) << 24) | \ 3878 (((b11)&3) << 22) | \ 3879 (((b10)&3) << 20) | \ 3880 (((b9) &3) << 18) | \ 3881 (((b8) &3) << 16) | \ 3882 (((b7) &3) << 14) | \ 3883 (((b6) &3) << 12) | \ 3884 (((b5) &3) << 10) | \ 3885 (((b4) &3) << 8) | \ 3886 (((b3) &3) << 6) | \ 3887 (((b2) &3) << 4) | \ 3888 (((b1) &3) << 2) | \ 3889 (((b0) &3))) 3890 3891 /* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */ 3892 3893 #define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */ 3894 #define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */ 3895 #define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */ 3896 #define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */ 3897 #define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */ 3898 #define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */ 3899 #define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */ 3900 #define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */ 3901 #define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */ 3902 #define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */ 3903 #define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */ 3904 #define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */ 3905 3906 /* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */ 3907 3908 #define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */ 3909 #define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */ 3910 #define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */ 3911 #define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */ 3912 #define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */ 3913 #define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */ 3914 #define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */ 3915 #define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */ 3916 3917 #define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ 3918 #define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */ 3919 #define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */ 3920 #define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */ 3921 #define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */ 3922 #define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */ 3923 #define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */ 3924 #define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */ 3925 3926 #define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ 3927 #define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ 3928 #define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ 3929 #define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ 3930 #define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ 3931 #define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ 3932 #define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ 3933 #define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ 3934 3935 #define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ 3936 #define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ 3937 #define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ 3938 #define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ 3939 #define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ 3940 #define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ 3941 #define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ 3942 #define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ 3943 3944 3945 /* for legacy compatibility */ 3946 3947 #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ 3948 #define W1LMAX_MAX W1LMAX_MIN 3949 #define EBIU_AMCBCTL0 EBIU_AMBCTL0 3950 #define EBIU_AMCBCTL1 EBIU_AMBCTL1 3951 #define PINT0_IRQ PINT0_REQUEST 3952 #define PINT1_IRQ PINT1_REQUEST 3953 #define PINT2_IRQ PINT2_REQUEST 3954 #define PINT3_IRQ PINT3_REQUEST 3955 3956 #endif /* _DEF_BF54X_H */ 3957