1comment "Processor Type" 2 3config CPU_32 4 bool 5 default y 6 7# Select CPU types depending on the architecture selected. This selects 8# which CPUs we support in the kernel image, and the compiler instruction 9# optimiser behaviour. 10 11# ARM610 12config CPU_ARM610 13 bool "Support ARM610 processor" if ARCH_RPC 14 select CPU_32v3 15 select CPU_CACHE_V3 16 select CPU_CACHE_VIVT 17 select CPU_CP15_MMU 18 select CPU_COPY_V3 if MMU 19 select CPU_TLB_V3 if MMU 20 select CPU_PABRT_NOIFAR 21 help 22 The ARM610 is the successor to the ARM3 processor 23 and was produced by VLSI Technology Inc. 24 25 Say Y if you want support for the ARM610 processor. 26 Otherwise, say N. 27 28# ARM7TDMI 29config CPU_ARM7TDMI 30 bool "Support ARM7TDMI processor" 31 depends on !MMU 32 select CPU_32v4T 33 select CPU_ABRT_LV4T 34 select CPU_PABRT_NOIFAR 35 select CPU_CACHE_V4 36 help 37 A 32-bit RISC microprocessor based on the ARM7 processor core 38 which has no memory control unit and cache. 39 40 Say Y if you want support for the ARM7TDMI processor. 41 Otherwise, say N. 42 43# ARM710 44config CPU_ARM710 45 bool "Support ARM710 processor" if ARCH_RPC 46 select CPU_32v3 47 select CPU_CACHE_V3 48 select CPU_CACHE_VIVT 49 select CPU_CP15_MMU 50 select CPU_COPY_V3 if MMU 51 select CPU_TLB_V3 if MMU 52 select CPU_PABRT_NOIFAR 53 help 54 A 32-bit RISC microprocessor based on the ARM7 processor core 55 designed by Advanced RISC Machines Ltd. The ARM710 is the 56 successor to the ARM610 processor. It was released in 57 July 1994 by VLSI Technology Inc. 58 59 Say Y if you want support for the ARM710 processor. 60 Otherwise, say N. 61 62# ARM720T 63config CPU_ARM720T 64 bool "Support ARM720T processor" if ARCH_INTEGRATOR 65 select CPU_32v4T 66 select CPU_ABRT_LV4T 67 select CPU_PABRT_NOIFAR 68 select CPU_CACHE_V4 69 select CPU_CACHE_VIVT 70 select CPU_CP15_MMU 71 select CPU_COPY_V4WT if MMU 72 select CPU_TLB_V4WT if MMU 73 help 74 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 75 MMU built around an ARM7TDMI core. 76 77 Say Y if you want support for the ARM720T processor. 78 Otherwise, say N. 79 80# ARM740T 81config CPU_ARM740T 82 bool "Support ARM740T processor" if ARCH_INTEGRATOR 83 depends on !MMU 84 select CPU_32v4T 85 select CPU_ABRT_LV4T 86 select CPU_PABRT_NOIFAR 87 select CPU_CACHE_V3 # although the core is v4t 88 select CPU_CP15_MPU 89 help 90 A 32-bit RISC processor with 8KB cache or 4KB variants, 91 write buffer and MPU(Protection Unit) built around 92 an ARM7TDMI core. 93 94 Say Y if you want support for the ARM740T processor. 95 Otherwise, say N. 96 97# ARM9TDMI 98config CPU_ARM9TDMI 99 bool "Support ARM9TDMI processor" 100 depends on !MMU 101 select CPU_32v4T 102 select CPU_ABRT_NOMMU 103 select CPU_PABRT_NOIFAR 104 select CPU_CACHE_V4 105 help 106 A 32-bit RISC microprocessor based on the ARM9 processor core 107 which has no memory control unit and cache. 108 109 Say Y if you want support for the ARM9TDMI processor. 110 Otherwise, say N. 111 112# ARM920T 113config CPU_ARM920T 114 bool "Support ARM920T processor" if ARCH_INTEGRATOR 115 select CPU_32v4T 116 select CPU_ABRT_EV4T 117 select CPU_PABRT_NOIFAR 118 select CPU_CACHE_V4WT 119 select CPU_CACHE_VIVT 120 select CPU_CP15_MMU 121 select CPU_COPY_V4WB if MMU 122 select CPU_TLB_V4WBI if MMU 123 help 124 The ARM920T is licensed to be produced by numerous vendors, 125 and is used in the Maverick EP9312 and the Samsung S3C2410. 126 127 More information on the Maverick EP9312 at 128 <http://linuxdevices.com/products/PD2382866068.html>. 129 130 Say Y if you want support for the ARM920T processor. 131 Otherwise, say N. 132 133# ARM922T 134config CPU_ARM922T 135 bool "Support ARM922T processor" if ARCH_INTEGRATOR 136 select CPU_32v4T 137 select CPU_ABRT_EV4T 138 select CPU_PABRT_NOIFAR 139 select CPU_CACHE_V4WT 140 select CPU_CACHE_VIVT 141 select CPU_CP15_MMU 142 select CPU_COPY_V4WB if MMU 143 select CPU_TLB_V4WBI if MMU 144 help 145 The ARM922T is a version of the ARM920T, but with smaller 146 instruction and data caches. It is used in Altera's 147 Excalibur XA device family and Micrel's KS8695 Centaur. 148 149 Say Y if you want support for the ARM922T processor. 150 Otherwise, say N. 151 152# ARM925T 153config CPU_ARM925T 154 bool "Support ARM925T processor" if ARCH_OMAP1 155 select CPU_32v4T 156 select CPU_ABRT_EV4T 157 select CPU_PABRT_NOIFAR 158 select CPU_CACHE_V4WT 159 select CPU_CACHE_VIVT 160 select CPU_CP15_MMU 161 select CPU_COPY_V4WB if MMU 162 select CPU_TLB_V4WBI if MMU 163 help 164 The ARM925T is a mix between the ARM920T and ARM926T, but with 165 different instruction and data caches. It is used in TI's OMAP 166 device family. 167 168 Say Y if you want support for the ARM925T processor. 169 Otherwise, say N. 170 171# ARM926T 172config CPU_ARM926T 173 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 174 select CPU_32v5 175 select CPU_ABRT_EV5TJ 176 select CPU_PABRT_NOIFAR 177 select CPU_CACHE_VIVT 178 select CPU_CP15_MMU 179 select CPU_COPY_V4WB if MMU 180 select CPU_TLB_V4WBI if MMU 181 help 182 This is a variant of the ARM920. It has slightly different 183 instruction sequences for cache and TLB operations. Curiously, 184 there is no documentation on it at the ARM corporate website. 185 186 Say Y if you want support for the ARM926T processor. 187 Otherwise, say N. 188 189# ARM940T 190config CPU_ARM940T 191 bool "Support ARM940T processor" if ARCH_INTEGRATOR 192 depends on !MMU 193 select CPU_32v4T 194 select CPU_ABRT_NOMMU 195 select CPU_PABRT_NOIFAR 196 select CPU_CACHE_VIVT 197 select CPU_CP15_MPU 198 help 199 ARM940T is a member of the ARM9TDMI family of general- 200 purpose microprocessors with MPU and separate 4KB 201 instruction and 4KB data cases, each with a 4-word line 202 length. 203 204 Say Y if you want support for the ARM940T processor. 205 Otherwise, say N. 206 207# ARM946E-S 208config CPU_ARM946E 209 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR 210 depends on !MMU 211 select CPU_32v5 212 select CPU_ABRT_NOMMU 213 select CPU_PABRT_NOIFAR 214 select CPU_CACHE_VIVT 215 select CPU_CP15_MPU 216 help 217 ARM946E-S is a member of the ARM9E-S family of high- 218 performance, 32-bit system-on-chip processor solutions. 219 The TCM and ARMv5TE 32-bit instruction set is supported. 220 221 Say Y if you want support for the ARM946E-S processor. 222 Otherwise, say N. 223 224# ARM1020 - needs validating 225config CPU_ARM1020 226 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR 227 select CPU_32v5 228 select CPU_ABRT_EV4T 229 select CPU_PABRT_NOIFAR 230 select CPU_CACHE_V4WT 231 select CPU_CACHE_VIVT 232 select CPU_CP15_MMU 233 select CPU_COPY_V4WB if MMU 234 select CPU_TLB_V4WBI if MMU 235 help 236 The ARM1020 is the 32K cached version of the ARM10 processor, 237 with an addition of a floating-point unit. 238 239 Say Y if you want support for the ARM1020 processor. 240 Otherwise, say N. 241 242# ARM1020E - needs validating 243config CPU_ARM1020E 244 bool "Support ARM1020E processor" if ARCH_INTEGRATOR 245 select CPU_32v5 246 select CPU_ABRT_EV4T 247 select CPU_PABRT_NOIFAR 248 select CPU_CACHE_V4WT 249 select CPU_CACHE_VIVT 250 select CPU_CP15_MMU 251 select CPU_COPY_V4WB if MMU 252 select CPU_TLB_V4WBI if MMU 253 depends on n 254 255# ARM1022E 256config CPU_ARM1022 257 bool "Support ARM1022E processor" if ARCH_INTEGRATOR 258 select CPU_32v5 259 select CPU_ABRT_EV4T 260 select CPU_PABRT_NOIFAR 261 select CPU_CACHE_VIVT 262 select CPU_CP15_MMU 263 select CPU_COPY_V4WB if MMU # can probably do better 264 select CPU_TLB_V4WBI if MMU 265 help 266 The ARM1022E is an implementation of the ARMv5TE architecture 267 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 268 embedded trace macrocell, and a floating-point unit. 269 270 Say Y if you want support for the ARM1022E processor. 271 Otherwise, say N. 272 273# ARM1026EJ-S 274config CPU_ARM1026 275 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR 276 select CPU_32v5 277 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 278 select CPU_PABRT_NOIFAR 279 select CPU_CACHE_VIVT 280 select CPU_CP15_MMU 281 select CPU_COPY_V4WB if MMU # can probably do better 282 select CPU_TLB_V4WBI if MMU 283 help 284 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 285 based upon the ARM10 integer core. 286 287 Say Y if you want support for the ARM1026EJ-S processor. 288 Otherwise, say N. 289 290# SA110 291config CPU_SA110 292 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC 293 select CPU_32v3 if ARCH_RPC 294 select CPU_32v4 if !ARCH_RPC 295 select CPU_ABRT_EV4 296 select CPU_PABRT_NOIFAR 297 select CPU_CACHE_V4WB 298 select CPU_CACHE_VIVT 299 select CPU_CP15_MMU 300 select CPU_COPY_V4WB if MMU 301 select CPU_TLB_V4WB if MMU 302 help 303 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 304 is available at five speeds ranging from 100 MHz to 233 MHz. 305 More information is available at 306 <http://developer.intel.com/design/strong/sa110.htm>. 307 308 Say Y if you want support for the SA-110 processor. 309 Otherwise, say N. 310 311# SA1100 312config CPU_SA1100 313 bool 314 select CPU_32v4 315 select CPU_ABRT_EV4 316 select CPU_PABRT_NOIFAR 317 select CPU_CACHE_V4WB 318 select CPU_CACHE_VIVT 319 select CPU_CP15_MMU 320 select CPU_TLB_V4WB if MMU 321 322# XScale 323config CPU_XSCALE 324 bool 325 select CPU_32v5 326 select CPU_ABRT_EV5T 327 select CPU_PABRT_NOIFAR 328 select CPU_CACHE_VIVT 329 select CPU_CP15_MMU 330 select CPU_TLB_V4WBI if MMU 331 332# XScale Core Version 3 333config CPU_XSC3 334 bool 335 select CPU_32v5 336 select CPU_ABRT_EV5T 337 select CPU_PABRT_NOIFAR 338 select CPU_CACHE_VIVT 339 select CPU_CP15_MMU 340 select CPU_TLB_V4WBI if MMU 341 select IO_36 342 343# Feroceon 344config CPU_FEROCEON 345 bool 346 select CPU_32v5 347 select CPU_ABRT_EV5T 348 select CPU_PABRT_NOIFAR 349 select CPU_CACHE_VIVT 350 select CPU_CP15_MMU 351 select CPU_COPY_FEROCEON if MMU 352 select CPU_TLB_FEROCEON if MMU 353 354config CPU_FEROCEON_OLD_ID 355 bool "Accept early Feroceon cores with an ARM926 ID" 356 depends on CPU_FEROCEON && !CPU_ARM926T 357 default y 358 help 359 This enables the usage of some old Feroceon cores 360 for which the CPU ID is equal to the ARM926 ID. 361 Relevant for Feroceon-1850 and early Feroceon-2850. 362 363# ARMv6 364config CPU_V6 365 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 366 select CPU_32v6 367 select CPU_ABRT_EV6 368 select CPU_PABRT_NOIFAR 369 select CPU_CACHE_V6 370 select CPU_CACHE_VIPT 371 select CPU_CP15_MMU 372 select CPU_HAS_ASID if MMU 373 select CPU_COPY_V6 if MMU 374 select CPU_TLB_V6 if MMU 375 376# ARMv6k 377config CPU_32v6K 378 bool "Support ARM V6K processor extensions" if !SMP 379 depends on CPU_V6 380 default y if SMP && !ARCH_MX3 381 help 382 Say Y here if your ARMv6 processor supports the 'K' extension. 383 This enables the kernel to use some instructions not present 384 on previous processors, and as such a kernel build with this 385 enabled will not boot on processors with do not support these 386 instructions. 387 388# ARMv7 389config CPU_V7 390 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 391 select CPU_32v6K 392 select CPU_32v7 393 select CPU_ABRT_EV7 394 select CPU_PABRT_IFAR 395 select CPU_CACHE_V7 396 select CPU_CACHE_VIPT 397 select CPU_CP15_MMU 398 select CPU_HAS_ASID if MMU 399 select CPU_COPY_V6 if MMU 400 select CPU_TLB_V7 if MMU 401 402# Figure out what processor architecture version we should be using. 403# This defines the compiler instruction set which depends on the machine type. 404config CPU_32v3 405 bool 406 select TLS_REG_EMUL if SMP || !MMU 407 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 408 409config CPU_32v4 410 bool 411 select TLS_REG_EMUL if SMP || !MMU 412 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 413 414config CPU_32v4T 415 bool 416 select TLS_REG_EMUL if SMP || !MMU 417 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 418 419config CPU_32v5 420 bool 421 select TLS_REG_EMUL if SMP || !MMU 422 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 423 424config CPU_32v6 425 bool 426 select TLS_REG_EMUL if !CPU_32v6K && !MMU 427 428config CPU_32v7 429 bool 430 431# The abort model 432config CPU_ABRT_NOMMU 433 bool 434 435config CPU_ABRT_EV4 436 bool 437 438config CPU_ABRT_EV4T 439 bool 440 441config CPU_ABRT_LV4T 442 bool 443 444config CPU_ABRT_EV5T 445 bool 446 447config CPU_ABRT_EV5TJ 448 bool 449 450config CPU_ABRT_EV6 451 bool 452 453config CPU_ABRT_EV7 454 bool 455 456config CPU_PABRT_IFAR 457 bool 458 459config CPU_PABRT_NOIFAR 460 bool 461 462# The cache model 463config CPU_CACHE_V3 464 bool 465 466config CPU_CACHE_V4 467 bool 468 469config CPU_CACHE_V4WT 470 bool 471 472config CPU_CACHE_V4WB 473 bool 474 475config CPU_CACHE_V6 476 bool 477 478config CPU_CACHE_V7 479 bool 480 481config CPU_CACHE_VIVT 482 bool 483 484config CPU_CACHE_VIPT 485 bool 486 487if MMU 488# The copy-page model 489config CPU_COPY_V3 490 bool 491 492config CPU_COPY_V4WT 493 bool 494 495config CPU_COPY_V4WB 496 bool 497 498config CPU_COPY_FEROCEON 499 bool 500 501config CPU_COPY_V6 502 bool 503 504# This selects the TLB model 505config CPU_TLB_V3 506 bool 507 help 508 ARM Architecture Version 3 TLB. 509 510config CPU_TLB_V4WT 511 bool 512 help 513 ARM Architecture Version 4 TLB with writethrough cache. 514 515config CPU_TLB_V4WB 516 bool 517 help 518 ARM Architecture Version 4 TLB with writeback cache. 519 520config CPU_TLB_V4WBI 521 bool 522 help 523 ARM Architecture Version 4 TLB with writeback cache and invalidate 524 instruction cache entry. 525 526config CPU_TLB_FEROCEON 527 bool 528 help 529 Feroceon TLB (v4wbi with non-outer-cachable page table walks). 530 531config CPU_TLB_V6 532 bool 533 534config CPU_TLB_V7 535 bool 536 537endif 538 539config CPU_HAS_ASID 540 bool 541 help 542 This indicates whether the CPU has the ASID register; used to 543 tag TLB and possibly cache entries. 544 545config CPU_CP15 546 bool 547 help 548 Processor has the CP15 register. 549 550config CPU_CP15_MMU 551 bool 552 select CPU_CP15 553 help 554 Processor has the CP15 register, which has MMU related registers. 555 556config CPU_CP15_MPU 557 bool 558 select CPU_CP15 559 help 560 Processor has the CP15 register, which has MPU related registers. 561 562# 563# CPU supports 36-bit I/O 564# 565config IO_36 566 bool 567 568comment "Processor Features" 569 570config ARM_THUMB 571 bool "Support Thumb user binaries" 572 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON 573 default y 574 help 575 Say Y if you want to include kernel support for running user space 576 Thumb binaries. 577 578 The Thumb instruction set is a compressed form of the standard ARM 579 instruction set resulting in smaller binaries at the expense of 580 slightly less efficient code. 581 582 If you don't know what this all is, saying Y is a safe choice. 583 584config ARM_THUMBEE 585 bool "Enable ThumbEE CPU extension" 586 depends on CPU_V7 587 help 588 Say Y here if you have a CPU with the ThumbEE extension and code to 589 make use of it. Say N for code that can run on CPUs without ThumbEE. 590 591config CPU_BIG_ENDIAN 592 bool "Build big-endian kernel" 593 depends on ARCH_SUPPORTS_BIG_ENDIAN 594 help 595 Say Y if you plan on running a kernel in big-endian mode. 596 Note that your board must be properly built and your board 597 port must properly enable any big-endian related features 598 of your chipset/board/processor. 599 600config CPU_HIGH_VECTOR 601 depends on !MMU && CPU_CP15 && !CPU_ARM740T 602 bool "Select the High exception vector" 603 default n 604 help 605 Say Y here to select high exception vector(0xFFFF0000~). 606 The exception vector can be vary depending on the platform 607 design in nommu mode. If your platform needs to select 608 high exception vector, say Y. 609 Otherwise or if you are unsure, say N, and the low exception 610 vector (0x00000000~) will be used. 611 612config CPU_ICACHE_DISABLE 613 bool "Disable I-Cache (I-bit)" 614 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 615 help 616 Say Y here to disable the processor instruction cache. Unless 617 you have a reason not to or are unsure, say N. 618 619config CPU_DCACHE_DISABLE 620 bool "Disable D-Cache (C-bit)" 621 depends on CPU_CP15 622 help 623 Say Y here to disable the processor data cache. Unless 624 you have a reason not to or are unsure, say N. 625 626config CPU_DCACHE_SIZE 627 hex 628 depends on CPU_ARM740T || CPU_ARM946E 629 default 0x00001000 if CPU_ARM740T 630 default 0x00002000 # default size for ARM946E-S 631 help 632 Some cores are synthesizable to have various sized cache. For 633 ARM946E-S case, it can vary from 0KB to 1MB. 634 To support such cache operations, it is efficient to know the size 635 before compile time. 636 If your SoC is configured to have a different size, define the value 637 here with proper conditions. 638 639config CPU_DCACHE_WRITETHROUGH 640 bool "Force write through D-cache" 641 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE 642 default y if CPU_ARM925T 643 help 644 Say Y here to use the data cache in writethrough mode. Unless you 645 specifically require this or are unsure, say N. 646 647config CPU_CACHE_ROUND_ROBIN 648 bool "Round robin I and D cache replacement algorithm" 649 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 650 help 651 Say Y here to use the predictable round-robin cache replacement 652 policy. Unless you specifically require this or are unsure, say N. 653 654config CPU_BPREDICT_DISABLE 655 bool "Disable branch prediction" 656 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 657 help 658 Say Y here to disable branch prediction. If unsure, say N. 659 660config TLS_REG_EMUL 661 bool 662 help 663 An SMP system using a pre-ARMv6 processor (there are apparently 664 a few prototypes like that in existence) and therefore access to 665 that required register must be emulated. 666 667config HAS_TLS_REG 668 bool 669 depends on !TLS_REG_EMUL 670 default y if SMP || CPU_32v7 671 help 672 This selects support for the CP15 thread register. 673 It is defined to be available on some ARMv6 processors (including 674 all SMP capable ARMv6's) or later processors. User space may 675 assume directly accessing that register and always obtain the 676 expected value only on ARMv7 and above. 677 678config NEEDS_SYSCALL_FOR_CMPXCHG 679 bool 680 help 681 SMP on a pre-ARMv6 processor? Well OK then. 682 Forget about fast user space cmpxchg support. 683 It is just not possible. 684 685config OUTER_CACHE 686 bool 687 default n 688 689config CACHE_FEROCEON_L2 690 bool "Enable the Feroceon L2 cache controller" 691 depends on ARCH_KIRKWOOD || ARCH_MV78XX0 692 default y 693 select OUTER_CACHE 694 help 695 This option enables the Feroceon L2 cache controller. 696 697config CACHE_FEROCEON_L2_WRITETHROUGH 698 bool "Force Feroceon L2 cache write through" 699 depends on CACHE_FEROCEON_L2 700 default n 701 help 702 Say Y here to use the Feroceon L2 cache in writethrough mode. 703 Unless you specifically require this, say N for writeback mode. 704 705config CACHE_L2X0 706 bool "Enable the L2x0 outer cache controller" 707 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP 708 default y 709 select OUTER_CACHE 710 help 711 This option enables the L2x0 PrimeCell. 712 713config CACHE_XSC3L2 714 bool "Enable the L2 cache on XScale3" 715 depends on CPU_XSC3 716 default y 717 select OUTER_CACHE 718 help 719 This option enables the L2 cache on XScale3. 720 721config ARM_L1_CACHE_SHIFT 722 int 723 default 6 if ARCH_OMAP3 724 default 5 725